CY62167EV18

CY62167EV18 MoBL® 16 Mbit (1M x 16) Static RAM 16 Mbit (1M x 16) Static RAM Features ■ ■ ■ Very high speed: 55 ns Wide voltage range: 1.65 V to 2.25 V Ultra low standby power ❐ Typical standby current: 1.5 A ❐ Maximum standby current: 12 A Ultra low active power ❐ Typical active current: 2.2 mA at f = 1 MHz Easy memory expansion with CE1, CE2, and OE features Automatic power down when deselected CMOS for optimum speed and power Offered in Pb-free 48-ball very fine ball grid array (VFBGA) packages automatic power down feature that reduces power consumption by 99 percent when addresses are not toggling. Place the device into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input and output pins (I/O0 through I/O15) are placed in a high impedance state when: the device is deselected (CE1HIGH or CE2 LOW); outputs are disabled (OE HIGH); both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH); and a write operation is in progress (CE1 LOW, CE2 HIGH and WE LOW). To write to the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19). To read from the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. See the Truth Table on page 10 for a complete description of read and write modes. ■ ■ ■ ■ ■ Functional Description The CY62167EV18 is a high performance CMOS static RAM organized as 1M words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life (MoBL®) in portable applications such as cellular telephones. The device also has an Logic Block Diagram DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER 1M × 16 RAM ARRAY SENSE AMPS I/O0–I/O7 I/O8–I/O15 COLUMN DECODER BHE CE2 Power Down Circuit CE1 BHE BLE A11 A12 A13 A14 A15 A16 A17 A18 A19 WE OE BLE CE2 CE1 Cypress Semiconductor Corporation Document #: 38-05447 Rev. *L • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 29, 2011 CY62167EV18 MoBL® Contents Pin Configuration ............................................................. 3 Product Portfolio .............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 4 Thermal Resistance .......................................................... 5 Data Retention Characteristics ....................................... 5 Switching Characteristics ................................................ 6 Switching Waveforms ...................................................... 7 Truth Table ...................................................................... 10 Ordering Information ...................................................... 11 Ordering Code Definition ........................................... 11 Package Diagrams .......................................................... 12 Acronyms ........................................................................ 14 Document Conventions ................................................. 14 Units of Measure ....................................................... 14 Document History Page ................................................. 15 Sales, Solutions, and Legal Information ...................... 16 Worldwide Sales and Design Support ....................... 16 Products .................................................................... 16 PSoC Solutions ......................................................... 16 Document #: 38-05447 Rev. *L Page 2 of 16 CY62167EV18 MoBL® Pin Configuration Figure 1. 48-Ball VFBGA (6 × 8 × 1 mm) Top View [ 1, 2] 1 BLE I/O8 I/O9 VSS VCC I/O14 I/O15 A18 2 OE BHE I/O10 I/O11 I/O12 I/O13 A19 A8 3 A0 A3 A5 A17 NC A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE1 I/O1 I/O3 I/O4 I/O5 WE A11 6 CE2 I/O0 I/O2 Vcc Vss I/O6 I/O7 NC A B C D E F G H Product Portfolio Power Dissipation Product VCC Range (V) Typ[3] 1.8 Speed (ns) Max 2.25 55 Typ[3] 2.2 Operating ICC (mA) f = 1 MHz Min CY62167EV18LL CY62167EV30LL [4] f = fmax Typ[3] 25 Max 30 Standby ISB2 (A) Typ[3] 1.5 Max 12 Max 4.0 1.65 Notes 1. NC pins are not connected on the die. 2. Ball H6 for the VFBGA package can be used to upgrade to a 32 M density. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 4. This part can be operated in the VCC range of 1.65 V–2.25 V at 55ns speed. It can also be operated in the VCC range of 2.2 V–3.6 V at 45ns speed. Document #: 38-05447 Rev. *L Page 3 of 16 CY62167EV18 MoBL® DC input voltage[5, 6]..... –0.2 V to 2.45 V (VCC(max) + 0.2 V) Output current into outputs (LOW) ............................. 20 mA Static discharge voltage........................................... >2001 V (MIL-STD-883, Method 3015) Latch up current....................................................... >200 mA Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature ............................... –65 °C to + 150 °C Ambient temperature with power applied .......................................... –55 °C to + 125 °C Supply voltage to ground potential ....................... –0.2 V to 2.45 V (VCC (max) + 0.2 V) DC voltage applied to outputs in High Z state[5, 6] ....... –0.2 V to 2.45 V (VCC (max) + 0.2 V) Operating Range Device CY62167EV18LL Range Industrial Ambient Temperature –40 °C to +85 °C VCC[7] 1.65 V to 2.25 V Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage Input leakage current Output leakage current VCC operating supply current Automatic power down current – CMOS inputs Test Conditions IOH = –0.1 mA IOL = 0.1 mA VCC = 1.65 V to 2.25 V VCC = 1.65 V to 2.25 V GND < VI < VCC GND < VO < VCC, Output Disabled f = fmax = 1/tRC f = 1 MHz VCC = VCC(max) IOUT = 0 mA CMOS levels 55 ns Min 1.4 – 1.4 –0.2 –1 –1 – – – Typ[8] – – – – – – 25 2.2 1.5 Max – 0.2 VCC + 0.2 V 0.4 +1 +1 30 4.0 12 Unit V V V V A A mA mA A ISB1[9] CE1 > VCC – 0.2 V or CE2 < 0.2 V or (BHE and BLE) > VCC – 0.2 V, VIN > VCC – 0.2V, VIN < 0.2 V) f = fmax (address and data only), f = 0 (OE, and WE), VCC = VCC (max) CE1 > VCC  0.2 V or CE2 < 0.2 V, VIN > VCC  0.2 V or VIN < 0.2 V, or (BHE and BLE) > VCC – 0.2 V, f = 0, VCC = VCC (max) ISB2[9] Automatic power down current – CMOS inputs – 1.5 12 A Capacitance Parameter[10] CIN COUT Description Input capacitance Output capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = VCC(typ) Max 10 10 Unit pF pF Notes 5. VIL(min) = –2.0 V for pulse durations less than 20 ns. 6. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns. 7. Full Device AC operation is based on a 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization. 8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 9. Chip enables (CE1 and CE2), and byte enables (BHE and BLE) must be tied to CMOS levels to meet the ISB1 /ISB2 / ICCDR spec. Other inputs can be left floating. 10. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05447 Rev. *L Page 4 of 16 CY62167EV18 MoBL® Thermal Resistance Parameter[11] JA JC Description Thermal resistance (Junction to ambient) Thermal resistance (Junction to case) Figure 2. AC Test Loads and Waveforms R1 VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 VCC GND 10% ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Test Conditions Still air, soldered on a 3 × 4.5 inch, two-layer printed circuit board VFBGA (6 × 8 × 1mm) 55 16 Unit C/W C/W Rise Time = 1 V/ns Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT V Parameters R1 R2 RTH VTH 1.8 V 13500 10800 6000 0.80 Unit    V Data Retention Characteristics Over the Operating Range Parameter VDR ICCDR[13] tCDR[11] tR[14] Description VCC for data retention Data retention current Chip deselect to data retention time Operation recovery time Figure 3. Data Retention Waveform DATA RETENTION MODE VDR > 1.0 V VCC(min) tR VCC = 1.0 V, CE1 > VCC – 0.2 V or CE2 < 0.2 V or (BHE and BLE) > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V Conditions Min 1.0 – 0 55 Typ[12] – – – – Max – 10 – – Unit V A ns ns VCC CE1 or BHE.BLE [15] VCC(min) tCDR or CE2 Notes 11. Tested initially and after any design or process changes that may affect these parameters. 12. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 13. Chip enables (CE1 and CE2), and byte enables (BHE and BLE) must be tied to CMOS levels to meet the ISB1 /ISB2 / ICCDR spec. Other inputs can be left floating. 14. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. 15. BHE. BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE. Document #: 38-05447 Rev. *L Page 5 of 16 CY62167EV18 MoBL® Switching Characteristics Parameter[16, 17] Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE [20] Description 55 ns Min Max Unit Read cycle time Address to data valid Data hold from address change CE1 LOW and CE2 HIGH to data valid OE LOW to data valid OE LOW to Low Z OE HIGH to High [18] 55 – 10 – – 5 – Z[18] Z[18, 19] 10 – 0 – – 10 – – 55 – 55 25 – 18 – 18 – 55 55 – 18 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Z[18, 19] CE1 LOW and CE2 HIGH to Low CE1 HIGH and CE2 LOW to High CE1 LOW and CE2 HIGH to power-up CE1 HIGH and CE2 LOW to Power-down BLE/BHE LOW to data valid BLE/BHE LOW to Low Z[18] BLE/BHE HIGH to High Z[18, 19] Write cycle time CE1 LOW and CE2 HIGH to write end Address setup to write end Address hold from write end Address setup to write start WE pulse Width BLE/BHE LOW to write end Data setup to write end Data hold from write end WE LOW to High WE HIGH to Low Z[18, 19] Z[18] 55 40 40 0 0 40 40 25 0 – 10 – – – – – – – – – 20 – ns ns ns ns ns ns ns ns ns ns ns Notes 16. Test conditions for all parameters other than tri-state parameters are based on signal transition time of 1 V/ns, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in AC Test Loads and Waveforms on page 5. 17. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification. 18. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 19. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the output enters a high impedance state. 20. The internal memory write time is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write. Document #: 38-05447 Rev. *L Page 6 of 16 CY62167EV18 MoBL® Switching Waveforms Figure 4. Read Cycle No. 1 (Address Transition Controlled).[21, 22] tRC RC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Figure 5. Read Cycle No. 2 (OE Controlled)[22, 23] ADDRESS tRC CE1 tPD CE2 tACE BHE/BLE tDBE tLZBE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% 50% ISB ICC HIGH IMPEDANCE DATA VALID tHZBE tHZCE Notes 21. The device is continuously selected. OE, CE1 = VIL, BHE, BLE or both = VIL, and CE2 = VIH. 22. WE is HIGH for read cycle. 23. Address valid before or similar to CE1, BHE, BLE transition LOW and CE2 transition HIGH. Document #: 38-05447 Rev. *L Page 7 of 16 CY62167EV18 MoBL® Switching Waveforms (continued) Figure 6. Write Cycle No. 1 (WE Controlled)[24, 25, 26] tWC ADDRESS tSCE CE1 CE2 tAW tSA WE tPWE tHA BHE/BLE tBW OE tSD DATA I/O NOTE 27 tHZOE VALID DATA tHD Figure 7. Write Cycle No. 2 (CE1 or CE2 Controlled)[24, 25, 26] tWC ADDRESS tSCE CE1 CE2 tSA tAW tPWE tHA WE BHE/BLE tBW OE tSD DATA I/O NOTE 27 tHZOE VALID DATA tHD Notes 24. The internal memory write time is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write 25. Data I/O is high impedance if OE = VIH. 26. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state. 27. During this period the I/Os are in output state. Do not apply input signals. Document #: 38-05447 Rev. *L Page 8 of 16 CY62167EV18 MoBL® Switching Waveforms (continued) Figure 8. Write Cycle No. 3 (WE controlled, OE LOW)[28] tWC ADDRESS tSCE CE1 CE2 BHE/BLE tBW tAW tSA WE tPWE tHA tSD DATA I/O NOTE 29 VALID DATA tHD tHZWE tLZWE Figure 9. Write Cycle No. 4 (BHE/BLE Controlled, OE Low)[28] tWC ADDRESS CE1 CE2 tSCE tAW BHE/BLE tSA WE tPWE tSD DATA I/O NOTE 29 VALID DATA tHD tBW tHA Notes 28. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state. 29. During this period the I/Os are in output state. Do not apply input signals. Document #: 38-05447 Rev. *L Page 9 of 16 CY62167EV18 MoBL® Truth Table CE1 H X[30] X [30] CE2 X[30] L X [30] WE X X X H H H H H H L L L OE X X X L L L H H H X X X BHE BLE X X H L H L L H L L H L X X H L L H H L L L L H Inputs/Outputs High Z High Z High Z Data Out (I/O0–I/O15) Data Out (I/O0–I/O7); High Z (I/O8–I/O15) High Z (I/O0–I/O7); Data Out (I/O8–I/O15) High Z High Z High Z Data In (I/O0–I/O15) Data In (I/O0–I/O7); High Z (I/O8–I/O15) High Z (I/O0–I/O7); Data In (I/O8–I/O15) Mode Deselect/Power-down Deselect/Power-down Deselect/Power-down Read Read Read Output disabled Output disabled Output disabled Write Write Write Power Standby (ISB) Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) L L L L L L L L L H H H H H H H H H Note 30. The ‘X’ (Don’t care) state for the Chip enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted. Document #: 38-05447 Rev. *L Page 10 of 16 CY62167EV18 MoBL® Ordering Information Speed (ns) 55 Ordering Code CY62167EV18LL-55BVI CY62167EV18LL-55BVXI CY62167EV30LL-45BVI [31] Package Diagram 51-85150 51-85150 Package Type 48-ball VFBGA (6 × 8 × 1 mm) 48-ball VFBGA (6 × 8 × 1 mm) (Pb-free) 48-ball VFBGA (6 × 8 × 1 mm) Operating Range Industrial Ordering Code Definition CY 621 6 7 E VXX LL 45/55 XXX X Temperature grade: I = Industrial Package type: BVX: VFBGA (Pb-free) Speed grade Low power V18 = Voltage range (1.8 V typical) V30 = Voltage range (3 V typical) E = Process Technology 90 nm Bus width = x16 Density = 16 Mbit 621 = MoBL SRAM family Company ID: CY = Cypress Note 31. This part can be operated in the VCC range of 1.65 V to 2.25 V at 55 ns speed. It can also be operated in the VCC range of 2.2 V–3.6 V at 45ns speed. Document #: 38-05447 Rev. *L Page 11 of 16 CY62167EV18 MoBL® Package Diagrams Figure 10. 48-Ball VFBGA (6 × 8 × 1 mm), 51-85150 51-85150 *F 51-85150-*E Document #: 38-05447 Rev. *L Page 12 of 16 CY62167EV18 MoBL® Figure 11. 48-Pin TSOP I (12 mm x 18.4 mm x 1.0 mm), 51-85183 51-85153 *C Document #: 38-05447 Rev. *L Page 13 of 16 CY62167EV18 MoBL® Acronyms Acronym BHE BLE CE CMOS I/O OE SRAM TSOP VFBGA WE Description byte high enable byte low enable chip enable complementary metal oxide semiconductor input/output output enable static random access memory thin small outline package very fine ball grid array write enable Document Conventions Units of Measure Symbol °C A mA MHz ns pF V  W Unit of Measure degrees Celsius microamperes milliamperes megahertz nanoseconds picofarads volts ohms watts Document #: 38-05447 Rev. *L Page 14 of 16 CY62167EV18 MoBL® Document History Page Document Title: CY62167EV18 MoBL® 16 Mbit (1M x 16) Static RAM Document Number: 38-05447 Rev. ** *A ECN No. 202600 463674 Orig. of Change AJU NXR Submission date 01/23/2004 See ECN Description of Change New Data Sheet Converted from Advance Information to Preliminary Changed VCC(max) from 2.20 V to 2.25 V Removed ‘L’ bin and 35 ns speed bin from product offering Changed ball E3 from DNU to NC Removed redundant foot note on DNU Changed the ISB2(typ) value from 1.3 Ato1.5 A Changed the ICC(max) value from 40 mA to 25 mA Changed the AC Test Load Capacitance value from 50 pF to 30 pF Corrected typo in Data Retention Characteristics (tR) from 100 µs to tRC ns Changed the ICCDR Value from 8 Ato5 A Changed tOHA, tLZCE, tLZBE, and tLZWE from 6 ns to 10 ns Changed tLZOE from 3 ns to 5 ns Changed tHZOE, tHZCE, tHZBE, and tHZWE from 15 ns to 18 ns Changed tSCE, tAW, and tBW from 40 ns to 35 ns Changed tPE from 30 ns to 35 ns Changed tSD from 20 ns to 25 ns Updated 48 ball FBGA Package Information Updated the Ordering Information table Minor Change: Moved to external web Replaced 45 ns speed bin with 55 ns speed bin Converted from preliminary to final Added footnote# 8 related ISB2 and ICCDR Changed ISB1 and ISB2 spec from 10 A to 12 A Changed ICCDR spec from 8 A to 10 A Added footnote# 13 related AC timing parameters Changed tWC spec from 45 ns to 55 ns Changed tSCE, tAW, tPWE, tBW spec from 35 ns to 40 ns Changed tHZWE spec from 18 ns to 20 ns Added 48-Ball VFBGA (6 x 7 x 1mm) package Added footnote# 1 related to FBGA package Updated Ordering Information table Added CY62167EV30LL-45BVI part in the Ordering Information table Added footnote# 5 related to CY62167EV30LL-45BVI part Added CY62167EV18LL-55BVI part in the Ordering Information table Removed inactive part from the ordering information table.Updated package diagrams. Added footnote #24 related to chip enable Updated template Included BHE and BLE in ISB1, ISB2, and ICCDR test conditions to reflect Byte power down feature. Removed 48-Ball VFBGA (6 x 7 x 1 mm) package related information. Added Acronyms and Ordering code definition. Format updates to match template. Updated Figure 1 and Package Diagram. Updated Package Diagrams. Added Document Conventions. Removed reference to AN1064 SRAM system guidelines. Added ISB1 to footnotes 9 and 13. Modified Ordering Code Definition. Updated Table of Contents. Page 15 of 16 *B *C *D 469182 619122 1130323 NSI NXR VKN See ECN See ECN See ECN *E 1388287 VKN See ECN *F *G *H *I *J 1664843 2675375 2904565 2934396 3006301 VKN/AESA VKN/PYRS AJU VKN RAME See ECN 03/17/2009 04/05/2010 06/03/10 08/12/2010 *K *L 3113908 3295175 PRAS RAME 12/17/2010 06/29/2011 Document #: 38-05447 Rev. *L CY62167EV18 MoBL® Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-05447 Rev. *L Revised June 29, 2011 Page 16 of 16 MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders.