CY62167E_11

CY62167E MoBL® 16-Mbit (1 M × 16 / 2 M × 8) Static RAM 16-Mbit (1 M × 16 / 2 M × 8) Static RAM Features ■ ■ ■ ■ Configurable as 1 M × 16 or as 2 M × 8 SRAM Very high speed: 45 ns Wide voltage range: 4.5 V to 5.5 V Ultra low standby power ❐ Typical standby current: 1.5 µA ❐ Maximum standby current: 12 µA Ultra low active power ❐ Typical active current: 2.2 mA at f = 1 MHz Easy memory expansion with CE1, CE2, and OE features Automatic power-down when deselected CMOS for optimum speed and power Offered in 48-pin TSOP I package reduces power consumption when addresses are not toggling. Place the device into standby mode when deselected (CE1 HIGH, or CE2 LOW, or both BHE and BLE are HIGH). The input and output pins (I/O0 through I/O15) are placed in a high impedance state when: ■ ■ ■ ■ The device is deselected (CE1 HIGH or CE2 LOW) Outputs are disabled (OE HIGH) Both byte high enable and byte low enable are disabled (BHE, BLE HIGH) or A write operation is in progress (CE1 LOW, CE2 HIGH, and WE LOW) ■ ■ ■ ■ ■ Functional Description The CY62167E is a high performance CMOS static RAM organized as 1 M words by 16-bits/2 M words by 8-bits. This device features advanced circuit design to provide an ultra low active current. This is ideal for providing More Battery Life (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that To write to the device, take chip enables (CE1 LOW and CE2 HIGH) and write enable (WE) input LOW. If byte low enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A19). If byte high enable (BHE) is LOW, then data from the I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19). To read from the device, take chip enables (CE1 LOW and CE2 HIGH) and output enable (OE) LOW while forcing the write enable (WE) HIGH. If byte low enable (BLE) is LOW, then data from the memory location specified by the address pins appears on I/O0 to I/O7. If byte high enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. See Truth Table on page 12 for a complete description of read and write modes. Logic Block Diagram A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 DATA IN DRIVERS ROW DECODER 1 M × 16 / 2 M × 8 RAM ARRAY SENSE AMPS I/O0–I/O7 I/O8–I/O15 COLUMN DECODER CE2 POWER DOWN CIRCUIT A11 A12 A13 A14 A15 A16 A17 A18 A19 CE1 BHE BLE BYTE BHE WE OE BLE CE2 CE1 Cypress Semiconductor Corporation Document Number: 001-15607 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 10, 2011 [+] Feedback CY62167E MoBL® Contents Pin Configuration ............................................................. 3 Product Portfolio .............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 Switching Characteristics ................................................ 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 12 Ordering Information ...................................................... 13 Ordering Code Definitions ......................................... 13 Package Diagram ............................................................ 14 Acronyms ........................................................................ 15 Document Conventions ................................................. 15 Units of Measure ....................................................... 15 Document History Page ................................................. 16 Sales, Solutions, and Legal Information ...................... 17 Worldwide Sales and Design Support ....................... 17 Products .................................................................... 17 PSoC Solutions ......................................................... 17 Document Number: 001-15607 Rev. *C Page 2 of 17 [+] Feedback CY62167E MoBL® Pin Configuration 48-pin TSOP I Top View [1, 2] A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE CE2 NC BHE BLE A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE Vss I/O15/A20 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 Vcc I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 OE Vss CE1 A0 Product Portfolio Power Dissipation Product Min CY62167ELL 4.5 VCC Range (V) Typ[3] 5.0 Max 5.5 45 Speed (ns) Operating ICC (mA) f = 1 MHz Typ[3] 2.2 Max 4.0 25 f = fmax Typ[3] Max 30 Standby ISB2 (µA) Typ[3] 1.5 Max 12 Notes 1. NC pins are not connected on the die. 2. The BYTE pin in the 48-pin TSOPI package must be tied to VCC to use the device as a 1 M × 16 SRAM. The 48-TSOPI package can also be used as a 2 M × 8 SRAM by tying the BYTE signal to VSS. In the 2 M × 8 configuration, pin 45 is A20, while BHE, BLE and I/O8 to I/O14 pins are not used. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. Document Number: 001-15607 Rev. *C Page 3 of 17 [+] Feedback CY62167E MoBL® Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature ................................ –65 °C to +150 °C Ambient temperature with power applied .......................................... –55 °C to +125 °C Supply voltage to ground potential .........................................................–0.5 V to 6.0 V DC voltage applied to outputs in high Z state[4, 5] ..........................................–0.5 V to 6.0 V DC input voltage[4, 5] ......................................–0.5 V to 6.0 V Output current into outputs (LOW) ............................. 20 mA Static discharge voltage .......................................... >2001 V (MIL-STD-883, method 3015) Latch-up current ..................................................... >200 mA Operating Range Device CY62167ELL Range Industrial Ambient Temperature VCC[6] –40 °C to +85 °C 4.5 V to 5.5 V Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage Input leakage current Output leakage current VCC operating supply current Test Conditions IOH = –1.0 mA IOL = 2.1 mA VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V GND < VI < VCC GND < VO < VCC, output disabled f = fMAX = 1/tRC f = 1 MHz ISB2[9] Automatic power down current—CMOS inputs VCC = VCC(max) IOUT = 0 mA CMOS levels 45 ns Min 2.4 – 2.2 –0.5 –1 –1 – – – Typ[8] – – – – – – 25 2.2 1.5 Max – 0.4 VCC + 0.5 V 0.7[7] +1 +1 30 4.0 12 Unit V V V V µA µA mA mA µA CE1 > VCC – 0.2 V or CE2 < 0.2 V, or BHE and BLE > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0, VCC = VCC(max) Notes 4. VIL(min) = –2.0 V for pulse durations less than 20 ns. 5. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns. 6. Full Device AC operation is based on a 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization. 7. Under DC conditions the device meets a VIL of 0.8 V. However, in dynamic conditions input LOW voltage applied to the device must not be higher than 0.7 V. 8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C 9. Chip enables (CE1 and CE2), byte enables (BHE and BLE) and BYTE need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating. Document Number: 001-15607 Rev. *C Page 4 of 17 [+] Feedback CY62167E MoBL® Capacitance Parameter[10] CIN COUT Description Input capacitance Output capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = VCC(typ) Max 10 10 Unit pF pF Thermal Resistance Parameter[10] JA JC Description Thermal resistance (junction to ambient) Thermal resistance (junction to case) Test Conditions Still air, soldered on a 3 × 4.5 inch, two-layer printed circuit board 48-pin TSOP I Unit 60 4.3 C/W C/W AC Test Loads and Waveforms Figure 1. AC Test Loads and Waveforms VCC OUTPUT R1 VCC GND 10% R2 ALL INPUT PULSES 90% 90% 10% FALL TIME= 1 V/ns 30 pF INCLUDING JIG AND SCOPE RISE TIME= 1 V/ns EQUIVALENT TO: THÉVENIN EQUIVALENT RTH OUTPUT V Parameters R1 R2 RTH VTH Values 1800 990 639 1.77 Unit    V Note 10. Tested initially and after any design or process changes that may affect these parameters. Document Number: 001-15607 Rev. *C Page 5 of 17 [+] Feedback CY62167E MoBL® Data Retention Characteristics Over the operating range Parameter VDR ICCDR[12] Description VCC for data retention Data retention current – VCC = VDR, CE1 > VCC – 0.2 V or CE2 < 0.2 V, or BHE and BLE > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V – – Conditions Min 2.0 – Typ[11] – – Max – 12 Unit V µA tCDR[13] tR[14] Chip deselect to data retention time Operation recovery time 0 45 – – – – ns ns Data Retention Waveform Figure 2. Data Retention Waveform[15] DATA RETENTION MODE VDR > 2.0 V VCC CE1 or BHE. BLE or CE2 VCC(min) tCDR VCC(min) tR Notes 11. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 12. Chip enables (CE1 and CE2), byte enables (BHE and BLE) and BYTE need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating. 13. Tested initially and after any design or process changes that may affect these parameters. 14. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs. 15. BHE. BLE is the AND of BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling BHE and BLE. Document Number: 001-15607 Rev. *C Page 6 of 17 [+] Feedback CY62167E MoBL® Switching Characteristics Over the Operating Range Parameter [16, 17] Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle[21] tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE Write cycle time CE1 LOW and CE2 HIGH to write end Address setup to write end Address hold from write end Address setup to write start WE pulse width BLE/BHE LOW to write end Data setup to write end Data hold from write end WE LOW to high WE HIGH to low Z[18, 19] Z[18] 45 35 35 0 0 35 35 25 0 – 10 – – – – – – – – – 18 – ns ns ns ns ns ns ns ns ns ns ns Read cycle time Address to data valid Data hold from address change CE1 LOW and CE2 HIGH to data valid OE LOW to data valid OE LOW to low Z[18] Z[18] Z[18, 19] OE HIGH to high Z[18, 19] CE1 LOW and CE2 HIGH to low 45 – 10 – – 5 – 10 – 0 – – 5 – – 45 – 45 22 – 18 – 18 – 45 45 – 18 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description 45 ns Min Max Unit CE1 HIGH and CE2 LOW to high CE1 LOW and CE2 HIGH to power-up CE1 HIGH and CE2 LOW to power-down BLE/BHE LOW to data valid BLE/BHE LOW to low Z[18, 20] Z[18, 19] BLE/BHE HIGH to high Notes 16. Test conditions for all parameters other than tristate parameters assume signal transition time of 1 V/ns, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in Figure 1 on page 5. 17. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification. 18. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 19. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 20. If both byte enables are toggled together, this value is 10 ns. 21. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. Document Number: 001-15607 Rev. *C Page 7 of 17 [+] Feedback CY62167E MoBL® Switching Waveforms Figure 3. Read Cycle No. 1 (Address Transition Controlled) [22, 23] tRC RC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Figure 4. Read Cycle No. 2 (OE Controlled) [23, 24] ADDRESS tRC CE1 CE2 tACE BHE/BLE tDBE tLZBE OE tDOE DATA OUT tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% 50% ICC ISB DATA VALID tHZOE HIGH IMPEDANCE tHZBE tPD tHZCE Notes 22. The device is continuously selected. OE, CE1 = VIL, BHE, BLE or both = VIL, and CE2 = VIH. 23. WE is HIGH for read cycle. 24. Address valid before or similar to CE1, BHE, BLE transition LOW and CE2 transition HIGH. Document Number: 001-15607 Rev. *C Page 8 of 17 [+] Feedback CY62167E MoBL® Switching Waveforms (continued) Figure 5. Write Cycle No. 1 (WE Controlled) [25, 26, 27] tWC ADDRESS tSCE CE1 CE2 tAW WE tSA tPWE tHA BHE/BLE tBW OE tSD DATA I/O NOTE 28 tHZOE VALID DATA tHD Notes 25. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. 26. Data I/O is high impedance if OE = VIH. 27. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state. 28. During this period the I/Os are in output state and input signals must not be applied. Document Number: 001-15607 Rev. *C Page 9 of 17 [+] Feedback CY62167E MoBL® Switching Waveforms (continued) Figure 6. Write Cycle No. 2 (CE1 or CE2 Controlled).[29, 30, 31] tWC ADDRESS tSCE CE1 CE2 tSA tAW tPWE tHA WE BHE/BLE tBW OE DATA I/O NOTE 32 tHZOE tSD VALID DATA tHD Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW) [31] tWC ADDRESS tSCE CE1 CE2 BHE/BLE tAW tSA WE tBW tHA tPWE tSD DATA I/O NOTE 32 VALID DATA tHD tHZWE tLZWE Notes 29. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. 30. Data I/O is high impedance if OE = VIH. 31. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state. 32. During this period the I/Os are in output state and input signals must not be applied. Document Number: 001-15607 Rev. *C Page 10 of 17 [+] Feedback CY62167E MoBL® Switching Waveforms (continued) Figure 8. Write Cycle No. 4 (BHE/BLE controlled, OE LOW) [33] tWC ADDRESS CE1 CE2 tSCE tAW BHE/BLE tSA WE tPWE tSD DATA I/O NOTE 34 VALID DATA tHD tBW tHA Notes 33. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state. 34. During this period the I/Os are in output state and input signals must not be applied. Document Number: 001-15607 Rev. *C Page 11 of 17 [+] Feedback CY62167E MoBL® Truth Table CE1 H X[35] X[35] L L L L L L L L L CE2 X [35] WE X X X H H H H H H L L L OE X X X L L L H H H X X X BHE X X H L H L L H L L H L BLE X X H L L H H L L L L H Inputs Outputs High Z High Z High Z Data out (I/O0–I/O15) Data out (I/O0–I/O7); High Z (I/O8–I/O15) High Z (I/O0–I/O7); Data out (I/O8–I/O15) High Z High Z High Z Data in (I/O0–I/O15) Data in (I/O0–I/O7); High Z (I/O8–I/O15) High Z (I/O0–I/O7); Data in (I/O8–I/O15) Mode Deselect/power-down Deselect/power-down Deselect/power-down Read Read Read Output disabled Output disabled Output disabled Write Write Write Power Standby (ISB) Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) L X[35] H H H H H H H H H Note 35. The ‘X’ (Do not care) state for the chip enables in the truth table refers to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted. Document Number: 001-15607 Rev. *C Page 12 of 17 [+] Feedback CY62167E MoBL® Ordering Information The below table lists the CY62167ELL key package features and ordering codes. The table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products. Speed (ns) 45 Ordering Code CY62167ELL-45ZXI Package Diagram Package Type Operating Range Industrial 51-85183 48-pin TSOP I (Pb-free) Ordering Code Definitions CY 621 6 7 E LL - 45 Z X I Temperature Grade: I = Industrial Pb-free Package Type: Z = 48-pin TSOP I Speed Grade: 45 ns LL = Low Power Process Technology: 90 nm Bus width = × 16 Density = 16-Mbit Family Code: MoBL SRAM family Company ID: CY = Cypress Document Number: 001-15607 Rev. *C Page 13 of 17 [+] Feedback CY62167E MoBL® Package Diagram Figure 9. 48-pin TSOP I (12 × 18.4 × 1.0 mm) Z48A, 51-85183 51-85183 *B Document Number: 001-15607 Rev. *C Page 14 of 17 [+] Feedback CY62167E MoBL® Acronyms Acronym BHE BLE CMOS CE I/O OE SRAM TSOP WE byte high enable byte low enable complementary metal oxide semiconductor chip enable input/output output enable static random access memory thin small outline package write enable Description Document Conventions Units of Measure Symbol °C MHz µA mA mm ns  % pF V W degree Celsius Mega Hertz micro Amperes milli Amperes milli meter nano seconds ohms percent pico Farad Volts Watts Unit of Measure Document Number: 001-15607 Rev. *C Page 15 of 17 [+] Feedback CY62167E MoBL® Document History Page Document Title: CY62167E MoBL®, 16-Mbit (1 M × 16 / 2 M × 8) Static RAM Document Number: 001-15607 Rev. ** *A ECN No. 1103145 1138903 Issue Date See ECN See ECN Orig. of Change VKN VKN Description of Change New Data Sheet Converted from preliminary to final Changed ICC(max) spec from 2.8 mA to 4.0 mA for f=1 MHz Changed ICC(typ) spec from 22 mA to 25 mA for f=fmax Changed ICC(max) spec from 25 mA to 30 mA for f=fmax Added footnote# 8 related to VIL Changed ICCDR spec from 10 A to 12 A Added footnote# 14 related to AC timing parameters Included BHE, BLE in ISB2, ICCDR test conditions to reflect byte power down feature Added footnote #35 related to chip enable Updated package diagram Updated template Removed the Note “For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.” in page 1 and its reference in Functional Description. Updated Switching Characteristics (changed the Min value of tLZBE parameter). Updated in new template. *B 2934385 06/03/10 VKN *C 3279426 06/10/2011 RAME Document Number: 001-15607 Rev. *C Page 16 of 17 [+] Feedback CY62167E MoBL® Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2007-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-15607 Rev. *C Revised June 10, 2011 Page 17 of 17 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback