CY62168EV30 MoBL®
16-Mbit (2 M × 8) Static RAM
16-Mbit (2 M × 8) Static RAM
Features
■ ■ ■
Very high speed: 45 ns Wide voltage range: 2.20 V to 3.60 V Ultra low standby power ❐ Typical standby current: 1.5 µA ❐ Maximum standby current: 12 µA Ultra low active power ❐ Typical active current: 2.2 mA at f = 1 MHz Easy memory expansion with CE1, CE2 and OE features Automatic power-down when deselected CMOS for optimum speed/power Offered in Pb-free 48-ball FBGA package. For Pb-free 48-pin TSOP I package, refer to CY62167EV30 datasheet.
■
automatic power-down feature that significantly reduces power consumption by 90% when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99% when deselected (Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW). The input and output pins (I/O0 through I/O7) are placed in a high impedance state when: the device is deselected (Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW), outputs are disabled (OE HIGH), or a write operation is in progress (Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and WE LOW). Write to the device by taking Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and the Write Enable (WE) input LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A20). Read from the device by taking Chip Enable 1 (CE1) and Output Enable (OE) LOW and Chip Enable 2 (CE2) HIGH while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or a write operation is in progress (CE1 LOW and CE2 HIGH and WE LOW). See the Truth Table on page 11 for a complete description of read and write modes.
■ ■ ■ ■
Functional Description
The CY62168EV30 is a high performance CMOS static RAM organized as 2 M words by 8-bits. This device features advanced circuit design to provide an ultra low active current. This is ideal for providing More Battery Life (MoBL) in portable applications such as cellular telephones. The device also has an
Logic Block Diagram
CE1 CE2
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 WE OE
DATA IN DRIVERS ROW DECODER
I/O 0 I/O 1 SENSE AMPS I/O 2 I/O 3 I/O 4 I/O 5 I/O 6
2M x 8 ARRAY
COLUMN DECODER
POWER DOWN
I/O 7
A13 A14 A15 A16 A17
A19 A20
A18
Cypress Semiconductor Corporation Document #: 001-07721 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
• 408-943-2600 Revised June 10, 2011
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CY62168EV30 MoBL®
Contents
Pin Configuration ............................................................. 3 Product Portfolio .............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 DC Electrical Characteristics .......................................... 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 Switching Characteristics ................................................ 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 11 Ordering Information ...................................................... 12 Ordering Code Definitions ......................................... 12 Package Diagram ............................................................ 13 Acronyms ........................................................................ 14 Document Conventions ................................................. 14 Units of Measure ....................................................... 14 Document History Page ................................................. 15 Sales, Solutions, and Legal Information ...................... 16 Worldwide Sales and Design Support ....................... 16 Products .................................................................... 16 PSoC Solutions ......................................................... 16
Document #: 001-07721 Rev. *D
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CY62168EV30 MoBL®
Pin Configuration
Figure 1. 48-ball FBGA Top View [1]
1 NC NC I/O0 VSS VCC I/O3 NC A18 4 A1 A4 A6 A7 A16 A15 A13 A10
2 OE NC NC I/O1 I/O2 NC A20 A8
3 A0 A3 A5 A17 NC A14 A12 A9
5 A2 CE1 NC I/O5 I/O6 NC WE A11
6 CE2 NC I/O4 VCC VSS I/O7 NC A19 A B C D E F G H
Product Portfolio
Power Dissipation Product Min CY62168EV30LL 2.2 VCC Range (V) Typ[2] 3.0 Max 3.6 45 Speed (ns) Operating ICC (mA) f = 1 MHz Typ[2] 2.2 Max 4.0 f = fmax Typ[2] 25 Max 30 Standby ISB2 (A) Typ[2] 1.5 Max 12
Notes 1. NC pins are not connected on the die. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
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Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature ................................ –65 °C to +150 °C Ambient temperature with power applied .......................................... –55 °C to +125 °C Supply voltage to ground potential ....................................... –0.3 V to VCC(max) + 0.3 V DC voltage applied to outputs in high Z state[3, 4] ........................–0.3 V to VCC(max) + 0.3 V DC input voltage[3, 4] .................. –0.3 V to VCC(max) + 0.3 V Output current into outputs (LOW) ............................. 20 mA Static discharge voltage .......................................... > 2001 V (MIL-STD-883, method 3015) Latch-up current .................................................... > 200 mA
Operating Range
Range Industrial Ambient Temperature (TA)[5] –40 °C to +85 °C VCC[6] 2.2 V to 3.6 V
DC Electrical Characteristics
Over the operating range Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1[8] Description Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage Input leakage current Output leakage current VCC operating supply current Test Conditions 2.2 < VCC < 2.7 2.7 < VCC < 3.6 2.2 < VCC < 2.7 2.7 < VCC < 3.6 2.2 < VCC < 2.7 2.7 < VCC < 3.6 2.2 < VCC < 2.7 2.7 < VCC < 3.6 GND < VI < VCC GND < VO < VCC, Output disabled f = fMAX = 1/tRC f = 1 MHz Automatic CE power-down current – CMOS inputs VCC = 3.6 V, IOUT = 0 mA, CMOS level IOH = 0.1 mA IOH = 1.0 mA IOL = 0.1 mA IOH = 2.1 mA CY62168EV30-45 Min 2.0 2.4 – – 1.8 2.2 –0.3 –0.3 –1 –1 – – – Typ[7] – – – – – – – – – – 25 2.2 1.5 Max – – 0.4 0.4 VCC + 0.3 VCC + 0.3 0.6 0.8 +1 +1 30 4.0 12 µA V V V µA µA mA Unit V
CE1 > VCC 0.2 V or CE2 < 0.2 V, VIN > VCC 0.2 V, VIN < 0.2 V, f = fMAX (address and data only), f = 0 (OE, WE) CE1 > VCC 0.2 V or CE2 < 0.2 V, VIN > VCC 0.2 V or VIN < 0.2 V, f = 0, VCC = 3.6 V
ISB2[8]
Automatic CE power-down current – CMOS inputs
–
1.5
12
µA
Notes 3. VIL(min) = –0.2 V for pulse durations less than 20 ns. 4. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns. 5. TA is the “Instant-On” case temperature. 6. Full device AC operation assumes a 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization. 7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 8. Chip enables (CE1 and CE2) must be at CMOS level to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
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Capacitance
Parameter[9] CIN COUT Description Input capacitance Output capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = VCC(typ) Max 8 10 Unit pF pF
Thermal Resistance
Parameter[9] JA JC Description Thermal resistance (junction to ambient) Thermal resistance (junction to case) Test Conditions Still air, soldered on a 3 × 4.5 inch, two-layer printed circuit board 48-ball FBGA 55 16 Unit C/W C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
R1 VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 ALL INPUT PULSES VCC GND 10% 90% 90% 10%
Fall time: 1 V/ns
Rise Time: 1 V/ns
Equivalent to:
THÉVENIN EQUIVALENT RTH VTH
OUTPUT
Parameters R1 R2 RTH VTH
2.5 V (2.2 V to 2.7 V) 16600 15400 8000 1.2
3.0 V (2.7 V to 3.6 V) 1103 1554 645 1.75
Unit V
Note 9. Tested initially and after any design or process changes that may affect these parameters.
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Data Retention Characteristics
Over the Operating Range Parameter VDR ICCDR[11] Description VCC for data retention Data retention current VCC = 1.5 V CE1 > VCC 0.2 V or CE2 < 0.2 V VIN > VCC 0.2 V or VIN < 0.2 V Conditions Min 1.5 – Typ[10] – – Max 3.6 10 Unit V µA
tCDR[12] tR[13]
Chip deselect to data retention time Operation recovery time
0 45
– –
– –
ns ns
Data Retention Waveform
Figure 3. Data Retention Waveform
DATA RETENTION MODE VCC CE1 VCC(min) tCDR VDR > 1.5 V VCC(min) tR
or
CE2
Notes 10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 11. Chip enables (CE1 and CE2) must be at CMOS level to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating. 12. Tested initially and after any design or process changes that may affect these parameters. 13. Full Device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) 100 µs.
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Switching Characteristics
Over the Operating Range Parameter [14] Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE
[17]
Description
45 ns Min 45 – 10 – – 5 – Max – 45 – 45 22 – 18 – 18 – 45 – – – – – – – – 18 –
Unit
Read cycle time Address to data valid Data hold from address change CE1 LOW and CE2 HIGH to data valid OE LOW to data valid OE LOW to low Z[15] Z[15, 16] Z[15] OE HIGH to high
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CE1 LOW and CE2 HIGH to low
10 – 0 – 45 35 35 0 0 35 25 0 – 10
CE1 HIGH or CE2 LOW to high Z[15, 16] CE1 LOW and CE2 HIGH to power-up CE1 HIGH or CE2 LOW to power-down Write cycle time CE1 LOW and CE2 HIGH to write end Address setup to write end Address hold from write end Address setup to write start WE pulse width Data setup to write end Data hold from write end WE LOW to high Z[15, 16] WE HIGH to low Z[15]
Notes 14. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in Figure 2 on page 5. 15. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 16. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state. 17. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
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Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled) [18, 19]
tRC RC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Figure 5. Read Cycle No. 2 (OE Controlled) [19, 20]
ADDRESS tRC CE1 CE2 tACE OE tDOE DATA VALID tHZOE HIGH IMPEDANCE tPD tHZCE
DATA OUT
tLZOE HIGH IMPEDANCE tLZCE
VCC SUPPLY CURRENT
tPU
50%
50%
ICC ISB
Notes 18. The device is continuously selected. OE, CE1 = VIL, and CE2 = VIH. 19. WE is HIGH for read cycle. 20. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH.
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Switching Waveforms (continued)
Figure 6. Write Cycle No. 1 (WE Controlled) [21, 22, 23]
tWC ADDRESS tSCE CE1 CE2 tAW WE tSA tPWE tHA
OE tSD DATA I/O NOTE 24 tHZOE VALID DATA
tHD
Figure 7. Write Cycle No. 2 (CE1 or CE2 Controlled) [21, 22, 23]
tWC ADDRESS tSCE CE1 CE2 tSA tAW tPWE tHA
WE
OE DATA I/O NOTE 24 tHZOE
tSD VALID DATA
tHD
Notes 21. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. 22. Data I/O is high impedance if OE = VIH. 23. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state. 24. During this period the I/Os are in output state. Do not apply input signals.
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Switching Waveforms (continued)
Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [25]
tWC ADDRESS tSCE CE1 CE2 tAW tSA WE tPWE tHA
tSD DATA I/O NOTE 26 VALID DATA
tHD
tHZWE
tLZWE
Notes 25. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state. 26. During this period the I/Os are in output state. Do not apply input signals.
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Truth Table
CE1 H X
[27]
CE2 X
[27]
WE X X H H L
OE X X L H X High Z High Z
I/O
Mode Deselect/power-down Deselect/power-down Read Output disabled Write
Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
L H H H
L L L
Data out (I/O0–I/O7) High Z Data in (I/O0–I/O7)
Note 27. The ‘X’ (Do not care) state for the chip enables in the truth table refers to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
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Ordering Information
The below table lists the CY62168EV30 MoBL key package features and ordering codes. The table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products. Speed (ns) 45 Ordering Code CY62168EV30LL-45BVXI Package Diagram Package Type Operating Range Industrial
51-85150 48-ball VFBGA (Pb-free)
Ordering Code Definitions
CY 621 6 8 E V30 LL - 45 BV X I Temperature Grade: I = Industrial Pb-free Package Type: BV = 48-ball VFBGA Speed Grade: 45 ns LL = Low Power Voltage Range = 3 V typical Process Technology: 90 nm Bus width = × 8 Density = 16-Mbit Family Code: MoBL SRAM family Company ID: CY = Cypress
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Package Diagram
Figure 9. 48-ball VFBGA (6 × 8 × 1 mm) BV48/BZ48, 51-85150
51-85150 *F
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Acronyms
Acronym CE CMOS FBGA I/O OE SRAM TSOP VFBGA WE chip enable complementary metal oxide semiconductor fine-pitch ball grid array input/output output enable static random access memory thin small outline package very fine-pitch ball grid array write enable Description
Document Conventions
Units of Measure
Symbol °C MHz µA s mA mm ns % pF V W degree Celsius Mega Hertz micro Amperes micro seconds milli Amperes milli meter nano seconds ohms percent pico Farad Volts Watts Unit of Measure
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Document History Page
Document Title: CY62168EV30 MoBL®, 16-Mbit (2 M × 8) Static RAM Document Number: 001-07721 Rev. ** *A ECN No. 457686 464509 Orig. of Change NXR NXR Issue Date See ECN See ECN New Data Sheet Removed TSOP I package; Added reference to CY62167EV30 TSOP I package which can be used as a 2 M × 8 SRAM Changed the ISB2(Typ) value from 1.3 µA to 1.5 µA Changed the ICC(Typ) value from 2 mA to 2.2 mA for f=1 MHz Test condition Changed the ICC(Typ) value from 15 mA to 22 mA and ICC(Max) value from 40 mA to 25 mA for f = 1 MHz Test condition Changed the ICCDR(Max) value from 8.5 µA to 8 µA Converted from preliminary to final Changed ICC(max) spec from 2.8 mA to 4.0 mA for f=1 MHz Changed ICC(typ) spec from 22 mA to 25 mA for f=fmax Changed ICC(max) spec from 25 mA to 30 mA for f=fmax Added footnote# 8 related to ISB2 and ICCDR Changed ISB1 and ISB2 spec from 8.5 µA to 12 µA Changed ICCDR spec from 8 µA to 10 µA Corrected typo in Functional Description section Corrected VCC stabilization time to 200 µsec Updated template. Added footnote #28 related to chip enable Updated package diagram Removed the Note “For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.” in page 1 and its reference in Functional Description. Updated Package Diagram. Updated in new template. Description of Change
*B
1138883
VKN
See ECN
*C
2934385
VKN
06/03/10
*D
3279426
RAME
06/10/2011
Document #: 001-07721 Rev. *D
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Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2006-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-07721 Rev. *D
Revised June 10, 2011
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