CY62177DV20LL-70BAI

CY62177DV20 MoBL2™ 32-Mbit (2M x 16) Static RAM Features ■ ■ ■ Very high speed: 70 ns Wide voltage range: 1.7V – 2.2V Ultra low active power ❐ Typical active current: 2 mA at f = 1 MHz ❐ Typical active current: 12 mA at f = fMAX Ultra low standby power Easy memory expansion with CE1, CE2, and OE features Automatic power down when deselected CMOS for optimum speed and power Offered in 48-ball VFBGA package by 99% when addresses are not toggling. The device can also be put into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input and output pins (IO0 through IO15) are placed in a high impedance state when: the device is deselected (CE1HIGH or CE2 LOW); outputs are disabled (OE HIGH); both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH); when a write operation is in progress (CE1 LOW, CE2 HIGH and WE LOW). To write to the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7) is written into the location specified on the address pins (A0 through A20). If Byte High Enable (BHE) is LOW, then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A20). To read from the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from memory appears on IO8 to IO15. See the Truth Table on page 9 for a complete description of read and write modes. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines. ■ ■ ■ ■ ■ Functional Description The CY62177DV20 is a high performance CMOS static RAM organized as 2M words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that reduces power consumption Logic Block Diagram DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER 2M × 16 RAM ARRAY SENSE AMPS IO0–IO7 IO8–IO15 COLUMN DECODER BHE CE2 Power Down Circuit CE1 BHE BLE A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 WE OE BLE CE2 CE1 Cypress Semiconductor Corporation Document #: 001-44018 Rev. ** • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 08, 2008 [+] Feedback CY62177DV20 MoBL2™ Pin Configuration Figure 1. 48-Ball VFBGA (8 x 9.5 x 1.2 mm) Top View [1] 1 BLE IO 8 IO 9 VSS VCC IO 14 IO 15 A18 2 OE BHE IO 10 IO11 3 A0 A3 A5 A17 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE1 IO 1 IO3 IO 4 IO 5 WE A11 6 CE2 IO 0 IO 2 Vcc Vss IO 6 IO 7 A20 A B C D E F G H IO 12 DNU IO 13 A19 A8 A14 A12 A9 Product Portfolio Power Dissipation Product VCC Range (V) Typ[2] 1.8 Speed (ns) Max 2.2 70 Typ[2] 2 Operating ICC (mA) f = 1 MHz Min CY62177DV20LL 1.7 Max 4 f = fmax Typ[2] 12 Max 25 Standby ISB2 (μA) Typ[2] 5 Max 50 Notes 1. DNU pins must be connected to VSS or left open. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C. Document #: 001-44018 Rev. ** Page 2 of 11 [+] Feedback CY62177DV20 MoBL2™ DC Input Voltage[3, 4] ....................... –0.2V toVCC(max) + 0.2V Output Current into Outputs (LOW) ............................ 20 mA Static Discharge Voltage........................................... >2001V (MIL-STD-883, Method 3015) Latch up Current...................................................... >200 mA Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................ –65°C to + 150°C Ambient Temperature with Power Applied ........................................... –55°C to + 125°C Supply Voltage to Ground Potential ......................................... –0.2V to VCC(max) + 0.2V DC Voltage Applied to Outputs in High Z State[3, 4].......................... –0.2V to VCC(max) + 0.2V Operating Range Device CY62177DV20LL Range Ambient Temperature VCC[5] 1.7V to 2.2V Industrial –40°C to +85°C Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current IOH = –0.1 mA IOL = 0.1 mA VCC = 1.7V to 2.2V VCC = 1.7V to 2.2V GND < VI < VCC GND < VO < VCC, Output Disabled f = fmax = 1/tRC f = 1 MHz VCC = VCC(max) IOUT = 0 mA CMOS levels 1.4 –0.2 –1 –1 12 2 5 Test Conditions 70 ns Min 1.4 0.2 VCC + 0.2V 0.4 +1 +1 25 4 100 Typ[2] Max Unit V V V V μA μA mA mA μA ISB1 Automatic CE Power Down CE1 > VCC – 0.2V or CE2 < 0.2V Current – CMOS Inputs VIN > VCC – 0.2V, VIN < 0.2V) f = fmax(Address and Data Only), f = 0 (OE, WE, BHE and BLE), VCC = VCC(max) Automatic CE Power Down CE1 > VCC – 0.2V or CE2 < 0.2V, Current – CMOS Inputs VIN > VCC – 0.2V or VIN < 0.2V, f = 0, VCC = VCC(max) ISB2 5 50 μA Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = VCC(typ) Max 12 12 Unit pF pF Notes 3. VIL(min) = –2.0V for pulse durations less than 20 ns. 4. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns. 5. Full Device AC operation is based on a 100 μs ramp time from 0 to VCC(min) and 100 μs wait time after VCC stabilization. Document #: 001-44018 Rev. ** Page 3 of 11 [+] Feedback CY62177DV20 MoBL2™ Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still air, soldered on a 3 × 4.5 inch, two-layer printed circuit board VFBGA 55 16 Unit °C/W °C/W AC Test Loads and Waveforms R1 VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 VCC(typ) GND 10% ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Rise Time = 1 V/ns Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT V Parameters R1 R2 RTH VTH 1.8V 13500 10800 6000 0.80 Unit Ω Ω Ω V Data Retention Characteristics Over the Operating Range Parameter VDR ICCDR tCDR[6] tR[7] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC = 1.0V, CE1 > VCC – 0.2V, CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V 0 tRC Conditions Min 1.0 25 Typ[2] Max Unit V μA ns ns Data Retention Waveform VCC CE1 or BHE.BLE [8] VCC(min) tCDR DATA RETENTION MODE VDR > 1.0 V VCC(min) tR or CE2 Notes 6. Tested initially and after any design or process changes that may affect these parameters. 7. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 μs or stable at VCC(min) > 100 μs. 8. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE. Document #: 001-44018 Rev. ** Page 4 of 11 [+] Feedback CY62177DV20 MoBL2™ Switching Characteristics Over the Operating Range [9] Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE [12] Description 70 ns Min Max Unit Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW and CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to OE HIGH to Low-Z[10] High-Z[10, 11] 70 70 10 70 35 5 25 10 25 0 70 70 5 25 High-Z[10, 11] ns ns ns ns ns ns ns ns ns ns ns ns ns ns CE1 LOW and CE2 HIGH to Low-Z[10] CE1 HIGH and CE2 LOW to CE1 LOW and CE2 HIGH to Power Up CE1 HIGH and CE2 LOW to Power Down BLE/BHE LOW to Data Valid BLE/BHE LOW to BLE/BHE HIGH to Low-Z[10] High-Z[10, 11] Write Cycle Time CE1 LOW and CE2 HIGH to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width BLE/BHE LOW to Write End Data Setup to Write End Data Hold from Write End WE LOW to High-Z WE HIGH to [10, 11] 70 60 60 0 0 45 60 30 0 25 10 ns ns ns ns ns ns ns ns ns ns ns Low-Z[10] Notes 9. Test conditions are based on signal transition time of 2 ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL. 10. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the output enters a high impedance state. 12. The internal memory write time is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write. Document #: 001-44018 Rev. ** Page 5 of 11 [+] Feedback CY62177DV20 MoBL2™ Switching Waveforms Figure 2 shows address transition controlled read cycle waveforms.[13, 14] Figure 2. Read Cycle No. 1 tRC RC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Figure 3 shows OE controlled read cycle waveforms.[14, 15] Figure 3. Read Cycle No. 2 ADDRESS tRC CE1 tPD CE2 tACE BHE/BLE tDBE tLZBE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% 50% ISB ICC HIGH IMPEDANCE DATA VALID tHZBE tHZCE Notes 13. The device is continuously selected. OE, CE1 = VIL, BHE, BLE or both = VIL, and CE2 = VIH. 14. WE is HIGH for read cycle. 15. Address valid before or similar to CE1, BHE, BLE transition LOW and CE2 transition HIGH. Document #: 001-44018 Rev. ** Page 6 of 11 [+] Feedback CY62177DV20 MoBL2™ Switching Waveforms (continued) Figure 4 shows WE controlled write cycle waveforms.[12, 16, 17] Figure 4. Write Cycle No. 1 tWC ADDRESS tSCE CE1 CE2 tAW tSA WE tPWE tHA BHE/BLE tBW OE tSD DATA IO NOTE 18 tHZOE VALID DATA tHD Notes 16. Data IO is high impedance if OE = VIH. 17. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state. 18. During this period the IOs are in output state. Do not apply input signals. Document #: 001-44018 Rev. ** Page 7 of 11 [+] Feedback CY62177DV20 MoBL2™ Switching Waveforms (continued) Figure 5 shows CE1 or CE2 controlled write cycle waveforms.[12, 16, 17] Figure 5. Write Cycle No. 2 tWC ADDRESS tSCE CE1 CE2 tSA tAW tPWE tHA WE BHE/BLE tBW OE tSD DATA IO NOTE 18 tHZOE VALID DATA tHD Figure 6 shows WE controlled, OE LOW write cycle waveforms.[17] Figure 6. Write Cycle No. 3 tWC ADDRESS tSCE CE1 CE2 BHE/BLE tBW tAW tSA WE tPWE tHA tSD DATA IO NOTE 18 VALID DATA tHD tHZWE tLZWE Document #: 001-44018 Rev. ** Page 8 of 11 [+] Feedback CY62177DV20 MoBL2™ Switching Waveforms (continued) Figure 7 shows BHE/BLE controlled, OE LOW write cycle waveforms.[17] Figure 7. Write Cycle No. 4 tWC ADDRESS CE1 CE2 tSCE tAW BHE/BLE tSA WE tPWE tSD DATA IO NOTE 18 VALID DATA tHD tBW tHA Truth Table CE1 H X X L L L L L L L L L CE2 X L X H H H H H H H H H WE X X X H H H H H H L L L OE X X X L L L H H H X X X BHE BLE X X H L H L L H L L H L X X H L L H H L L L L H Inputs/Outputs High Z High Z High Z Data Out (IO0–IO15) Data Out (IO0–IO7); High Z (IO8–IO15) High Z (IO0–IO7); Data Out (IO8–IO15) High Z High Z High Z Data In (IO0–IO15) Data In (IO0–IO7); High Z (IO8–IO15) High Z (IO0–IO7); Data In (IO8–IO15) Mode Deselect / Power Down Deselect / Power Down Deselect / Power Down Read Read Read Output Disabled Output Disabled Output Disabled Write Write Write Power Standby (ISB) Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Document #: 001-44018 Rev. ** Page 9 of 11 [+] Feedback CY62177DV20 MoBL2™ Ordering Information Speed (ns) 70 Ordering Code CY62177DV20LL-70BAI Package Diagram 51-85191 Package Type 48-ball VFBGA (8.0 x 9.5 x 1.2 mm) Operating Range Industrial Package Diagram Figure 8. 48-Ball VFBGA (8.0 x 9.5 x 1.2 mm) BOTTOM VIEW TOP VIEW Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 1 2 3 4 5 6 6 5 4 3 2 1 A1 CORNER A B 9.50±0.10 0.75 C 9.50±0.10 5.25 D E F G H A B C D E 2.625 F G H A B 8.00±0.10 A 1.875 0.75 3.75 B 8.00±0.10 0.65 MAX. 0.25 C 0.21±0.05 SEATING PLANE 0.26 MAX. C 1.20 MAX 0.15 C 0.15(4X) 51-85191-** UNLESS OTHERWISE SPECIFIED ALL DIMENSIONS ARE IN MILLIMETERS STANDARD TOLERANCES ON: DECIMALS + + + DRAWN ANGLES + DATE DESIGNED BY DATE HTN CHK BY 06/25/03 DATE .XX .XXX CYPRESS Company Confidential Document #: 001-44018 Rev. ** Page 10 of 11 [+] Feedback CY62177DV20 MoBL2™ Document History Page Document Title: CY62177DV20 MoBL2™ 32-Mbit (2M x 16) Static RAM Document Number: 001-44018 REV. ** ECN NO. 1910928 Issue Date See ECN Orig. of Change Description of Change VKN/AESA New Data Sheet © Cypress Semiconductor Corporation, 2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-44018 Rev. ** Revised January 08, 2008 Page 11 of 11 MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback