CY62177DV30

CY62177DV30 MoBL® 32-Mbit (2M x 16) Static RAM Features ■ ■ ■ Very high speed: 55 ns Wide voltage range: 2.20 V–3.60 V Ultra-low active power ❐ Typical active current: 2 mA @ f = 1 MHz ❐ Typical active current: 15 mA @ f = fmax Ultra low standby power Easy memory expansion with CE1, CE2 and OE features Automatic power-down when deselected Complementary metal oxide semiconductor (CMOS) for optimum speed/power Packages offered in a 48-ball fine ball grid array (FBGA) ■ ■ ■ ■ ■ applications such as cellular telephones.The device also has an automatic power-down feature that significantly reduces power consumption. The device can also be put into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE1HIGH or CE2 LOW), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE1 LOW, CE2 HIGH and WE LOW). Writing to the device is accomplished by taking Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A20). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A20). Reading from the device is accomplished by taking Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table for a complete description of read and write modes. Functional Description[1] The CY62177DV30 is a high-performance CMOS static RAM organized as 2M words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life (MoBL®) in portable Logic Block Diagram DATA-IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER 2048K × 16 RAM Array SENSE AMPS I/O0–I/O7 I/O8–I/O15 COLUMN DECODER BHE WE OE BLE A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 CE2 CE1 Power-down Circuit Note 1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation Document Number : 38-05633 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 25, 2011 [+] Feedback CY62177DV30 MoBL® Contents Product Portfolio .............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 5 Data Retention Waveform................................................. 6 Switching Characteristics ................................................ 6 Switching Waveforms ...................................................... 7 Truth Table ...................................................................... 10 Ordering Information ...................................................... 10 Ordering Code Definition ........................................... 10 Package Diagram ............................................................ 11 Acronyms ........................................................................ 12 Document Conventions ................................................. 12 Units of Measure ....................................................... 12 Sales, Solutions, and Legal Information ...................... 14 Worldwide Sales and Design Support ....................... 14 Products .................................................................... 14 PSoC Solutions ......................................................... 14 Document Number : 38-05633 Rev. *E Page 2 of 14 [+] Feedback CY62177DV30 MoBL® Pin Configuration[2] Figure 1. 48-Ball FBGA Top View 1 BLE I/O8 I/O9 VSS VCC I/O14 I/O15 A18 2 OE BHE I/O10 I/O11 3 A0 A3 A5 A17 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE1 I/O1 I/O3 I/O4 I/O5 WE A11 6 CE2 I/O0 I/O2 Vcc Vss I/O6 I/O7 A20 A B C D E F G H I/O12 DNU I/O13 A19 A8 A14 A12 A9 Product Portfolio Power Dissipation Product Min CY62177DV30LL 2.2 VCC Range (V) Typ[3] 3.0 Max 3.6 55 Speed (ns) Operating ICC(mA) f = 1 MHz Typ[3] 2 Max 4 15 f = fmax Typ[3] Max 30 Standby ISB2(A) Typ[3] 5 Max 50 Notes 2. DNU pins have to be left floating or tied to Vss to ensure proper application. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C. Document Number : 38-05633 Rev. *E Page 3 of 14 [+] Feedback CY62177DV30 MoBL® Maximum Ratings (Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.) Storage temperature ............................... –65 °C to + 150 °C Ambient temperature with power applied .......................................... –55 °C to + 125 °C Supply voltage to ground potential ...... –0.3 V to VCC + 0.3 V DC voltage applied to outputs in High Z state[4, 5] ............................... –0.3 V to VCC + 0.3 V DC input voltage[4, 5] ............................ –0.3 V to VCC + 0.3 V Output current into outputs (LOW) .............................. 20 mA Static discharge voltage........................................... >2001 V (per MIL-STD-883, method 3015) Latch-up current .....................................................>200 mA Operating Range Device CY62177DV30LL Range Ambient Temperature VCC[6] 2.20 V to 3.60 V Industrial –40 °C to +85 °C Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH Description Output HIGH voltage Output LOW voltage Input HIGH voltage IOH = –0.1 mA IOH = –1.0 mA IOL = 0.1 mA IOL = 2.1mA VCC = 2.2 V to 2.7 V VCC= 2.7 V to 3.6 V VIL IIX IOZ ICC ISB1 Input LOW voltage Input leakage current Output leakage current VCC operating supply current Automatic CE power-down current—CMOS inputs Automatic CE power-down current—CMOS inputs VCC = 2.2 V to 2.7 V VCC= 2.7 V to 3.6 V GND < VI < VCC GND < VO < VCC, output disabled f = fMAX = 1/tRC f = 1 MHz VCC = VCCmax IOUT = 0 mA CMOS levels – Test Conditions VCC = 2.20 V VCC = 2.70 V VCC = 2.20 V VCC = 2.70 V Min 2.0 2.4 – – 1.8 2.2 –0.3 -0.3 –1 –1 Typ[7] – – – – – – – – – – 15 2 5 Max – – 0.4 0.4 VCC +0.3V VCC +0.3V 0.6 0.8 +1 +1 30 4 100 Unit V V V V V V V V A A mA mA A CE1 > VCC0.2 V, CE2 < 0.2 V, VIN > VCC–0.2 V, VIN < 0.2 V) f = fMAX (address and data only), f = 0 (OE, WE, BHE and BLE), VCC=3.60 V CE1 > VCC 0.2 V, CE2 < 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0, VCC = 3.60 V ISB2 – 5 50 A Notes 4. VIL(min.) = –2.0 V for pulse durations less than 20 ns. 5. VIH(Max) = VCC + 0.75 V for pulse durations less than 20 ns. 6. Full Device AC operation requires linear VCC ramp from 0 to VCC(min) > 500 s. 7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C Document Number : 38-05633 Rev. *E Page 4 of 14 [+] Feedback CY62177DV30 MoBL® Capacitance Parameter[8, 9] CIN COUT Description Input capacitance Output capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = VCC(typ) Max. 12 12 Unit pF pF Thermal Resistance Parameter[9] JA JC Description Thermal resistance (Junction to ambient) Thermal resistance (Junction to case) Test Conditions Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit board BGA 55 16 Unit C/W C/W AC Test Loads and Waveforms VCC OUTPUT R1 VCC R2 10% GND Rise Time = 1 V/ns ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns 50 pF INCLUDING JIG AND SCOPE Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT V 2.5 V (2.2 V to 2.7 V) 16667 15385 8000 1.20 3.0 V (2.7 V to 3.6 V) 1103 1554 645 1.75 Unit    V Parameters R1 R2 RTH VTH Data Retention Characteristics (Over the Operating Range) Parameter VDR ICCDR Description VCC for data retention Data retention current VCC= 1.5 V CE1 > VCC0.2 V, CE2 < 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V Conditions Min 1.5 – Typ[10] – Max – 25 Unit V A tCDR[9] tR[11] Chip deselect to data retention time Operation recovery time 0 55 – – – – ns ns Notes 8. This applies for all packages. 9. Tested initially and after any design or process changes that may affect these parameters. 10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C 11. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 s or stable at VCC(min.) > 100 s. Document Number : 38-05633 Rev. *E Page 5 of 14 [+] Feedback CY62177DV30 MoBL® Data Retention Waveform[12, 13] VCC CE or BHE.BLE VCC, min. tCDR DATA RETENTION MODE VDR > 1.5 V VCC, min. tR Switching Characteristics Over the Operating Range Parameter[13, 14] READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE WRITE CYCLE[17] tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE Write cycle time CE LOW to write end Address set-up to write end Address hold from write end Address set-up to write start WE pulse width BLE/BHE LOW to write end Data set-up to write end Data hold from write end WE LOW to High WE HIGH to Low Z[15, 16] Z[15] 55 40 40 0 0 40 40 25 0 – 10 – – – – – – – – – 20 – ns ns ns ns ns ns ns ns ns ns ns Read cycle time Address to data valid Data hold from address change CE LOW to data valid OE LOW to data valid OE LOW to LOW CE LOW to Low Z[15] OE HIGH to High Z[15, 16] Z[15] Z[15, 16] CE HIGH to High 55 – 10 – – 5 – 10 – 0 – – 10 – – 55 – 55 25 – 20 – 20 – 55 55 – 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min Max Unit CE LOW HIGH to power-up CE HIGH to power-down BLE/BHE LOW to data valid BLE/BHE LOW to Low Z[15] Z[15, 16] BLE/BHE HIGH to HIGH Notes 12. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE. 13. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 14. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section. 15. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 16. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 17. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. Document Number : 38-05633 Rev. *E Page 6 of 14 [+] Feedback CY62177DV30 MoBL® Switching Waveforms Figure 2. Read Cycle 1 (Address Transition Controlled)[18, 19] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID Figure 3. Read Cycle 2 (OE Controlled)[19, 20, 21] tAA DATA VALID ADDRESS tRC CE tPD tACE tHZCE BHE/BLE tLZBE OE tDBE tHZBE tHZOE HIGH IMPEDANCE ICC ISB DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tPU tLZCE tDOE DATA VALID 50% 50% Notes 18. The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL. 19. WE is HIGH for read cycle. 20. Address valid prior to or coincident with CE, BHE, BLE transition LOW. 21. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. Document Number : 38-05633 Rev. *E Page 7 of 14 [+] Feedback CY62177DV30 MoBL® Switching Waveforms (continued) Figure 4. Write Cycle 1 (WE Controlled)[22, 23, 24, 25, 26] tWC ADDRESS tSCE CE tSA WE tAW tPWE tHA BHE/BLE tBW OE tSD DATA I/O See Note 24 tHD VALID DATA tHZOE Figure 5. Write Cycle 2 (CE Controlled)[22, 23, 24, 25, 26] tWC ADDRESS tSCE CE tSA tAW tPWE tHA WE tBW BHE/BLE OE tSD DATA I/O See Note 24 tHD VALID DATA t HZOE Notes 22. Data I/O is high impedance if OE = VIH. 23. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high-impedance state. 24. During this period, the I/Os are in output state and input signals should not be applied. 25. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 26. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. Document Number : 38-05633 Rev. *E Page 8 of 14 [+] Feedback CY62177DV30 MoBL® Switching Waveforms (continued) Figure 6. Write Cycle 3 (WE Controlled, OE LOW)[27, 28, 29] tWC ADDRESS tSCE CE BHE/BLE tBW tAW tHA tSA WE tPWE tSD DATA I/O See Note 29 tHD tLZWE VALID DATA tHZWE Figure 7. Write Cycle 4 (BHE/BLE Controlled, OE LOW)[27, 28, 29] tWC ADDRESS CE tSCE tAW BHE/BLE tSA WE tBW tHA tPWE tSD tHD DATA I/O See Note 29 VALID DATA Notes 27. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 28. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high-impedance state. 29. During this period, the I/Os are in output state and input signals should not be applied. Document Number : 38-05633 Rev. *E Page 9 of 14 [+] Feedback CY62177DV30 MoBL® Truth Table CE1 H X X L L L L L L L L L CE2 X L X H H H H H H H H H WE X X X H H H H H H L L L OE X X X L L L H H H X X X BHE X X H L H L L H L L H L BLE X X H L L H H L L L L H Inputs/Outputs High Z High Z High Z Data out (I/O0–I/O15) Data out (I/O0–I/O7); High Z (I/O8–I/O15) High Z (I/O0–I/O7); Data Out (I/O8–I/O15) High Z High Z High Z Data in (I/O0–I/O15) Data in (I/O0–I/O7); High Z (I/O8–I/O15) High Z (I/O0–I/O7); Data in (I/O8–I/O15) Mode Deselect/power-down Deselect/power-down Deselect/power-down Read Read Read Output disabled Output disabled Output disabled Write Write Write Power Standby (ISB) Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 55 Ordering Code CY62177DV30LL-55BAXI Package Diagram 51-85191 Package Type 48-ball FBGA (8 mm × 9.5mm × 1.2 mm) (Pb-free) Operating Range Industrial Ordering Code Definition CY 621 7 7D V30 LL 55 BAX I Temperature Grade I = Industrial Package Type = BAX :48-ball FBGA (Pb-free) Speed Grade = 55ns Low Power Voltage Range (3 V Typical) Bus Width = X16 D = 130nm Technology Density = 32 Mbit MoBL SRAM Family Company ID: CY = Cypress Document Number : 38-05633 Rev. *E Page 10 of 14 [+] Feedback CY62177DV30 MoBL® Package Diagram Figure 8. 48 ball FBGA (8 x 9.5 x 1.2 mm) (51-85191) 51-85191 *A Document Number : 38-05633 Rev. *E Page 11 of 14 [+] Feedback CY62177DV30 MoBL® Acronyms Acronym CMOS I/O SRAM FBGA input/output static random access memory fine ball grid array Description complementary metal oxide semiconductor Document Conventions Units of Measure Symbol °C A mA MHz ns pF V  W Unit of Measure degrees Celsius microamperes milliampere megahertz nanoseconds picofarads volts ohms watts Document Number : 38-05633 Rev. *E Page 12 of 14 [+] Feedback CY62177DV30 MoBL® Document History Page Document Title:CY62177DV30 MoBL® 32-Mbit (2M x 16) Static RAM Document #: 38-05633 REV. ** *A ECN NO. 251075 330363 Issue Date See ECN See ECN Orig. of Change AJU AJU Description of Change New Data Sheet Changed title of data sheet from CYM62177DV30 to CY62177DV30 Added second chip enable (CE2) Added footnote #12 on page 5 Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Changed ISB1 from 60 and 40 A to 100 A for the L and LL versions for both the 55 and the 70 ns speed bins respectively. Converted from Preliminary to Final Changed the ISB2(Max) from 40 A to 50 A for LL version of both 45 ns and 55 ns speed bins Changed the ICCDR(Max) from 20 A to 25 A for LL version Updated the Ordeing Information table Removed inactive parts from Ordering Information. Updated package diagram. Updated links in Sales, Solutions, and Legal Information. Updated datasheet as per template Removed CY62177DV30L related info Removed 70 ns speed bin related info Added Ordering Code Definition Added Acronyms and Units of Measure table *B 400960 See ECN NXR *C 469187 See ECN NXR *D 2896036 03/19/10 AJU *E 3153110 01/25/2011 RAME Document Number : 38-05633 Rev. *E Page 13 of 14 [+] Feedback CY62177DV30 MoBL® Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2006-2011. T6he information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number : 38-05633 Rev. *E Revised January 25, 2011 Page 14 of 14 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback