CY62177EV30 MoBL®
32-Mbit (2M × 16/4M × 8) Static RAM
32-Mbit (2M × 16/4M × 8) Static RAM
Features
Functional Description
■
Thin small outline package (TSOP) I configurable as 2M × 16
or as 4M × 8 static RAM (SRAM)
■
Very high speed
❐ 55 ns
■
Wide voltage range
❐ 2.2 V to 3.7 V
■
Ultra low standby power
❐ Typical standby current: 3 A
❐ Maximum standby current: 25 A
■
Ultra low active power
❐ Typical active current: 4.5 mA at f = 1 MHz
■
Easy memory expansion with CE1, CE2, and OE Features
■
Automatic power down when deselected
■
Complementary Metal Oxide Semiconductor (CMOS) for
optimum speed and power
■
Available in Pb-free 48-pin TSOP I package and 48-ball FBGA
package
The CY62177EV30 is a high performance CMOS static RAM
organized as 2M words by 16 bits and 4M words by 8 bits. This
device features advanced circuit design to provide ultra low
active current. It is ideal for providing More Battery Life
(MoBL®) in portable applications such as cellular telephones.
The device also has an automatic power down feature that
significantly reduces power consumption by 99 percent when
addresses are not toggling. The device can also be put into
standby mode when deselected (CE1 HIGH or CE2 LOW or both
BHE and BLE are HIGH). The input and output pins (I/O0 through
I/O15) are placed in a high impedance state when: deselected
(CE1HIGH or CE2 LOW), outputs are disabled (OE HIGH), both
Byte High Enable and Byte Low Enable are disabled (BHE, BLE
HIGH), or during a write operation (CE1 LOW, CE2 HIGH and WE
LOW).
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0 through
A20). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O8 through I/O15) is written to the location specified on the
address pins (A0 through A20). To read from the device, take
Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable
(OE) LOW while forcing the Write Enable (WE) HIGH. If Byte
Low Enable (BLE) is LOW, then data from the memory location
specified by the address pins appear on I/O0 to I/O7. If Byte High
Enable (BHE) is LOW, then data from memory appears on I/O8
to I/O15. See the Truth Table on page 11 for a complete
description of read and write modes.
Pin #13 of the 48 TSOP I package is an DNU pin that must be
left floating at all times to ensure proper application.
For a complete list of related resources, click here.
Logic Block Diagram
2M × 16
RAM Array
SENSE AMPS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
BYTE
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
BHE
WE
CE2
CE1
OE
BLE
Power-Down
Circuit
Cypress Semiconductor Corporation
Document Number: 001-09880 Rev. *O
•
198 Champion Court
BHE
BLE
•
CE2
CE1
San Jose, CA 95134-1709
•
408-943-2600
Revised February 16, 2018
CY62177EV30 MoBL®
Contents
Pin Configurations ........................................................... 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Document Number: 001-09880 Rev. *O
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagram ............................................................ 13
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support ....................... 19
Products .................................................................... 19
PSoC® Solutions ...................................................... 19
Cypress Developer Community ................................. 19
Technical Support ..................................................... 19
Page 2 of 19
CY62177EV30 MoBL®
Pin Configurations
Figure 1. 48-pin TSOP I pinout (Front View) [1, 2]
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE
CE2
DNU
BHE
BLE
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
Vss
I/O15/A21
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
Vcc
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
Vss
CE1
A0
Figure 2. 48-ball FBGA pinout (Top View)
1
2
3
4
5
6
BLE
OE
A0
A1
A2
CE2
A
I/O8
BHE
A3
A4
CE1
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
VSS
I/O11
A17
A7
I/O3
Vcc
D
VCC
I/O12 NC
A16
I/O4
Vss
E
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15
A19
A12
A13
WE
I/O7
G
A18
A8
A9
A10
A11
A20
H
Product Portfolio
Power Dissipation
VCC Range (V)
Product
CY62177EV30LL
Speed
(ns)
Min
Typ [3]
Max
2.2
3.0
3.7
55
Operating ICC (mA)
f = 1 MHz
Standby ISB2 (A)
f = fMax
Typ [3]
Max
Typ [3]
Max
Typ [3]
Max
4.5
5.5
35
45
3
25
Notes
1. DNU Pin# 13 needs to be left floating to ensure proper application.
2. The BYTE pin in the 48-pin TSOP I package has to be tied to VCC to use the device as a 2M × 16 SRAM.
The 48-pin TSOP I package can also be used as a 4M × 8 SRAM by tying the BYTE signal to VSS. In the 4M × 8 configuration, Pin 45 is A21, while BHE, BLE, and
I/O8 to I/O14 pins are not used.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
Document Number: 001-09880 Rev. *O
Page 3 of 19
CY62177EV30 MoBL®
DC input voltage [4, 5] ................... –0.3 V to VCC(max) + 0.3 V
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage
(per MIL-STD-883, method 3015) ......................... > 2001 V
Latch up current ..................................................... > 200 mA
Operating Range
Supply voltage
to ground potential [4, 5] ............... –0.3 V to VCC(max) + 0.3 V
DC voltage applied to outputs
in High Z state [4, 5] ...................... –0.3 V to VCC(max) + 0.3 V
Device
CY62177EV30LL
Range
Ambient
Temperature
VCC [6]
Industrial –40 °C to +85 °C 2.2 V to 3.7 V
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
55 ns
Min
Typ [7]
Max
VCC = 2.20 V
2.0
–
–
Unit
VOH
Output HIGH voltage
IOH = –0.1 mA
IOH = –1.0 mA
VCC = 2.70 V
2.4
–
–
V
VOL
Output LOW voltage
IOL = 0.1 mA
VCC = 2.20 V
–
–
0.4
V
IOL = 2.1 mA
VCC = 2.70 V
–
–
0.4
V
1.8
–
VCC + 0.3
V
VIH
Input HIGH voltage
VIL
Input LOW voltage
VCC = 2.2 V to 2.7 V
V
VCC= 2.7 V to 3.7 V
2.2
–
VCC + 0.3
V
VCC = 2.2 V to 2.7 V
–0.3
–
0.6
V
VCC= 2.7 V to 3.7 V
–0.3
–
0.7 [8]
V
–1
–
+1
A
IIX
Input leakage current
GND < VI < VCC
IOZ
Output leakage current
GND < VO < VCC, Output Disabled
–1
–
+1
A
ICC
VCC operating supply current
f = fMax = 1/tRC
–
35
45
mA
–
4.5
5.5
mA
–
3
25
A
f = 1 MHz
ISB2 [9, 10]
Automatic CE power down
current – CMOS inputs
VCC = VCC(max)
IOUT = 0 mA
CMOS levels
CE1 > VCC – 0.2 V or CE2 < 0.2 V or
(BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0,
VCC = 3.7 V
Notes
4. VIL(min) = –2.0 V for pulse durations less than 20 ns.
5. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
6. Full Device AC operation assumes a 100 s ramp time from 0 to VCC (min) and 200 s wait time after VCC stabilization.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
8. Under DC conditions the device meets a VIL of 0.8 V. However, in dynamic conditions Input LOW Voltage applied to the device must not be higher than 0.7 V.
9. The BYTE pin in the 48-pin TSOP I package has to be tied to VCC to use the device as a 2M × 16 SRAM.
The 48-pin TSOP I package can also be used as a 4M × 8 SRAM by tying the BYTE signal to VSS. In the 4M × 8 configuration, Pin 45 is A21, while BHE, BLE, and
I/O8 to I/O14 pins are not used.
10. Chip enables (CE1 and CE2), BYTE, and Byte Enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2/ICCDR spec. Other inputs can be left floating.
Document Number: 001-09880 Rev. *O
Page 4 of 19
CY62177EV30 MoBL®
Capacitance
Parameter [11]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
Max
Unit
15
pF
15
pF
FBGA
TSOP I
Unit
38.10
55.91
C/W
7.54
9.39
C/W
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Thermal Resistance
Parameter [11]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
AC Test Loads and Waveforms
R1
VCC
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
Figure 3. AC Test Loads and Waveforms
ALL INPUT PULSES
VCC
90%
90%
10%
10%
GND
Fall Time = 1 V/ns
R2
Rise Time = 1 V/ns
Equivalent to: THEVENIN EQUIVALENT
OUTPUT
RTH
V
Parameter
2.5 V
3.3 V
Unit
R1
16667
1103
R2
15385
1554
RTH
8000
645
VTH
1.20
1.75
V
Note
11. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-09880 Rev. *O
Page 5 of 19
CY62177EV30 MoBL®
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
Description
Conditions
VCC for data retention
ICCDR
[13]
Data retention current
VCC = 1.5 V,
Min
Typ [12]
Max
Unit
1.5
–
–
V
–
–
17
A
CE1 > VCC – 0.2 V or CE2 < 0.2 V, or
(BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
tCDR[14]
Chip deselect to data retention
time
0
–
–
ns
tR[15]
Operation recovery time
55
–
–
ns
Data Retention Waveform
VCC
Figure 4. Data Retention Waveform [16]
DATA RETENTION MODE
VCC(min)
VDR > 1.5 V
tCDR
VCC(min)
tR
CE1 or
BHE.BLE
CE2
or
Notes
12. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
13. Chip enables (CE1 and CE2), BYTE, Address Pin A20 and Byte Enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2/ICCDR spec. Other inputs
can be left floating.
14. Tested initially and after any design or process changes that may affect these parameters.
15. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
16. BHE.BLE is the AND of both BHE and BLE. Chip is deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
Document Number: 001-09880 Rev. *O
Page 6 of 19
CY62177EV30 MoBL®
Switching Characteristics
Over the Operating Range
Parameter [17, 18]
Description
55 ns
Min
Max
Unit
Read Cycle
tRC
Read cycle time
55
–
ns
tAA
Address to data valid
–
55
ns
tOHA
Data hold from address change
6
–
ns
tACE
CE1 LOW and CE2 HIGH to data valid
–
55
ns
tDOE
OE LOW to data valid
–
25
ns
5
–
ns
–
18
ns
tLZOE
tHZOE
OE LOW to LOW Z
[19]
OE HIGH to High Z
[19, 20]
[19]
tLZCE
CE1 LOW and CE2 HIGH to Low Z
10
–
ns
tHZCE
CE1 HIGH and CE2 LOW to High Z [19, 20]
–
18
ns
tPU
CE1 LOW and CE2 HIGH to power up
0
–
ns
tPD
CE1 HIGH and CE2 LOW to power down
–
55
ns
tDBE
BLE/BHE LOW to data valid
–
55
ns
tLZBE
BLE/BHE LOW to Low Z [19]
10
–
ns
–
18
ns
tHZBE
Write Cycle
BLE/BHE HIGH to HIGH Z
[19, 20]
[21, 22]
tWC
Write cycle time
55
–
ns
tSCE
CE1 LOW and CE2 HIGH to write end
40
–
ns
tAW
Address setup to write end
40
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address setup to write start
0
–
ns
tPWE
WE pulse width
40
–
ns
tBW
BLE/BHE LOW to write end
40
–
ns
tSD
Data setup to write end
25
–
ns
tHD
Data hold from Write End
0
–
ns
tHZWE
WE LOW to High Z [19, 20]
–
20
ns
10
–
ns
tLZWE
WE HIGH to Low Z
[19]
Notes
17. In an earlier revision of this device, under a specific application condition, READ and WRITE operations were limited to switching of the byte enable and/or chip enable
signals as described in the Application Note AN66311. However, the issue has been fixed and in production now, and hence, this Application Note is no longer
applicable. It is available for download on our website as it contains information on the date code of the parts, beyond which the fix has been in production.
18. Test conditions for all parameters other than tristate parameters assume signal transition time of 1 V/ns, timing reference levels of VCC(typ)/2, input pulse levels of 0
to VCC(typ), and output loading of the specified IOL/IOH as shown in Figure 3 on page 5.
19. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given
device.
20. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedence state.
21. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write
and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates
the write.
22. The minimum write pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be sum of tSD and tHZWE.
Document Number: 001-09880 Rev. *O
Page 7 of 19
CY62177EV30 MoBL®
Switching Waveforms
Figure 5. Read Cycle No. 1 (Address Transition Controlled) [23, 24]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 6. Read Cycle No. 2 (OE Controlled) [24, 25]
ADDRESS
tRC
CE1
tPD
CE2
tHZCE
tACE
BHE/BLE
tLZBE
tDBE
tHZBE
OE
tHZOE
tDOE
DATA OUT
VCC
SUPPLY
CURRENT
tLZOE
HIGH IMPEDANCE
tPU
HIGH
IMPEDANCE
DATA VALID
tLZCE
50%
50%
ICC
ISB
Notes
23. The device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH.
24. WE is HIGH for read cycle.
25. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH.
Document Number: 001-09880 Rev. *O
Page 8 of 19
CY62177EV30 MoBL®
Switching Waveforms (continued)
Figure 7. Write Cycle No. 1 (WE Controlled) [26, 27, 28, 29]
tWC
ADDRESS
tSCE
CE1
CE2
tAW
tSA
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
VALID DATA
NOTE 29
tHZOE
Figure 8. Write Cycle No. 2 (CE1 or CE2 Controlled) [26, 27, 28, 29]
tWC
ADDRESS
tSCE
CE1
CE2
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
VALID DATA
NOTE 29
tHZOE
Notes
26. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write
and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates
the write.
27. Data I/O is high impedance if OE = VIH.
28. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
29. During this period the I/Os are in output state and input signals should not be applied.
Document Number: 001-09880 Rev. *O
Page 9 of 19
CY62177EV30 MoBL®
Switching Waveforms (continued)
Figure 9. Write Cycle No. 3 (WE Controlled, OE LOW) [30]
tWC
ADDRESS
tSCE
CE1
CE2
tBW
BHE/BLE
tAW
tSA
WE
tHA
tPWE
tSD
DATA I/O
NOTE 31
tHD
VALID DATA
tLZWE
tHZWE
Figure 10. Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [30, 32]
tWC
ADDRESS
CE1
CE2
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
WE
tPWE
tSD
DATA I/O
NOTE 31
tHD
VALID DATA
Notes
30. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
31. During this period the I/Os are in output state and input signals should not be applied.
32. The minimum write pulse width for Write Cycle No. 3 (WE controlled, OE LOW) should be sum of tSD and tHZWE.
Document Number: 001-09880 Rev. *O
Page 10 of 19
CY62177EV30 MoBL®
Truth Table
CE1
H
CE2
[33]
X
X[33]
WE
X
OE
X
BHE
BLE
[33]
[33]
High Z
Deselect/Power Down
Standby (ISB)
[33]
High Z
Deselect/Power Down
Standby (ISB)
X
[33]
Power
L
X
X
X
X
H
H
High Z
Deselect/Power Down
Standby (ISB)
L
H
H
L
L
L
Data Out (I/O0–I/O15)
Read
Active (ICC)
L
H
H
L
H
L
High Z (I/O8–I/O15);
Data Out (I/O0–I/O7)
Read
Active (ICC)
L
H
H
L
L
H
Data Out (I/O8–I/O15);
High Z (I/O0–I/O7)
Read
Active (ICC)
L
H
L
X
L
L
Data In (I/O0–I/O15)
Write
Active (ICC)
L
H
L
X
H
L
High Z (I/O8–I/O15);
Data In (I/O0–I/O7)
Write
Active (ICC)
L
H
L
X
L
H
Data In (I/O8–I/O15);
High Z (I/O0–I/O7)
Write
Active (ICC)
L
H
H
H
L
H
High Z
Output Disabled
Active (ICC)
L
H
H
H
H
L
High Z
Output Disabled
Active (ICC)
L
H
H
H
L
L
High Z
Output Disabled
Active (ICC)
X
X
X
Mode
[33]
[33]
X
X
Input/Output
Note
33. The ‘X’ (Don’t care) state for the chip enables and byte enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these
pins is not permitted.
Document Number: 001-09880 Rev. *O
Page 11 of 19
CY62177EV30 MoBL®
Ordering Information
Speed
(ns)
Ordering Code
Package
Diagram
Package Type
Operating
Range
55
CY62177EV30LL-55ZXI
51-85183
48-pin TSOP I (12 × 18.4 × 1 mm) Pb-free
Industrial
55
CY62177EV30LL-55BAXI
51-85191
48 ball FBGA (8 × 9.5 × 1.2 mm) Pb-free
Industrial
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 621 7 7 E V30 LL - 55 Z,BA X I
Temperature Grade:
I = Industrial
X = Pb-free
Package Type:
Z = 48-pin TSOP I, BA = 48 ball FBGA
Speed Grade: 55 ns
Low Power
Voltage Range: V30 = 3 V (typical)
Process Technology: E = 90 nm
Bus Width = × 16
Density = 32-Mbit
621 = MoBL SRAM family
Company ID: CY = Cypress
Document Number: 001-09880 Rev. *O
Page 12 of 19
CY62177EV30 MoBL®
Package Diagram
Figure 11. 48-ball FBGA (8 × 9.5 × 1.2 mm) BA48J Package Outline, 51-85191
51-85191 *C
Document Number: 001-09880 Rev. *O
Page 13 of 19
CY62177EV30 MoBL®
Package Diagram (continued)
Figure 12. 48-pin TSOP I (12 × 18.4 × 1 mm) Z48A Package Outline, 51-85183
STANDARD PIN OUT (TOP VIEW)
2X (N/2 TIPS)
0.10
2X
2
1
N
SEE DETAIL B
A
0.10 C
A2
0.10
2X
8
R
B
E
(c)
5
e
N/2 +1
N/2
5
D1
D
0.20
2X (N/2 TIPS)
GAUGE PLANE
9
C
PARALLEL TO
SEATING PLANE
C
SEATING PLANE
4
0.25 BASIC
0°
A1
L
DETAIL A
B
A
B
SEE DETAIL A
0.08MM M C A-B
b
6
7
WITH PLATING
REVERSE PIN OUT (TOP VIEW)
e/2
3
1
N
7
c
c1
X
X = A OR B
b1
N/2
N/2 +1
SYMBOL
DIMENSIONS
MIN.
NOM.
MAX.
1.
2.
PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN): INK OR LASER MARK.
1.00
1.05
4.
TO BE DETERMINED AT THE SEATING PLANE
0.20
0.23
A2
0.95
0.17
0.22
b
0.17
c1
0.10
0.16
c
0.10
0.21
D
20.00 BASIC
18.40 BASIC
E
12.00 BASIC
5.
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE
MOLD PROTRUSION ON E IS 0.15mm PER SIDE AND ON D1 IS 0.25mm PER SIDE.
6.
DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08mm TOTAL IN EXCESS OF b DIMENSION AT MAX.
MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON LOWER RADIUS OR
THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD
TO BE 0.07mm .
7.
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
0.10mm AND 0.25mm FROM THE LEAD TIP.
8.
LEAD COPLANARITY SHALL BE WITHIN 0.10mm AS MEASURED FROM THE
SEATING PLANE.
0.50 BASIC
0
0°
R
0.08
0.60
0.70
8
0.20
48
-C- . THE SEATING PLANE IS
DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE
LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.
0.27
D1
0.50
DIMENSIONS ARE IN MILLIMETERS (mm).
3.
b1
N
NOTES:
0.15
0.05
L
DETAIL B
1.20
A
A1
e
BASE METAL
SECTION B-B
9. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
10. JEDEC SPECIFICATION NO. REF: MO-142(D)DD.
51-85183 *F
Document Number: 001-09880 Rev. *O
Page 14 of 19
CY62177EV30 MoBL®
Acronyms
Acronym
Document Conventions
Description
Units of Measure
BHE
Byte High Enable
BLE
Byte Low Enable
°C
degree Celsius
CE
Chip Enable
MHz
megahertz
CMOS
Complementary Metal Oxide Semiconductor
µA
microampere
I/O
Input/Output
mA
milliampere
OE
Output Enable
ms
millisecond
SRAM
Static Random Access Memory
ns
nanosecond
TSOP
Thin Small Outline Package
WE
Write Enable
Document Number: 001-09880 Rev. *O
Symbol
Unit of Measure
ohm
%
percent
pF
picofarad
ps
picosecond
V
volt
W
watt
Page 15 of 19
CY62177EV30 MoBL®
Document History Page
Document Title: CY62177EV30 MoBL®, 32-Mbit (2M × 16/4M × 8) Static RAM
Document Number: 001-09880
Revision
ECN
Orig. of
Change
Submission
Date
**
498562
NXR
08/31/2006
New data sheet.
*A
2544845
VKN /
PYRS
07/29/2008
Added 48-pin TSOP I package related information in all instances across the
document.
Removed 45 ns speed bin related information in all instances across the
document.
Added 70 ns speed bin related information in all instances across the
document.
Updated Electrical Characteristics:
Added Note 10 and referred the same note in ISB2 parameter.
Updated Ordering Information:
Updated part numbers.
Updated Package Diagram:
Added spec 51-85183 *A.
*B
2589750
VKN /
PYRS
10/15/2008
Updated Pin Configurations:
Updated Figure 1 (Changed pin functions of pin 10 from NC to A20 and pin 13
from A20 to DNU).
*C
2668432
VKN /
PYRS
03/03/2009
Removed 70 ns speed bin related information in all instances across the
document.
Added 55 ns speed bin related information in all instances across the
document.
Replaced 3.6 V with 3.7 V in VCC range in all instances across the document.
Updated Electrical Characteristics:
Changed maximum value of ICC parameter from 30 mA to 45 mA
corresponding to Test Condition “f = f(max)”.
Changed maximum value of ICC parameter from 2.8 mA to 4.5 mA
corresponding to Test Condition “f = 1 MHz”.
Removed ISB1 parameter and its details.
Changed maximum value of ISB2 parameter from 17 A to 25 A.
Referred Note 9 in ISB2 parameter.
Updated Note 10.
*D
2779867
VKN
10/06/2009
Changed status from Preliminary to Final.
Updated Electrical Characteristics:
Added details of VIL parameter corresponding to Test Condition “For TSOP I
Package”.
Added Note 8 and referred the same note in maximum value of VIL parameter
corresponding to Test Condition “For TSOP I Package”.
Changed typical value of ICC parameter from 28 mA to 35 mA corresponding
to Test Condition “f = f(max)”.
Changed typical value of ICC parameter from 2.2 mA to 4.5 mA corresponding
to Test Condition “f = 1 MHz”.
Changed maximum value of ICC parameter from 4.5 mA to 5.5 mA
corresponding to Test Condition “f = 1 MHz”.
Updated Capacitance:
Changed maximum value of COUT parameter from 10 pF to 15 pF.
Updated Thermal Resistance:
Replaced TBD with values in FBGA column.
Updated Switching Characteristics:
Changed minimum value of tOHA parameter from 10 ns to 6 ns.
Document Number: 001-09880 Rev. *O
Description of Change
Page 16 of 19
CY62177EV30 MoBL®
Document History Page (continued)
Document Title: CY62177EV30 MoBL®, 32-Mbit (2M × 16/4M × 8) Static RAM
Document Number: 001-09880
Revision
ECN
Orig. of
Change
Submission
Date
*E
2899662
AJU
03/26/2010
Updated Ordering Information:
Updated part numbers.
Updated Package Diagram:
spec 51-85191 – Changed revision from ** to *A.
spec 51-85183 – Changed revision from *A to *B.
*F
2927528
VKN
05/04/2010
Updated Electrical Characteristics:
Updated Note 10.
Updated Truth Table:
Added Note 33 and referred the same note in respective places.
Added Acronyms.
Updated to new template.
*G
3177000
AJU
02/18/2011
Removed 48-ball FBGA package related information in all instances in the
document.
Updated Features (Removed 48-ball FBGA package related information).
Updated Pin Configurations:
Removed 48-ball FBGA package related information.
Updated Note 1 (Replaced NC with DNU).
Updated Electrical Characteristics (Updated details in “Test Conditions”
column of ISB2 parameter).
Updated Thermal Resistance (Removed 48-ball FBGA package related
information).
Updated Data Retention Characteristics (Updated details in “Conditions”
column of ICCDR parameter).
Updated Ordering Information:
No change in part numbers.
Added Ordering Code Definitions.
Updated Package Diagram:
Removed spec 51-85191 *A.
Updated Acronyms.
Added Units of Measure.
Updated to new template.
*H
3295175
RAME
06/29/2011
Updated Functional Description:
Removed Note “For best practice recommendations, refer to the Cypress
application note System Design Guidelines.” and its reference.
Updated Package Diagram:
spec 51-85183 – Changed revision from *B to *C.
*I
3461953
TAVA
12/22/2011
Included 48-ball FBGA package related information in all instances in the
document.
Updated Ordering Information:
Updated part numbers.
Updated Package Diagram:
Added spec 51-85191 *B.
*J
4100342
VINI
08/21/2013
Updated Switching Characteristics:
Added Note 17 and referred the same note in “Parameter” column.
Updated Package Diagram:
spec 51-85191 – Changed revision from *B to *C.
Updated to new template.
Completing Sunset Review.
*K
4111710
NILE
09/12/2013
Updated Electrical Characteristics:
Updated Note 10.
Updated Data Retention Characteristics:
Updated Note 13.
Document Number: 001-09880 Rev. *O
Description of Change
Page 17 of 19
CY62177EV30 MoBL®
Document History Page (continued)
Document Title: CY62177EV30 MoBL®, 32-Mbit (2M × 16/4M × 8) Static RAM
Document Number: 001-09880
Revision
ECN
Orig. of
Change
Submission
Date
*L
4355423
MEMJ
04/29/2014
Updated Electrical Characteristics:
Updated Note 10 (Issue is fixed so pin A20 can be left floating in standby).
Updated Switching Characteristics:
Added Note 22 and referred the same note in Write Cycle (for tPWE parameter
in WE Controlled, OE LOW condition).
Updated Switching Waveforms:
Added Note 32 and referred the same note in Figure 10 (for tPWE parameter
in WE Controlled, OE LOW condition).
*M
4567826
VINI
11/12/2014
Updated Features:
Included 48-ball FBGA package related information.
Updated Functional Description:
Added “For a complete list of related resources, click here.” at the end.
Updated Maximum Ratings:
Referred Notes 4, 5 in “Supply voltage to ground potential”.
Completing Sunset Review.
*N
5017414
VINI
11/17/2015
Updated Thermal Resistance:
Replaced “2-layer” with “four-layer” in “Test Conditions” column.
Changed value of JA parameter corresponding to TSOP I package from
44.66 C/W to 55.91 C/W.
Changed value of JC parameter corresponding to TSOP I package from
12.12 C/W to 9.39 C/W.
Updated Package Diagram:
spec 51-85183 – Changed revision from *C to *D.
Updated to new template.
Completing Sunset Review.
*O
6073315
VINI
02/16/2018
Updated Package Diagram:
spec 51-85183 – Changed revision from *D to *F.
Updated to new template.
Document Number: 001-09880 Rev. *O
Description of Change
Page 18 of 19
CY62177EV30 MoBL®
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Arm® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
cypress.com/clocks
cypress.com/interface
Internet of Things
Memory
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
Cypress Developer Community
Community | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
Touch Sensing
cypress.com/touch
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2006-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-09880 Rev. *O
Revised February 16, 2018
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor Corporation.
Page 19 of 19
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