CY62256N
256-Kbit (32 K × 8) Static RAM
256-Kbit (32 K × 8) Static RA
Features
Functional Description
■
Temperature ranges
❐ Commercial: 0 °C to +70 °C
❐ Industrial: –40 °C to +85 °C
❐ Automotive-A: –40 °C to +85 °C
❐ Automotive-E: –40 °C to +125 °C
The CY62256N is a high performance CMOS static RAM
organized as 32K words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE) and active LOW
output enable (OE) and tristate drivers. This device has an
automatic power-down feature, reducing the power consumption
by 99.9 percent when deselected.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O0 through I/O7) is written into the memory location addressed
by the address present on the address pins (A0 through A14).
Reading the device is accomplished by selecting the device and
enabling the outputs, CE and OE active LOW, while WE remains
inactive or HIGH. Under these conditions, the contents of the
location addressed by the information on address pins are
present on the eight data input/output pins.
The input/output pins remain in a high impedance state unless
the chip is selected, outputs are enabled, and write enable (WE)
is HIGH.
For a complete list of related documentation, click here.
■
High speed: 55 ns
■
Voltage range: 4.5 V to 5.5 V operation
■
Low active power
❐ 275 mW (max)
■
Low standby power (LL version)
❐ 82.5 W (max)
■
Easy memory expansion with CE and OE Features
■
TTL-compatible inputs and outputs
■
Automatic power-down when deselected
■
CMOS for optimum speed and power
■
Available in Pb-free and non Pb-free 28-pin (600-mil) PDIP,
28-pin (300-mil) narrow SOIC, 28-pin TSOP I, and 28-pin
reverse TSOP I packages
Logic Block Diagram
I/O0
INPUTBUFFER
I/O1
32K x 8
ARRAY
I/O2
SENSE AMPS
ROW DECODER
A10
A9
A8
A7
A6
A5
A4
A3
A2
I/O3
I/O4
I/O5
CE
WE
COLUMN
DECODER
I/O6
POWER
DOWN
I/O7
Cypress Semiconductor Corporation
Document Number: 001-06511 Rev. *J
•
A12
A11
A1
A0
A13
A14
OE
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 28, 2017
CY62256N
Contents
Product Portfolio .............................................................. 3
Pin Configurations ........................................................... 3
Pin Definitions .................................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Typical DC and AC Characteristics .............................. 10
Document Number: 001-06511 Rev. *J
Truth Table ...................................................................... 11
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagrams .......................................................... 13
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 17
Worldwide Sales and Design Support ....................... 17
Products .................................................................... 17
PSoC® Solutions ...................................................... 17
Cypress Developer Community ................................. 17
Technical Support ..................................................... 17
Page 2 of 17
CY62256N
Product Portfolio
Power Dissipation
VCC Range (V)
Product
CY62256NLL Commercial
[1]
Speed (ns)
Min
Typ
Max
4.5
5.0
5.5
Operating, ICC (mA)
Typ
[1]
Standby, ISB2 (A)
Max
Typ[1]
Max
70
25
50
0.1
5
CY62256NLL Industrial
55/70
25
50
0.1
10
CY62256NLL Automotive-A
55/70
25
50
0.1
10
CY62256NLL Automotive-E
55
25
50
0.1
15
Pin Configurations
Figure 1. 28-pin DIP and Narrow SOIC pinout
Figure 2. 28-pin TSOP I and Reverse TSOP I pinout
Pin Definitions
Pin Number
Type
Description
1–10, 21, 23–26
Input
A0–A14. Address Inputs
11–13, 15–19,
Input/Output
I/O0–I/O7. Data lines. Used as input or output lines depending on operation
27
Input/Control WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is conducted
20
Input/Control CE. When LOW, selects the chip. When HIGH, deselects the chip
22
Input/Control OE. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pins behave as
outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins
14
Ground
28
Power Supply VCC. Power supply for the device
GND. Ground for the device
Note
1. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions
(TA = 25 °C, VCC). Parameters are guaranteed by design and characterization, and not 100% tested.
Document Number: 001-06511 Rev. *J
Page 3 of 17
CY62256N
Maximum Ratings
Output current into outputs (LOW) ............................. 20 mA
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 C to +150 C
Ambient temperature with
power applied .......................................... –55 C to +125 C
Supply voltage to ground potential
(pin 28 to pin 14) [2] .....................................–0.5 V to +7.0 V
DC voltage applied to outputs
in high Z State [2] ................................ –0.5 V to VCC + 0.5 V
DC input voltage [2] ............................. –0.5 V to VCC + 0.5 V
Static discharge voltage
(per MIL-STD-883, method 3015) ......................... > 2001 V
Latch-up current ................................................... > 200 mA
Operating Range
Ambient Temperature (TA) [3]
VCC
0 C to +70 C
5 V 10%
–40 C to +85 C
5 V 10%
Automotive-A
–40 C to +85 C
5 V 10%
Automotive-E
–40 C to +125 C
5 V 10%
Range
Commercial
Industrial
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
-55
-70
Unit
Min
Typ [4]
Max
Min
Typ [4]
Max
2.4
–
–
2.4
–
–
V
–
–
0.4
–
–
0.4
V
VOH
Output HIGH
voltage
VCC = Min, IOH = 1.0 mA
VOL
Output LOW
voltage
VCC = Min, IOL = 2.1 mA
VIH
Input HIGH
voltage
2.2
–
VCC + 0.5
2.2
–
VCC + 0.5
V
VIL
Input LOW
voltage
–0.5
–
0.8
–0.5
–
0.8
V
IIX
Input leakage
current
GND VI VCC
–0.5
–
+0.5
–0.5
–
+0.5
A
IOZ
Output leakage
current
GND VO VCC, output disabled
–0.5
–
+0.5
–0.5
–
+0.5
A
ICC
VCC operating
supply current
VCC = Max,
IOUT = 0 mA,
f = fMAX = 1/tRC
ISB1
ISB2
Automatic CE
power-down
current – TTL
inputs
Automatic CE
power-down
current – CMOS
inputs
LL - Commercial
–
–
–
–
25
50
mA
LL - Industrial
–
25
50
–
25
50
mA
LL - Automotive-A
–
25
50
–
25
50
mA
LL - Automotive-E
–
25
50
–
–
–
mA
Max. VCC, CE VIH, LL - Commercial
VIN VIH or VIN VIL,
LL - Industrial
f = fMAX
LL - Automotive-A
–
–
–
–
0.3
0.5
mA
–
0.3
0.5
–
0.3
0.5
mA
–
0.3
0.5
–
0.3
0.5
mA
LL - Automotive-E
–
0.3
0.5
–
–
–
mA
Max. VCC,
LL - Commercial
CE VCC 0.3 V,
LL - Industrial
VIN VCC 0.3 V, or
VIN 0.3 V, f = 0
LL - Automotive-A
–
–
–
–
0.1
5
A
–
0.1
10
–
0.1
10
A
–
0.1
10
–
0.1
10
A
LL - Automotive-E
–
0.1
15
–
–
–
A
Notes
2. VIL (min) = 2.0 V for pulse durations of less than 20 ns.
3. TA is the “Instant-On” case temperature.
4. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions
(TA = 25 °C, VCC). Parameters are guaranteed by design and characterization, and not 100% tested.
Document Number: 001-06511 Rev. *J
Page 4 of 17
CY62256N
Capacitance
Parameter [5]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
Max
Unit
6
pF
8
pF
TA = 25 C, f = 1 MHz, VCC = 5.0 V
Thermal Resistance
Parameter [5]
JA
Description
Test Conditions
Thermal resistance Still air, soldered on
(junction to ambient) a 4.25 × 1.125 inch,
4-layer printed
Thermal resistance
circuit board
(junction to case)
JC
DIP
SOIC
TSOP
RTSOP
Unit
75.61
76.56
93.89
93.89
C/W
43.12
36.07
24.64
24.64
C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
R1 1800
R1 1800
5V
OUTPUT
5V
ALL INPUT PULSES
OUTPUT
R2
990
100 pF
INCLUDING
JIG AND
SCOPE
(a)
3.0 V
R2
990
5 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
5 ns
< 5 ns
(b)
Equivalent to:
THÉVENIN EQUIVALENT
639
OUTPUT
1.77 V
Note
5. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-06511 Rev. *J
Page 5 of 17
CY62256N
Data Retention Characteristics
Parameter
Conditions [6]
Description
VDR
VCC for data retention
ICCDR
Data
retention
current
LL – Commercial
LL – Industrial/
Automotive-A
VCC = 2.0 V, CE VCC 0.3 V,
VIN VCC 0.3 V, or VIN 0.3 V
tCDR
Operation recovery time
Max
Unit
2.0
–
–
V
–
0.1
5
A
0.1
10
A
–
0.1
10
A
0
–
–
ns
CY62256NLL-55
55
–
–
ns
CY62256NLL-70
70
–
–
Chip deselect to data retention
time
tR[7]
Typ [7]
–
LL – Automotive-E
[7]
Min
Data Retention Waveform
Figure 4. Data Retention Waveform
DATA RETENTION MODE
VCC
3.0 V
tCDR
VDR 2 V
3.0 V
tR
CE
Notes
6. No input may exceed VCC + 0.5 V.
7. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions
(TA = 25 °C, VCC). Parameters are guaranteed by design and characterization, and not 100% tested.
Document Number: 001-06511 Rev. *J
Page 6 of 17
CY62256N
Switching Characteristics
Over the Operating Range
Parameter [8]
Description
CY62256N-55
CY62256N-70
Min
Max
Min
Max
Unit
Read Cycle
tRC
Read cycle time
55
–
70
–
ns
tAA
Address to data valid
–
55
–
70
ns
tOHA
Data hold from address change
5
–
5
–
ns
tACE
CE LOW to data valid
–
55
–
70
ns
tDOE
OE LOW to data valid
–
25
–
35
ns
5
–
5
–
ns
–
20
–
25
ns
tLZOE
tHZOE
OE LOW to low Z
[9]
OE HIGH to high Z
[9, 10]
[9]
tLZCE
CE LOW to low Z
5
–
5
–
ns
tHZCE
CE HIGH to high Z [9, 10]
–
20
–
25
ns
tPU
CE LOW to power-up
0
–
0
–
ns
CE HIGH to power-down
–
55
–
70
ns
tPD
Write Cycle
[11, 12]
tWC
Write cycle time
55
–
70
–
ns
tSCE
CE LOW to write end
45
–
60
–
ns
tAW
Address setup to write end
45
–
60
–
ns
tHA
Address hold from write end
0
–
0
–
ns
tSA
Address setup to write start
0
–
0
–
ns
tPWE
WE pulse width
40
–
50
–
ns
tSD
Data setup to write end
25
–
30
–
ns
tHD
Data hold from write end
0
–
0
–
ns
tHZWE
WE LOW to high Z [9, 10]
–
20
–
25
ns
5
–
5
–
ns
tLZWE
WE HIGH to low Z
[9]
Notes
8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH
and 100-pF load capacitance.
9. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
10. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage.
11. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can terminate
a Write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the Write.
12. The minimum write cycle time for Write Cycle No. 3 (WE Controlled, OE LOW) is the sum of tHZWE and tSD.
Document Number: 001-06511 Rev. *J
Page 7 of 17
CY62256N
Switching Waveforms
Figure 5. Read Cycle No. 1 [13, 14]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Figure 6. Read Cycle No. 2 [14, 15]
tRC
CE
tACE
OE
tHZOE
tHZCE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
DATA VALID
tPD
tPU
ICC
50%
50%
ISB
Notes
13. Device is continuously selected. OE, CE = VIL.
14. WE is HIGH for Read cycle.
15. Address valid prior to or coincident with CE transition LOW.
Document Number: 001-06511 Rev. *J
Page 8 of 17
CY62256N
Switching Waveforms (continued)
Figure 7. Write Cycle No. 1 (WE Controlled) [16, 17, 18]
tWC
ADDRESS
CE
tAW
tHA
tSA
WE
tPWE
OE
tSD
DATA I/O
NOTE 19
tHD
DATAIN VALID
tHZOE
Figure 8. Write Cycle No. 2 (CE Controlled) [16, 17, 18]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
WE
tSD
DATA I/O
tHD
DATAIN VALID
Figure 9. Write Cycle No. 3 (WE Controlled, OE LOW) [18, 20]
tWC
ADDRESS
CE
tAW
WE
tHA
tSA
tSD
DATA I/O
NOTE 19
tHZWE
tHD
DATAIN VALID
tLZWE
Notes
16. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can terminate
a Write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the Write.
17. Data I/O is high impedance if OE = VIH.
18. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
19. During this period, the I/Os are in output state and input signals should not be applied.
20. The minimum write cycle pulse width should be equal to the sum of tSD and tHZWE.
Document Number: 001-06511 Rev. *J
Page 9 of 17
CY62256N
Typical DC and AC Characteristics
1.4
1.2
0.8
0.6
VIN = 5.0V
TA = 25C
0.4
0.0
4.0
2.0
1.0
0.8
0.6
VCC = 5.0V
VIN = 5.0V
0.4
4.5
5.0
5.5
0.0
55
6.0
25
SUPPLY VOLTAGE (V)
1.6
1.3
1.4
NORMALIZED tAA
NORMALIZED tAA
1.4
1.2
TA = 25C
1.0
0.8
4.0
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
1.2
1.0
4.5
5.0
5.5
6.0
VCC = 5.0V
0.6
55
25
125
OUTPUT SOURCE CURRENT (mA)
120
105
140
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
120
100
80
60
VCC = 5.0V
TA = 25C
40
20
0
0.0
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
AMBIENT TEMPERATURE (C)
SUPPLY VOLTAGE (V)
25
AMBIENT TEMPERATURE (C)
0.8
0.9
VCC = 5.0V
VIN = 5.0V
–0.5
55
125
AMBIENT TEMPERATURE (C)
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
1.1
1.0
0.0
0.2
ISB
ISB
1.5
0.5
OUTPUT SINK CURRENT (mA)
0.2
2.5
ISB2 A
1.0
3.0
ICC
1.2
ICC
NORMALIZED ICC
NORMALIZED ICC, ISB
1.4
STANDBY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
100
80
VCC = 5.0V
TA = 25C
60
40
20
0
0.0
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
Document Number: 001-06511 Rev. *J
Page 10 of 17
CY62256N
Typical DC and AC Characteristics (continued)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
30.0
2.5
25.0
2.0
1.5
1.0
20.0
15.0
VCC = 4.5 V
TA = 25 C
10.0
0.5
0.0
0.0
1.25
5.0
1.0
2.0
3.0
4.0
5.0
0.0
SUPPLY VOLTAGE (V)
0
200
400
600
NORMALIZED ICC
3.0
DELTA tAA (ns)
NORMALIZED IPO
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
800 1000
NORMALIZED ICC vs. CYCLE TIME
1.00
VCC = 5.0 V
TA = 25 C
VIN = 5.0 V
0.75
0.50
10
CAPACITANCE (pF)
20
30
40
CYCLE FREQUENCY (MHz)
Truth Table
CE
H
WE
X
OE
X
Inputs/Outputs
High Z
Mode
Deselect/power-down
Power
Standby (ISB)
L
H
L
Data Out
Read
Active (ICC)
L
L
X
Data In
Write
Active (ICC)
L
H
H
High Z
Output Disabled
Active (ICC)
Document Number: 001-06511 Rev. *J
Page 11 of 17
CY62256N
Ordering Information
Speed
(ns)
55
70
Ordering Code
Package
Diagram
Package Type
Operating
Range
CY62256NLL55SNXI
51-85092 28-pin SNC (300 Mils) Narrow Body (Pb-free)
CY62256NLL55ZXI
51-85071 28-pin TSOP I (Pb-free)
Industrial
CY62256NLL55ZXA
51-85071 28-pin TSOP I (Pb-free)
Automotive-A
CY62256NLL55SNXE
51-85092 28-pin SNC (300 Mils) Narrow Body (Pb-free)
Automotive-E
CY62256NLL55ZXE
51-85071 28-pin TSOP I (Pb-free)
CY62256NLL70PXC
51-85017 28-pin (600 Mil) Molded DIP (Pb-free)
CY62256NLL70SNXC
51-85092 28-pin SNC (300 Mils) Narrow Body (Pb-free)
CY62256NLL70ZRXI
51-85074 28-pin Reverse TSOP I (Pb-free)
CY62256NLL70SNXA
51-85092 28-pin SNC (300 Mils) Narrow Body (Pb-free)
Commercial
Industrial
Automotive-A
Ordering Code Definitions
CY 62 256 N LL - XX XXX X
Temperature Grade: X = C or I or A or E
C = Commercial = 0 °C to +70 °C; I = Industrial = –40 °C to +85 °C;
A = Automotive-A = –40 °C to +85 °C; E = Automotive-E = –40 °C to +125 °C
Package Type: XXX = SNX or ZX or PX or ZRX
SNX = 28-pin SNC (Pb-free)
ZX= 28-pin TSOP I (Pb-free)
PX = 28-pin Molded DIP (Pb-free)
ZRX = 28-pin Reverse TSOP I (Pb-free)
Speed Grade: XX = 55 ns or 70 ns
Low Power
Nitride Seal Mask fix
Density: 256 kbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
Document Number: 001-06511 Rev. *J
Page 12 of 17
CY62256N
Package Diagrams
Figure 10. 28-pin PDIP (1.480 × 0.550 × 0.195 Inches) P28.6/PZ28.6 Package Outline, 51-85017
51-85017 *F
Figure 11. 28-pin SNC (300 Mils) SN28.3 (Narrow Body) Package Outline, 51-85092
51-85092 *E
Document Number: 001-06511 Rev. *J
Page 13 of 17
CY62256N
Package Diagrams (continued)
Figure 12. 28-pin TSOP I (8 × 13.4 × 1.2 mm) Z28 (Standard) Package Outline, 51-85071
51-85071 *J
Figure 13. 28-pin TSOP I (8 × 13.4 mm) Package Outline - Reverse, 51-85074
51-85074 *H
Document Number: 001-06511 Rev. *J
Page 14 of 17
CY62256N
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CMOS
Complementary Metal Oxide Semiconductor
I/O
Input/Output
°C
degree Celsius
SRAM
Static Random Access Memory
A
microampere
TSOP
Thin Small Outline Package
mA
milliampere
VFBGA
Very Fine-Pitch Ball Grid Array
MHz
megahertz
ns
nanosecond
ohm
pF
picofarad
V
volt
W
watt
Document Number: 001-06511 Rev. *J
Symbol
Unit of Measure
Page 15 of 17
CY62256N
Document History Page
Document Title: CY62256N, 256-Kbit (32 K × 8) Static RAM
Document Number: 001-06511
Revision
ECN
Orig. of
Change
Submission
Date
**
426504
NXR
See ECN
New data sheet.
*A
488954
NXR
See ECN
Added Automotive product
Updated ordering Information table
Description of Change
*B
2715270
VKN / AESA
06/05/2009
Updated POD of 28-Pin (600-Mil) Molded DIP package (Spec# 51-85017)
*C
2891344
VKN
03/12/2010
Added Table of Contents
Removed “L” product information
Updated Ordering Information table
Updated Package Diagrams (Figure 10, Figure 11, and Figure 12)
Updated Sales, Solutions, and Legal Information
*D
3119519
AJU
01/04/2011
Updated Ordering Information.
Added Ordering Code Definitions.
*E
3329873
RAME
07/27/11
Updated template and styles according to current Cypress standards.
Added acronyms and units.
Removed reference to AN1064 SRAM system guidelines.
Updated operation recovery time parameter under Data Retention
Characteristics on page 6.
*F
3433878
TAVA
11/09/11
Updated Package Diagrams.
*G
4122787
VINI
09/13/2013
Updated Package Diagrams:
spec 51-85092 – Changed revision from *D to *E.
Updated in new template.
Completing Sunset Review.
*H
4525875
VINI
10/06/2014
Updated Maximum Ratings:
Referred Note 2 in “Supply voltage to ground potential (pin 28 to pin 14)”.
Updated Package Diagrams:
spec 51-85071 – Changed revision from *I to *J.
spec 51-85074 – Changed revision from *G to *H.
Completing Sunset Review.
*I
4576406
VINI
01/16/2015
Added related documentation hyperlink in page 1.
Added Note 12 in Switching Characteristics.
Added note reference 12 in the Switching Characteristics table.
Added Note 20 in Switching Waveforms.
Added note reference 20 in Figure 9.
Updated Figure 10 in Package Diagrams (spec 51-85017 *E to *F).
*J
5718683
AESATMP7
04/28/2017
Updated Cypress Logo and Copyright.
Document Number: 001-06511 Rev. *J
Page 16 of 17
CY62256N
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
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cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/memory
PSoC
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cypress.com/go/psoc
cypress.com/go/touch
USB Controllers
Wireless/RF
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP| PSoC 6
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2006-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-06511 Rev. *J
Revised April 28, 2017
Page 17 of 17
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