CY7B9911-5JC

CY7B9911 RoboClock+™ Programmable Skew Clock Buffer Features ■ ■ ■ Functional Description The CY7B9911 High Speed Programmable Skew Clock Buffer (PSCB) offers user selectable control over system clock functions. This multiple output clock driver provides the system integrator with functions necessary to optimize the timing of high performance computer systems. Each of the eight individual TTL drivers, arranged in four pairs of user controllable outputs, can drive terminated transmission lines with impedances as low as 50Ω. They deliver minimal and specified output skews and full swing logic levels. Each output is hardwired to one of nine delay or function configurations. Delay increments of 0.6 to 1.5 ns are determined by the operating frequency with outputs able to skew up to ±6 time units from their nominal “zero” skew position. The completely integrated PLL allows cancellation of external load and transmission line delay effects. When this “zero delay” capability of the PSCB is combined with the selectable output skew functions, you can create output-to-output delays of up to ±12 time units. Divide-by-two and divide-by-four output functions are provided for additional flexibility in designing complex clock systems. When combined with the internal PLL, these divide functions enable distribution of a low frequency clock that is multiplied by two or four at the clock destination. This facility minimizes clock distribution difficulty enabling maximum system clock speed and flexibility. All output pair skew 2001V (per MIL-STD-883, Method 3015) Latch Up Current ..................................................... >200 mA Document Number: 38-07209 Rev. *B t 0 +6t t0 U Page 4 of 13 CY7B9911 RoboClock+™ Operating Range Range Commercial Ambient Temperature 0°C to +70°C VCC 5V ± 10% Electrical Characteristics Over the Operating Range CY7B9911 Parameter VOH VOL VIH VIL VIHH VIMM VILL IIH IIL IIHH IIMM IILL IOS ICCQ Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage (REF and FB inputs only) Input LOW Voltage (REF and FB inputs only) Three Level Input HIGH Voltage (Test, FS, xFn)[5] Three Level Input MID Voltage (Test, FS, xFn)[5] Three Level Input LOW Voltage (Test, FS, xFn)[5] Input HIGH Leakage Current (REF and FB inputs only) Input LOW Leakage Current (REF and FB inputs only) Input HIGH Current (Test, FS, xFn) Input MID Current (Test, FS, xFn) Input LOW Current (Test, FS, xFn) Output Short Circuit Current[5] Operating Current Used by Internal Circuitry Output Buffer Current per Output Pair[6] Power Dissipation per Output Pair[8] Min £ VCC £ Max Min £ VCC £ Max Min £ VCC £ Max VCC = Max, VIN = Max. VCC = Max, VIN = 0.4V VIN = VCC VIN = VCC/2 VIN = GND VCC = Max, VOUT = GND (25×C only) VCCN = VCCQ = Max, Com’l All Input Selects Open VCCN = VCCQ = Max, IOUT = 0 mA Input Selects Open, fMAX VCCN = VCCQ = Max, IOUT = 0 mA Input Selects Open, fMAX –50 –500 200 50 –200 –250 85 Test Conditions VCC = Min, IOH = – 16 mA VCC = Min, IOH =–40 mA VCC = Min, IOL = 46 mA VCC = Min, IOL = 46 mA 2.0 –0.5 VCC – 0.85 VCC/2 – 500 mV 0.0 VCC 0.8 VCC VCC/2 + 500 mV 0.85 10 V V V V V mA mA mA mA mA mA mA 0.45 V 2.4 Min Max Unit V ICCN 14 mA PD 78 mW Notes 5. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs glitch and the PLL requires an additional tLOCK time before all datasheet limits are achieved. 6. CY7B9911 must be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. 7. Total output current per output pair is approximated by the following expression that includes device current plus load current: CY7B9911:ICCN = [(4 + 0.11F) + [((835 – 3F)/Z) + (.0022FC)]N] x 1.1 Where F = frequency in MHz; C = capacitive load in pF; Z = line impedance in ohms; N = number of loaded outputs; 0, 1, or 2; FC = F * C. 8. Total power dissipation per output pair is approximated by the following expression that includes device power dissipation plus power dissipation due to the load circuit: CY7B9911:PD = [(22 + 0.61F) + [((1550 – 2.7F)/Z) + (.0125FC)]N] x 1.1. Document Number: 38-07209 Rev. *B Page 5 of 13 CY7B9911 RoboClock+™ Capacitance Test conditions assume signal transition times unless otherwise specified. Parameter CIN Description Input Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max 10 Unit pF AC Test Loads and Waveforms 5V R1 CL R1=130 R2=91 CL = 30 pF (Includes fixture and probe capacitance) 2.0V Vth =1.5V 0.8V 0.0V ≤1ns 3.0V 2.0V Vth =1.5V 0.8V ≤1ns R2 TTL AC Test Load (CY7B9911) TTL Input Test Waveform (CY7B9911) Document Number: 38-07209 Rev. *B Page 6 of 13 CY7B9911 RoboClock+™ Switching Characteristics Over the Operating Range[2, 10] CY7B9911–5 Parameter fNOM Description Operating Clock Frequency in MHz FS = LOW FS = MID [1, 2] [1, 2] [1, 2 , 3] CY7B9911–7 Max 30 50 100 Min 15 25 40 4.0 4.0 See Table 1 Typ Max 30 50 100 ns ns Unit MHz Min 15 25 40 4.0 4.0 See Table 1 Typ FS = HIGH tRPWH tRPWL tU tSKEWPR tSKEW0 tSKEW1 tSKEW2 tSKEW3 tSKEW4 tDEV tPD tODCV tPWH tPWL tORISE tOFALL tLOCK tJR REF Pulse Width HIGH REF Pulse Width LOW Programmable Skew Unit Zero Output Matched Pair Skew (XQ0, XQ1)[11, 12] Zero Output Skew (All Outputs)[11, 13] 0.1 0.25 0.6 0.5 0.5 0.5 0.25 0.5 0.7 1.2 0.9 1.2 1.25 0.1 0.3 0.6 1.0 0.7 1.2 0.25 0.75 1.0 1.7 1.4 1.9 1.65 ns ns ns ns ns ns ns ns ns ns ns ns ns ms ps ps Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)[11, 14] Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided)[11, 14] Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)[11, 14] Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted)[11, 14] Device-to-Device Skew[10, 15] Propagation Delay, REF Rise to FB Rise Output Duty Cycle Variation[18] 50%[17, 18] 0.15 0.15 RMS[10] Peak-to-Peak [10] –0.5 –1.0 0.0 0.0 +0.5 +1.0 2.0 2.5 –0.7 –1.2 0.0 0.0 +0.7 +1.2 2.5 3 Output HIGH Time Deviation from 50%[17, 18] Output LOW Time Deviation from Output Rise Time[17, 19] [17, 19] 1.0 1.0 1.5 1.5 0.5 25 200 0.15 0.15 1.5 1.5 2.5 2.5 0.5 25 200 Output Fall Time PLL Lock Time[20] Cycle-to-Cycle Output Jitter Notes 9. Test conditions assume signal transition times of 2 ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified. 10. Guaranteed by statistical correlation. Tested initially and after any design or process changes that affect these parameters. 11. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay is selected when all are loaded with 30 pF and terminated with 50Ω to 2.06V. 12. tSKEWPR is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0tU. 13. tSKEW0 is defined as the skew between outputs when they are selected for 0tU. Other outputs are divided or inverted but not shifted. 14. There are three classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2 or Divide-by-4 mode). 15. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC ambient temperature, air flow, and so on). 16. tODCV is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications. 17. Specified with outputs loaded with 30 pF. Devices are terminated through 50Ω to 2.06V. 18. tPWH is measured at 2.0V. tPWL is measured at 0.8V. 19. tORISE and tOFALL measured between 0.8V and 2.0V. 20. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits. Document Number: 38-07209 Rev. *B Page 7 of 13 CY7B9911 RoboClock+™ AC Timing Diagrams Figure 2. AC Timing Diagrams tREF tRPWH REF tPD tODCV tRPWL tODCV FB tJR Q tSKEWPR, tSKEW0, 1 OTHER Q tSKEWPR, tSKEW0, 1 tSKEW2 INVERTED Q tSKEW3, 4 tSKEW3, 4 REF DIVIDED BY 2 tSKEW1,3, 4 REF DIVIDED BY 4 tSKEW2 tSKEW3, 4 tSKEW2, 4 Document Number: 38-07209 Rev. *B Page 8 of 13 CY7B9911 RoboClock+™ Figure 3. Zero Skew and Zero Delay Clock Driver REF L1 Z0 LOAD SYSTEM CLOCK FB REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST LENGTH L1 = L2 = L3 = L4 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 LOAD L2 Z0 LOAD Z0 L4 Z0 LOAD L3 Operational Mode Descriptions Figure 2 shows the PSCB configured as a zero skew clock buffer. In this mode the 7B9911 is used as the basis for a low skew clock distribution tree. When all of the function select inputs (xF0, xF1) are left open, the outputs are aligned and each drive a terminated transmission line to an independent load. The FB input is tied to any output in this configuration and the operating frequency range is selected with the FS pin. The low skew specification, coupled with the ability to drive terminated transmission lines (with impedances as low as 50 ohms), enables efficient printed circuit board design. Figure 4. Programmable Skew Clock Driver REF Z0 LOAD L1 SYSTEM CLOCK FB REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 LENGTH L1 = L2 L3 < L2 by 6 inches L4 > L2 by 6 inches LOAD L2 Z0 LOAD Z0 LOAD Z0 L3 L4 Figure 3 shows a configuration to equalize skew between metal traces of different lengths. In addition to low skew between outputs, the PSCB is programmed to stagger the timing of its outputs. The four groups of output pairs are each programmed to different output timing. Skew timing is adjusted over a wide range in small increments with the appropriate strapping of the function select pins. In this configuration the 4Q0 output is sent to FB and configured for zero skew. The other three pairs of outputs are programmed to yield different skews relative to the feedback. By advancing the clock signal on the longer traces or retarding the clock signal on shorter traces, all loads receive the clock pulse at the same time. In this illustration the FB input is connected to an output with 0 ns skew (xF1, xF0 = MID) selected. The internal PLL synchronizes the FB and REF inputs and aligns their rising edges to make certain that all outputs have precise phase alignment. Clock skews is advanced by ±6 time units (tU) when using an output selected for zero skew as the feedback. There is a wider Page 9 of 13 Document Number: 38-07209 Rev. *B CY7B9911 RoboClock+™ range of delays, if the output connected to FB is also skewed. As “Zero Skew”, +tU, and –tU are defined relative to output groups and the PLL aligns the rising edges of REF and FB, wider output skews are created by proper selection of the xFn inputs. For example, a +10 tU between REF and 3Qx is achieved by connecting 1Q0 to FB and setting 1F0 = 1F1 = GND, 3F0 = MID, and 3F1 = High. (Since FB aligns at –4 tU and 3Qx skews to +6 tU, a total of +10 tU skew is realized.) Many other configurations are realized by skewing both the output used as the FB input and skewing the other outputs. Figure 5. Inverted Output Connections REF Figure 6. Frequency Multiplier with Skew Connections REF FB REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST 20 MHz 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 40 MHz 20 MHz 80 MHz FB REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 Figure 4 shows an example of the invert function of the PSCB. In this example the 4Q0 output used as the FB input is programmed for invert (4F0 = 4F1 = HIGH) while the other three pairs of outputs are programmed for zero skew. When 4F0 and 4F1 are tied high, 4Q0 and 4Q1 become inverted zero phase outputs. The PLL aligns the rising edge of the FB input with the rising edge of the REF. This causes the 1Q, 2Q, and 3Q outputs to become the “inverted” outputs with respect to the REF input. By selecting the output to connect to FB, you can have two inverted and six non-inverted outputs or six inverted and two non-inverted outputs. The correct configuration is determined by the need for more (or fewer) inverted outputs. 1Q, 2Q, and 3Q outputs is also skewed to compensate for varying trace delays independent of inversion on 4Q. Figure 5 illustrates the PSCB configured as a clock multiplier. The 3Q0 output is programmed to divide by four and is sent back to FB. This causes the PLL to increase its frequency until the 3Q0 and 3Q1 outputs are locked at 20 MHz while the 1Qx and 2Qx outputs run at 80 MHz. The 4Q0 and 4Q1 outputs are programmed to divide by two, that results in a 40 MHz waveform at these outputs. Note that the 20 and 40 MHz clocks fall simultaneously and are out of phase on their rising edge. This enables the designer to use the rising edges of the 1⁄2 frequency and 1⁄4 frequency outputs without concern for rising edge skew. The 2Q0, 2Q1, 1Q0, and 1Q1 outputs run at 80 MHz and are skewed by programming their select inputs accordingly. Note that the FS pin is wired for 80 MHz operation because that is the frequency of the fastest output. Figure 7. Frequency Divider Connections REF 20 MHz FB REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 10 MHz 5 MHz 20 MHz Figure 6 demonstrates the PSCB in a clock divider application. 2Q0 is fed back to the FB input and programmed for zero skew. 3Qx is programmed to divide by four. 4Qx is programmed to divide by two. Note that the falling edges of the 4Qx and 3Qx outputs are aligned. This enables use of the rising edges of the 1⁄2 frequency and 1⁄4 frequency without concern for skew mismatch. The 1Qx outputs are programmed to zero skew and are aligned with the 2Qx outputs. In this example, the FS input is grounded to configure the device in the 15 to 30 MHz range since the highest frequency output is running at 20 MHz. Document Number: 38-07209 Rev. *B Page 10 of 13 CY7B9911 RoboClock+™ Figure 7 shows some of the functions that are selectable on the 3Qx and 4Qx outputs. These include inverted outputs and outputs that offer divide-by-2 and divide-by-4 timing. An inverted output allows the system designer to clock different subsystems on opposite edges, without suffering from the pulse asymmetry typical of non-ideal loading. This function enables each of the two subsystems to clock 180 degrees out of phase, but still stay aligned within the skew specification. The divided outputs offer a zero delay divider for portions of the system that divides the clock by either two or four, and still remain within a narrow skew of the “1X” clock. Without this feature, addition of an external divider is required and the propagation delay of the divider adds to the skew between the different clock signals. These divided outputs, coupled with the Phase Locked Loop, enable the PSCB to multiply the clock rate at the REF input by either two or four. This mode enables the designer to distribute a low frequency clock between various portions of the system. It also locally multiplies the clock rate to a more suitable frequency, maintaining the low skew characteristics of the clock driver. The PSCB performs all of the functions described in this section at the same time. It can multiply by two and four or divide by two (and four) at the same time that it is shifting its outputs over a wide range or maintaining zero skew between selected outputs. Figure 8. Multi-Function Clock Driver REF Z0 20 MHz DISTRIBUTION CLOCK FB REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 80 MHz INVERTED LOAD 20 MHz Z0 LOAD 80 MHz ZEROSKEW 80 MHz SKEWED4ns Z0 LOAD Z0 LOAD Figure 9. Board-to-Board Clock Distribution LOAD Z0 L1 FB SYSTEM CLOCK REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST Z0 L2 Z0 LOAD 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 L4 FB REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST REF L3 Z0 LOAD 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 LOAD LOAD Document Number: 38-07209 Rev. *B Page 11 of 13 CY7B9911 RoboClock+™ Figure 8 shows the CY7B9911 connected in series to construct a zero-skew clock distribution tree between boards. Delays of the downstream clock buffers are programmed to compensate for the wire length (that is, select negative skew equal to the wire delay) necessary to connect them to the master clock source, approximating a zero delay clock tree. Cascaded clock buffers accumulate low frequency jitter because of the non-ideal filtering characteristics of the PLL filter. Do not connect more than two clock buffers in series. Ordering Information Accuracy (ps) 500 500 750 Ordering Code CY7B9911–5JC CY7B9911–5JCT CY7B9911–7JC [21] Package Type 32-Pb Plastic Leaded Chip Carrier 32-Pb Plastic Leaded Chip Carrier - Tape and Reel 32-Pb Plastic Leaded Chip Carrier Operating Range Commercial Commercial Commercial Note 21. Not recommended for the new design. Package Diagrams Figure 10. 32-Pin Plastic Leaded Chip Carrier J65 51-85002-*B Document Number: 38-07209 Rev. *B Page 12 of 13 CY7B9911 RoboClock+™ Document History Page Document Title: CY7B9911 RoboClock+™ Programmable Skew Clock Buffer Document Number: 38-07209 REV. ** *A *B ECN NO. 110342 1199925 1286064 Issue Date 12/21/01 Orig. of Change SZV Description of Change Change from Specification number: 38-00623 to 38-07209 See ECN KVM/AESA Added Tape and Reel part in Ordering Information Added note: Not recommended for the new design See ECN AESA Change status to final © Cypress Semiconductor Corporation, 2001-2007. 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Document Number: 38-07209 Rev. *B Revised June 20, 2007 Page 13 of 13 PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. RoboClock+ is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.