CY7B991
CY7B992
Programmable Skew Clock Buffer
Programmable Skew Clock Buffer
Features
Functional Description
■
All output pair skew 2001 V
Latch Up Current ................................................... > 200 mA
Document Number: 38-07138 Rev. *L
Page 6 of 21
CY7B991
CY7B992
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage (REF and
FB inputs only)
Input LOW Voltage (REF and
–0.5
FB inputs only)
Three Level Input HIGH
Min VCC Max
VCC – 0.85
Voltage (Test, FS, × Fn) [5]
Three Level Input MID Voltage Min VCC Max
VCC/2 –
(Test, FS, × Fn) [5]
500 mV
Three Level Input LOW
Min VCC Maximum
0.0
Voltage (Test, FS, × Fn) [5]
Input HIGH Leakage Current VCC = Max, VIN = Max.
–
(REF and FB inputs only)
Input LOW Leakage Current VCC = Max, VIN = 0.4 V
–500
(REF and FB inputs only)
Input HIGH Current (Test, FS, VIN = VCC
–
× Fn)
Input MID Current (Test, FS, VIN = VCC/2
–50
× Fn)
Input LOW Current (Test, FS, VIN = GND
–
× Fn)
Output Short Circuit Current [6] VCC = Max, VOUT
–
= GND (25 °C only)
Operating Current Used by VCCN = VCCQ = Max, Commercial
–
Internal Circuitry
All Input Selects Open Industrial
–
Output Buffer Current per
VCCN = VCCQ = Max,
–
Output Pair [7]
IOUT = 0 mA
Input Selects Open, fMAX
Power Dissipation per Output VCCN = VCCQ = Max,
–
Pair [5]
IOUT = 0 mA,
Input Selects Open, fMAX
VIL
VIHH
VIMM
VILL
IIH
IIL
IIHH
IIMM
IILL
IOS
ICCQ
ICCN
PD
VCC = Min IOH = –16 mA
VCC = Min, IOH =–40 mA
VCC = Min, IOL = 46 mA
VCC = Min, IOL = 46 mA
CY7B991
Min
Max
2.4
–
–
–
–
0.45
–
–
2.0
VCC
CY7B992
Min
Max
–
–
VCC –0.75
–
–
–
–
0.45
VCC – 1.35
VCC
Unit
V
V
V
0.8
–0.5
1.35
V
VCC
VCC – 0.85
VCC
V
VCC/2 +
500 mV
0.85
VCC/2 –
500 mV
0.0
VCC/2 +
500 mV
0.85
V
10
–
10
A
–
–500
–
A
200
–
200
A
50
–50
50
A
–200
–
–200
A
–250
–
N/A
mA
85
90
14
–
–
–
85
90
19
mA
78
–
104 [8]
mW
V
mA
Notes
5. Total power dissipation per output pair can be approximated by the following expression that includes device power dissipation plus power dissipation due to the load
circuit:
CY7B991:PD = [(22 + 0.61F) + [((1550 – 2.7F)/Z) + (.0125FC)]N] × 1.1
CY7B992:PD = [(19.25+ 0.94F) + [((700 + 6F)/Z) + (.017FC)]N] × 1.1
See note 7 for variable definition.
6. CY7B991 must be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. CY7B992 outputs must not
be shorted to GND. Doing so may cause permanent damage.
7. Total output current per output pair is approximated by the following expression that includes device current plus load current:
CY7B991: ICCN = [(4 + 0.11F) + [((835 – 3F)/Z) + (.0022FC)]N] × 1.1
CY7B992: ICCN = [(3.5 + 0.17F) + [((1160 – 2.8F)/Z) + (.0025FC)]N] × 1.1
Where
F = frequency in MHz; C = capacitive load in pF; Z = line impedance in ohms; N = number of loaded outputs; 0, 1, or 2; FC = F C.
8. Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-07138 Rev. *L
Page 7 of 21
CY7B991
CY7B992
Capacitance
Parameter [9]
CIN
Description
Test Conditions
Input Capacitance
TA = 25 °C, f = 1 MHz, VCC = 5.0 V
Max
Unit
10
pF
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
5V
R1
CL
R2
3.0V
R1=130
R2=91
CL = 50 pF (CL =30 pF for –2 and –5 devices)
(Includes fixture and probe capacitance)
2.0V
Vth =1.5V
0.8V
0.0V
TTL Input Test Waveform (CY7B991)
VCC
CL
1ns
1ns
TTL AC Test Load (CY7B991)
R1
2.0V
Vth =1.5V
0.8V
R1=100
R2=100
CL = 50 pF (CL =30 pF for –2 and –5 devices)
(Includes fixture and probe capacitance)
R2
CMOS AC Test Load (CY7B992)
VCC
80%
Vth = VCC/2
20%
0.0V
3ns
80%
Vth = VCC/2
20%
3ns
CMOS Input Test Waveform (CY7B992)
Note
9. CMOS output buffer current and power dissipation specified at 50 MHz reference frequency.
Document Number: 38-07138 Rev. *L
Page 8 of 21
CY7B991
CY7B992
Switching Characteristics
Over the Operating Range
Parameter [10, 11]
Description
FS = LOW [10, 13]
FS = MID [10, 13]
FS = HIGH [10, 13, 14]
CY7B991-2 [12]
CY7B992-2 [12]
Min
Typ
Max
Min
Typ
Max
15
–
30
15
–
30
25
–
50
25
–
50
40
–
80
40
–
80 [15]
5.0
–
–
5.0
–
–
5.0
–
–
5.0
–
–
See Table 1 on page 4
–
0.05
0.20
–
0.05
0.20
–
0.1
0.25
–
0.1
0.25
–
0.25
0.5
–
0.25
0.5
Unit
fNOM
Operating Clock Frequency
in MHz
tRPWH
tRPWL
tU
tSKEWPR
tSKEW0
tSKEW1
REF Pulse Width HIGH
REF Pulse Width LOW
Programmable Skew Unit
Zero Output Matched-Pair Skew (XQ0, XQ1) [16, 17]
Zero Output Skew (All Outputs) [16, 18, 19]
Output Skew (Rise-Rise, Fall-Fall, Same Class
Outputs) [16, 19]
tSKEW2
Output Skew (Rise-Fall, Nominal-Inverted,
Divided-Divided) [16, 19]
Output Skew (Rise-Rise, Fall-Fall, Different Class
Outputs) [16, 19]
–
0.3
0.5
–
0.3
0.5
ns
–
0.25
0.5
–
0.25
0.5
ns
tSKEW4
Output Skew (Rise-Fall, Nominal-Divided,
Divided-Inverted) [16, 19]
–
0.5
0.9
–
0.5
0.7
ns
tDEV
tPD
tODCV
tPWH
tPWL
tORISE
tOFALL
tLOCK
tJR
Device-to-Device Skew [12, 20]
Propagation Delay, REF Rise to FB Rise
Output Duty Cycle Variation [21]
Output HIGH Time Deviation from 50% [22, 23]
Output LOW Time Deviation from 50% [22, 23]
Output Rise Time [22, 24]
Output Fall Time [22, 24]
PLL Lock Time [25]
Cycle-to-Cycle Output Jitter RMS [12]
Peak-to-Peak [12]
–
–0.25
–0.65
–
–
0.15
0.15
–
–
–
–
0.0
0.0
–
–
1.0
1.0
–
–
–
0.75
+0.25
+0.65
2.0
1.5
1.2
1.2
0.5
25
200
–
–0.25
–0.5
–
–
0.5
0.5
–
–
–
–
0.0
0.0
–
–
2.0
2.0
–
–
–
0.75
+0.25
+0.5
3.0
3.0
2.5
2.5
0.5
25
200
ns
ns
ns
ns
ns
ns
ns
ms
ps
ps
tSKEW3
MHz
ns
ns
ns
ns
ns
Notes
10. The level is set on FS is determined by the “normal” operating frequency (fNOM) of the VCO and Time Unit Generator (see Logic Block Diagram). Nominal frequency
(fNOM) always appears at 1Q0 and the other outputs when they are operated in their undivided modes (see Table 2). The frequency appearing at the REF and FB
inputs are fNOM when the output connected to FB is undivided. The frequency of the REF and FB inputs are fNOM/2 or fNOM/4 when the part is configured for a
frequency multiplication by using a divided output as the FB input.
11. Test measurement levels for the CY7B991 are TTL levels (1.5 V to 1.5 V). Test measurement levels for the CY7B992 are CMOS levels (VCC/2 to VCC/2). Test
conditions assume signal transition times of 2 ns or less and output loading as shown in the Figure 3 on page 8 unless otherwise specified.
12. Guaranteed by statistical correlation. Tested initially and after any design or process changes that affect these parameters.
13. For all tristate inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry
holds an unconnected input to VCC/2.
14. When the FS pin is selected HIGH, the REF input must not transition upon power up until VCC has reached 4.3 V.
15. Except as noted, all CY7B992-2 and -5 timing parameters are specified to 80 MHz with a 30 pF load.
16. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay is selected when all are loaded with
50 pF and terminated with 50 to 2.06 V (CY7B991) or VCC/2 (CY7B992).
17. tSKEWPR is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0tU.
18. tSKEW0 is defined as the skew between outputs when they are selected for 0tU. Other outputs are divided or inverted but not shifted.
19. CL = 0 pF. For CL = 30 pF, tSKEW0 = 0.35 ns.
20. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC ambient temperature, air flow, and so on.)
21. tODCV is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.
22. Specified with outputs loaded with 30 pF for the CY7B99X-2 and -5 devices and 50 pF for the CY7B99X-7 devices. Devices are terminated through 50 to 2.06 V
(CY7B991) or VCC/2 (CY7B992).
23. tPWH is measured at 2.0 V for the CY7B991 and 0.8 VCC for the CY7B992. tPWL is measured at 0.8V for the CY7B991 and 0.2 VCC for the CY7B992.
24. tORISE and tOFALL measured between 0.8V and 2.0V for the CY7B991 or 0.8 VCC and 0.2 VCC for the CY7B992.
25. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter
is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
Document Number: 38-07138 Rev. *L
Page 9 of 21
CY7B991
CY7B992
Switching Characteristics
Over the Operating Range
Parameter [26, 27]
Description
FS = LOW [26, 28]
FS = MID [26, 28]
FS = HIGH [26, 28, 29]
CY7B991-5
CY7B992-5
Typ
Max
Min
Typ
Max
–
30
15
–
30
–
50
25
–
50
–
80
40
–
80 [30]
–
–
5.0
–
–
–
–
5.0
–
–
See Table 1 on page 4
–
0.1
0.25
–
0.1
0.25
–
0.25
0.5
–
0.25
0.5
–
0.6
0.7
–
0.6
0.7
Min
15
25
40
5.0
5.0
Unit
fNOM
Operating Clock
Frequency in MHz
tRPWH
tRPWL
tU
tSKEWPR
tSKEW0
tSKEW1
REF Pulse Width HIGH
REF Pulse Width LOW
Programmable Skew Unit
Zero Output Matched-Pair Skew (XQ0, XQ1) [31, 32]
Zero Output Skew (All Outputs) [31, 33]
Output Skew (Rise-Rise, Fall-Fall, Same Class
Outputs) [31, 34]
tSKEW2
Output Skew (Rise-Fall, Nominal-Inverted,
Divided-Divided) [31, 34]
Output Skew (Rise-Rise, Fall-Fall, Different Class
Outputs)[31, 34]
–
0.5
1.0
–
0.6
1.5
ns
–
0.5
0.7
–
0.5
0.7
ns
tSKEW4
Output Skew (Rise-Fall, Nominal-Divided,
Divided-Inverted) [31, 34]
–
0.5
1.0
–
0.6
1.7
ns
tDEV
tPD
tODCV
tPWH
tPWL
tORISE
tOFALL
tLOCK
tJR
Device-to-Device Skew [35, 36]
Propagation Delay, REF Rise to FB Rise
Output Duty Cycle Variation [21]
Output HIGH Time Deviation from 50% [38, 39]
Output LOW Time Deviation from 50% [38, 39]
Output Rise Time [38, 40]
Output Fall Time [38, 40]
PLL Lock Time [41]
Cycle-to-Cycle Output Jitter RMS [35]
Peak-to-Peak [35]
–
–0.5
–1.0
–
–
0.15
0.15
–
–
–
–
0.0
0.0
–
–
1.0
1.0
–
–
–
1.25
+0.5
+1.0
2.5
3
1.5
1.5
0.5
25
200
–
–0.5
–1.2
–
–
0.5
0.5
–
–
–
–
0.0
0.0
–
–
2.0
2.0
–
–
–
1.25
+0.5
+1.2
4.0
4.0
3.5
3.5
0.5
25
200
ns
ns
ns
ns
ns
ns
ns
ms
ps
ps
tSKEW3
MHz
ns
ns
ns
ns
ns
Notes
26. The level is set on FS is determined by the “normal” operating frequency (fNOM) of the VCO and Time Unit Generator (see Logic Block Diagram). Nominal frequency
(fNOM) always appears at 1Q0 and the other outputs when they are operated in their undivided modes (see Table 2). The frequency appearing at the REF and FB
inputs are fNOM when the output connected to FB is undivided. The frequency of the REF and FB inputs are fNOM/2 or fNOM/4 when the part is configured for a
frequency multiplication by using a divided output as the FB input.
27. Test measurement levels for the CY7B991 are TTL levels (1.5 V to 1.5 V). Test measurement levels for the CY7B992 are CMOS levels (VCC/2 to VCC/2). Test
conditions assume signal transition times of 2 ns or less and output loading as shown in the Figure 3 on page 8 unless otherwise specified.
28. For all tristate inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry
holds an unconnected input to VCC/2.
29. When the FS pin is selected HIGH, the REF input must not transition upon power up until VCC has reached 4.3 V.
30. Except as noted, all CY7B992-2 and -5 timing parameters are specified to 80 MHz with a 30 pF load.
31. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay is selected when all are loaded with
50 pF and terminated with 50 to 2.06 V (CY7B991) or VCC/2 (CY7B992).
32. tSKEWPR is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0tU.
33. tSKEW0 is defined as the skew between outputs when they are selected for 0tU. Other outputs are divided or inverted but not shifted.
34. CL = 0 pF. For CL = 30 pF, tSKEW0 = 0.35 ns.
35. Guaranteed by statistical correlation. Tested initially and after any design or process changes that affect these parameters.
36. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC ambient temperature, air flow, and so on.)
37. tODCV is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.
38. Specified with outputs loaded with 30 pF for the CY7B99X-2 and -5 devices and 50 pF for the CY7B99X-7 devices. Devices are terminated through 50 to 2.06 V
(CY7B991) or VCC/2 (CY7B992).
39. tPWH is measured at 2.0 V for the CY7B991 and 0.8 VCC for the CY7B992. tPWL is measured at 0.8V for the CY7B991 and 0.2 VCC for the CY7B992.
40. tORISE and tOFALL measured between 0.8V and 2.0V for the CY7B991 or 0.8 VCC and 0.2 VCC for the CY7B992.
41. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter
is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
Document Number: 38-07138 Rev. *L
Page 10 of 21
CY7B991
CY7B992
Switching Characteristics
Over the Operating Range
Parameter [42, 43]
Description
FS = LOW [42, 44]
FS = MID [42, 44]
FS = HIGH [42, 44]
CY7B991-7
CY7B992-7
Typ
Max
Min
Typ
Max
–
30
15
–
30
–
50
25
–
50
–
80
40
–
80 [45]
–
–
5.0
–
–
–
–
5.0
–
–
See Table 1 on page 4
–
0.1
0.25
–
0.1
0.25
–
0.3
0.75
–
0.3
0.75
–
0.6
1.0
–
0.6
1.0
Min
15
25
40
5.0
5.0
Unit
fNOM
Operating Clock Frequency
in MHz
tRPWH
tRPWL
tU
tSKEWPR
tSKEW0
tSKEW1
REF Pulse Width HIGH
REF Pulse Width LOW
Programmable Skew Unit
Zero Output Matched-Pair Skew (XQ0, XQ1) [46, 47]
Zero Output Skew (All Outputs) [46, 48]
Output Skew (Rise-Rise, Fall-Fall, Same Class
Outputs) [46, 49]
tSKEW2
Output Skew (Rise-Fall, Nominal-Inverted,
Divided-Divided) [46, 49]
Output Skew (Rise-Rise, Fall-Fall, Different Class
Outputs) [46, 49]
–
1.0
1.5
–
1.0
1.5
ns
–
0.7
1.2
–
0.7
1.2
ns
tSKEW4
Output Skew (Rise-Fall, Nominal-Divided,
Divided-Inverted) [16, 19]
–
1.2
1.7
–
1.2
1.7
ns
tDEV
tPD
tODCV
tPWH
tPWL
tORISE
tOFALL
tLOCK
tJR
Device-to-Device Skew[50, 51]
Propagation Delay, REF Rise to FB Rise
Output Duty Cycle Variation[52]
Output HIGH Time Deviation from 50%[53, 54]
Output LOW Time Deviation from 50%[53, 54]
Output Rise Time [53, 55]
Output Fall Time [53, 55]
PLL Lock Time [56]
Cycle-to-Cycle Output Jitter RMS[50]
Peak-to-Peak [50]
–
–0.7
–1.2
–
–
0.15
0.15
–
–
–
–
0.0
0.0
–
–
1.5
1.5
–
–
–
1.65
+0.7
+1.2
3
3.5
2.5
2.5
0.5
25
200
–
–0.7
–1.5
–
–
0.5
0.5
–
–
–
–
0.0
0.0
–
–
3.0
3.0
–
–
–
1.65
+0.7
+1.5
5.5
5.5
5.0
5.0
0.5
25
200
ns
ns
ns
ns
ns
ns
ns
ms
ps
ps
tSKEW3
MHz
ns
ns
ns
ns
ns
Notes
42. The level is set on FS is determined by the “normal” operating frequency (fNOM) of the VCO and Time Unit Generator (see Logic Block Diagram). Nominal frequency
(fNOM) always appears at 1Q0 and the other outputs when they are operated in their undivided modes (see Table 2). The frequency appearing at the REF and FB
inputs are fNOM when the output connected to FB is undivided. The frequency of the REF and FB inputs are fNOM/2 or fNOM/4 when the part is configured for a
frequency multiplication by using a divided output as the FB input.
43. Test measurement levels for the CY7B991 are TTL levels (1.5 V to 1.5 V). Test measurement levels for the CY7B992 are CMOS levels (VCC/2 to VCC/2). Test
conditions assume signal transition times of 2 ns or less and output loading as shown in the Figure 3 on page 8 unless otherwise specified.
44. For all tristate inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry
holds an unconnected input to VCC/2.
45. Except as noted, all CY7B992-2 and -5 timing parameters are specified to 80 MHz with a 30 pF load.
46. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay is selected when all are loaded with
50 pF and terminated with 50 to 2.06 V (CY7B991) or VCC/2 (CY7B992).
47. tSKEWPR is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0tU.
48. tSKEW0 is defined as the skew between outputs when they are selected for 0tU. Other outputs are divided or inverted but not shifted.
49. CL = 0 pF. For CL = 30 pF, tSKEW0 = 0.35 ns.
50. Guaranteed by statistical correlation. Tested initially and after any design or process changes that affect these parameters.
51. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC ambient temperature, air flow, and so on.)
52. tODCV is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.
53. Specified with outputs loaded with 30 pF for the CY7B99X-2 and -5 devices and 50 pF for the CY7B99X-7 devices. Devices are terminated through 50 to 2.06 V
(CY7B991) or VCC/2 (CY7B992).
54. tPWH is measured at 2.0 V for the CY7B991 and 0.8 VCC for the CY7B992. tPWL is measured at 0.8V for the CY7B991 and 0.2 VCC for the CY7B992.
55. tORISE and tOFALL measured between 0.8V and 2.0V for the CY7B991 or 0.8 VCC and 0.2 VCC for the CY7B992.
56. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter
is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
Document Number: 38-07138 Rev. *L
Page 11 of 21
CY7B991
CY7B992
AC Timing Diagrams
tREF
tRPWL
tRPWH
REF
tODCV
tPD
tODCV
FB
tJR
Q
tSKEWPR,
tSKEW0,1
tSKEWPR,
tSKEW0,1
OTHER Q
tSKEW2
tSKEW2
INVERTED Q
tSKEW3,4
tSKEW3,4
tSKEW3,4
REF DIVIDED BY 2
tSKEW1,3, 4
tSKEW2,4
REF DIVIDED BY 4
Document Number: 38-07138 Rev. *L
Page 12 of 21
CY7B991
CY7B992
Operational Mode Descriptions
Figure 4. Zero Skew and Zero Delay Clock Driver
REF
SYSTEM
CLOCK
LOAD
Z0
L1
FB
REF
FS
LOAD
4F0
4F1
4Q0
4Q1
3F0
3F1
2F0
2F1
3Q0
3Q1
1F0
1F1
1Q0
1Q1
L2
Z0
LOAD
L3
2Q0
2Q1
Z0
L4
LOAD
TEST
Z0
LENGTH L1 = L2 = L3 = L4
Figure 4 shows the PSCB configured as a zero skew clock
buffer. In this mode the 7B991/992 is used as the basis for a
low-skew clock distribution tree. When all of the function select
inputs (× F0, × F1) are left open, the outputs are aligned and each
drives a terminated transmission line to an independent load.
The FB input is tied to any output in this configuration and the
operating frequency range is selected with the FS pin. The
low-skew specification, coupled with the ability to drive
terminated transmission lines (with impedances as low as
50 ohms), enables efficient printed circuit board design.
Figure 5. Programmable Skew Clock Driver
REF
SYSTEM
CLOCK
FB
REF
FS
4F0
4F1
LOAD
L1
LOAD
4Q0
4Q1
3F0
3F1
2F0
2F1
3Q0
3Q1
1F0
1F1
1Q0
1Q1
Z0
L2
Z0
LOAD
L3
2Q0
2Q1
Z0
L4
LOAD
TEST
LENGTH L1 = L2
L3 < L2 by 6 inches
L4 > L2 by 6 inches
Figure 5 shows a configuration to equalize skew between metal
traces of different lengths. In addition to low skew between
outputs, the PSCB is programmed to stagger the timing of its
Document Number: 38-07138 Rev. *L
Z0
outputs. Each of the four groups of output pairs are programmed
to different output timing. Skew timing is adjusted over a wide
range in small increments with the appropriate strapping of the
Page 13 of 21
CY7B991
CY7B992
function select pins. In this configuration the 4Q0 output is fed
back to FB and configured for zero skew. The other three pairs
of outputs are programmed to yield different skews relative to the
feedback. By advancing the clock signal on the longer traces or
retarding the clock signal on shorter traces, all loads can receive
the clock pulse at the same time.
In this illustration the FB input is connected to an output with 0 ns
skew (× F1, × F0 = MID) selected. The internal PLL synchronizes
the FB and REF inputs and aligns their rising edges to ensure
that all outputs have precise phase alignment.
Clock skews are advanced by ±6 time units (tU) when using an
output selected for zero skew as the feedback. A wider range of
delays is possible if the output connected to FB is also skewed.
Since “Zero Skew”, +tU, and –tU are defined relative to output
groups, and since the PLL aligns the rising edges of REF and
FB, you can create wider output skews by proper selection of the
× Fn inputs. For example, a +10 tU between REF and 3Qx is
achieved by connecting 1Q0 to FB and setting 1F0 = 1F1 = GND,
3F0 = MID, and 3F1 = High. (Since FB aligns at –4tU and 3Qx
skews to +6tU, a total of +10tU skew is realized.) Many other
configurations are realized by skewing both the outputs used as
the FB input and skewing the other outputs.
Figure 6. Inverted Output Connections
REF
FB
REF
FS
4F0
4F1
4Q0
4Q1
3F0
3F1
3Q0
3Q1
2F0
2F1
2Q0
2Q1
1F0
1F1
1Q0
1Q1
TEST
Figure 6 shows an example of the invert function of the PSCB.
In this example the 4Q0 output used as the FB input is
programmed for invert (4F0 = 4F1 = HIGH) while the other three
pairs of outputs are programmed for zero skew. When 4F0 and
4F1 are tied high, 4Q0 and 4Q1 become inverted zero phase
outputs. The PLL aligns the rising edge of the FB input with the
rising edge of the REF. This causes the 1Q, 2Q, and 3Q outputs
to become the “inverted” outputs with respect to the REF input.
It is possible to have 2 inverted and 6 non-inverted outputs or 6
inverted and 2 non-inverted outputs by selecting the output
connected to FB. The correct configuration is determined by the
need for more (or fewer) inverted outputs. 1Q, 2Q, and 3Q
outputs can also be skewed to compensate for varying trace
delays independent of inversion on 4Q.
Document Number: 38-07138 Rev. *L
Figure 7. Frequency Multiplier with Skew Connections
REF
20 MHz
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
40 MHz
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
20 MHz
80 MHz
Figure 7 shows the PSCB configured as a clock multiplier. The
3Q0 output is programmed to divide by four and is sent to FB.
This causes the PLL to increase its frequency until the 3Q0 and
3Q1 outputs are locked at 20 MHz while the 1Qx and 2Qx
outputs run at 80 MHz. The 4Q0 and 4Q1 outputs are
programmed to divide by two, that results in a 40 MHz waveform
at these outputs. Note that the 20 and 40 MHz clocks fall
simultaneously and are out of phase on their rising edge. This
enables the designer to use the rising edges of the 1⁄2 frequency
and 1⁄4 frequency outputs without concern for rising edge skew.
The 2Q0, 2Q1, 1Q0, and 1Q1 outputs run at 80 MHz and are
skewed by programming their select inputs accordingly. Note
that the FS pin is wired for 80 MHz operation because that is the
frequency of the fastest output.
Figure 8. Frequency Divider Connections
REF
20 MHz
FB
REF
FS
4F0
4F1
4Q0
4Q1
10 MHz
3F0
3F1
2F0
2F1
3Q0
3Q1
5 MHz
1F0
1F1
TEST
1Q0
1Q1
2Q0
2Q1
20 MHz
Figure 8 demonstrates the PSCB in a clock divider application.
2Q0 is fed back to the FB input and programmed for zero skew.
3Qx is programmed to divide by four. 4Qx is programmed to
divide by two. Note that the falling edges of the 4Qx and 3Qx
outputs are aligned. This enables the use of rising edges of the
1⁄ frequency and 1⁄ frequency without concern for skew
2
4
mismatch. The 1Qx outputs are programmed to zero skew and
Page 14 of 21
CY7B991
CY7B992
are aligned with the 2Qx outputs. In this example, the FS input
is grounded to configure the device in the 15 MHz to 30 MHz
range since the highest frequency output is running at 20 MHz.
Figure 9 shows some of the functions that are selectable on the
3Qx and 4Qx outputs. These include inverted outputs and
outputs that offer divide-by-2 and divide-by-4 timing. An inverted
output enables the system designer to clock different
subsystems on opposite edges, without suffering from the pulse
asymmetry typical of non-ideal loading. This function enables
each of the two subsystems to clock 180 degrees out of phase
and align within the skew specifications.
The divided outputs offer a zero delay divider for portions of the
system that need the clock divided by either two or four, and still
remain within a narrow skew of the “1X” clock. Without this
feature, an external divider is added, and the propagation delay
of the divider adds to the skew between the different clock
signals.
These divided outputs, coupled with the Phase Locked Loop,
enables the PSCB to multiply the clock rate at the REF input by
either two or four. This mode enables the designer to distribute
a low frequency clock between various portions of the system,
and then locally multiply the clock rate to a more suitable
frequency, still maintaining the low skew characteristics of the
clock driver. The PSCB performs all of the functions described in
this section at the same time. It multiplies by two and four or
divides by two (and four) at the same time. In other words, it is
shifting its outputs over a wide range or maintaining zero skew
between selected outputs.
Figure 9. Multi-Function Clock Driver
REF
LOAD
Z0
20 MHz
DISTRIBUTION
CLOCK
80 MHz
INVERTED
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
Document Number: 38-07138 Rev. *L
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
LOAD
20 MHz
Z0
LOAD
80 MHz
ZERO SKEW
80 MHz
SKEWED –3.125 ns (–4tU)
Z0
LOAD
Z0
Page 15 of 21
CY7B991
CY7B992
Figure 10. Board-to-Board Clock Distribution
LOAD
REF
Z0
L1
FB
SYSTEM
CLOCK
REF
FS
4F0
4F1
LOAD
L2
4Q0
4Q1
3F0
3F1
2F0
2F1
3Q0
3Q1
1F0
1F1
1Q0
1Q1
Z0
LOAD
L3
2Q0
2Q1
Z0
L4
TEST
Z0
Figure 10 shows the CY7B991 and 992 connected in series to
construct a zero skew clock distribution tree between boards.
Delays of the downstream clock buffers are programmed to
compensate for the wire length (that is, select negative skew
equal to the wire delay) necessary to connect them to the master
Document Number: 38-07138 Rev. *L
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
LOAD
LOAD
clock source, approximating a zero delay clock tree. Cascaded
clock buffers accumulates low frequency jitter because of the
non-ideal filtering characteristics of the PLL filter. Do not connect
more than two clock buffers in series.
Page 16 of 21
CY7B991
CY7B992
Ordering Information
Accuracy
(ps)
500
Ordering Code
Package Type
Operating
Range
CY7B991-5JI
32-pin PLCC
Industrial
CY7B991-5JIT
32-pin PLCC - Tape and Reel
Industrial
750
CY7B991-7JI
32-pin PLCC
Industrial
750
CY7B992-7JC
32-pin PLCC
Commercial
CY7B992-7JCT
32-pin PLCC - Tape and Reel
Commercial
CY7B992-7JI
32-pin PLCC
Industrial
250
CY7B991-2JXC
32-pin PLCC
Commercial
CY7B991-2JXCT
32-pin PLCC - Tape and Reel
Commercial
500
CY7B991-5JXC
32-pin PLCC
Commercial
CY7B991-5JXCT
32-pin PLCC - Tape and Reel
Commercial
CY7B991-5JXI
32-pin PLCC
Industrial
CY7B991-5JXIT
32-pin PLCC - Tape and Reel
Industrial
CY7B991-7JXC
32-pin PLCC
Commercial
CY7B991-7JXCT
32-pin PLCC - Tape and Reel
Commercial
CY7B991-7JXI
32-pin PLCC
Industrial
CY7B992-5JXI (Not
32-pin PLCC
Recommended for New Designs)
Industrial
CY7B992-5JXIT
32-pin PLCC - Tape and Reel
Industrial
CY7B992-7JXC
32-pin PLCC
Commercial
CY7B992-7JXCT
32-pin PLCC - Tape and Reel
Commercial
Pb-free
750
500
750
Ordering Code Definitions
CY 7B99X – X
J
X
X
X
X = blank or T
blank = Tube; T = Tape and Reel
Temperature: X = C or I
C = Commercial; I = Industrial
X = Pb-free, blank = not Pb-free
Package Type: J = 32-pin PLCC package
Speed grade: X = 2 ps or 5 ps or 7 ps, based on propagation delay
Base part number: 7B99X = 7B991 or 7B992
7B991 = Clock buffer with TTL outputs
7B992 = Clock buffer with CMOS outputs
Company ID: CY = Cypress
Document Number: 38-07138 Rev. *L
Page 17 of 21
CY7B991
CY7B992
Package Diagram
Figure 11. 32-pin PLCC (0.453 × 0.553 inches) J32 Package Outline, 51-85002
51-85002 *D
Document Number: 38-07138 Rev. *L
Page 18 of 21
CY7B991
CY7B992
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CMOS
Complementary Metal-Oxide Semiconductor
FB
Feedback
LCC
Leadless Chip Carrier
PLCC
Plastic Leaded Chip Carrier
PLL
Phase-Locked Loop
mA
milliampere
PSCB
Programmable Skew Clock Buffers
ms
millisecond
TTL
Transistor-Transistor Logic
mW
milliwatt
VCO
Voltage Controlled Oscillator
ns
nanosecond
Document Number: 38-07138 Rev. *L
Symbol
Unit of Measure
°C
degree Celsius
MHz
megahertz
µA
microampere
ohm
%
percent
pF
picofarad
ps
picosecond
V
volt
Page 19 of 21
CY7B991
CY7B992
Document History Page
Document Title: CY7B991/CY7B992, Programmable Skew Clock Buffer
Document Number: 38-07138
Rev.
ECN
Orig. of
Change
Submission
Date
**
110247
SZV
12/19/01
Changed Specification number: 38-00513 to 38-07138.
*A
1199925
KVM /
AESA
See ECN
Updated Features (Remove Compatible with a Pentium™-based processor).
Updated Ordering Information (Added Pb-free part numbers, Update package
names in Ordering Information table).
*B
1286064
AESA
See ECN
Changed status from Preliminary to Final.
*C
2750166
TSAI
08/10/09
Post to external web.
*D
2761988
CXQ
09/10/09
Updated Ordering Information (Fixed Ordering Information table replacement
error of “lead” with “Pb”).
*E
2894960
KVM
03/18/10
Updated Ordering Information (Removed following obsolete parts from the
ordering information table: CY7B991-7LMB, CY7B992-7LMB, CY7B992-5JI,
CY7B992-5JIT).
Updated Package Diagram.
Updated sales links
Added Table of Contents.
*F
2905889
KVM
04/06/2010
Updated Ordering Information (Removed inactive part numbers
CY7B991-2JC, CY7B991-2JCT, CY7B991-5JC, CY7B991-5JCT,
CY7B991-7JC, CY7B991-7JCT, CY7B992-2JC and CY7B992-2JCT).
*G
2950368
KVM
06/11/2010
Updated Operating Range (Removed Military temperature range).
Removed Military Specifications.
Updated Ordering Information (Added part numbers CY7B992-7JXC and
CY7B992-7JXCT).
*H
3045340
BASH
10/07/2010
Updated Ordering Information (Removed inactive part numbers CY7B992-5JC
and CY7B992-5JCT).
Added Ordering Code Definitions.
*I
3201434
BASH
03/21/2011
Added Acronyms and Units of Measure.
*J
3560698
PURU
03/24/2012
Updated Ordering Information (Added part number CY7B991-7JXI).
Updated Package Diagram.
*K
4334627
CINM
04/06/2014
Updated in new template.
*L
4403827
AJU
06/10/2014
Updated Ordering Information:
No change in part numbers.
Added “Not Recommended for New Designs” against the MPN
“CY7B992-5JXI”.
Description of Change
Completing Sunset Review.
Document Number: 38-07138 Rev. *L
Page 20 of 21
CY7B991
CY7B992
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
cypress.com/go/memory
PSoC
cypress.com/go/psoc
Touch Sensing
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
cypress.com/go/touch
USB Controllers
Wireless/RF
psoc.cypress.com/solutions
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2001-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-07138 Rev. *L
Revised June 10, 2014
All products and company names mentioned in this document may be the trademarks of their respective holders.
Page 21 of 21
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