CY7B993V-2ACT

RoboClock CY7B993V CY7B994V High-speed Multi-phase PLL Clock Buffer Features • 500-ps max. Total Timing Budget™ (TTB™) window • 12–100-MHz (CY7B993V), or 24–200-MHz (CY7B994V) input/output operation • Matched pair output skew < 200 ps • Zero input-to-output delay • 18 LVTTL outputs driving 50Ω terminated lines • 16 outputs at 200 MHz: Commercial temperature • 6 outputs at 200 MHz: Industrial temperature • 3.3V LVTTL/LVPECL, fault-tolerant, and hot insertable reference inputs • Phase adjustments in 625-/1300-ps steps up to ± 10.4 ns • Multiply/divide ratios of 1–6, 8, 10, 12 • Individual output bank disable • Output high-impedance option for testing purposes • Fully integrated phase-locked loop (PLL) with lock indicator • 1100V (per MIL-STD-883, Method 3015) Latch-up Current.................................................. > ± 200 mA Operating Range Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 3.3V ± 10% 3.3V ± 10% Electrical Characteristics Over the Operating Range Parameter VOH VOL IOZ VIH Description LVTTL HIGH Voltage QFA[0:1], [1:4]Q[A:B][0:1] LOCK LVTTL LOW Voltage QFA[0:1], [1:4]Q[A:B][0:1] LOCK High-impedance State Leakage Current LVTTL Input HIGH FBK[A:B]±, REF[A:B]± REFSEL, FBSEL, FBDIS, DIS[1:4] VIL II IlH IlL LVTTL Input LOW LVTTL VIN >VCC LVTTL Input HIGH Current LVTTL Input LOW Current FBK[A:B]±, REF[A:B]± REFSEL, FBSEL, FBDIS, DIS[1:4] FBK[A:B]±, REF[A:B]± FBK[A:B]±, REF[A:B]± VCC = GND, VIN = 3.63V VCC = Max., VIN = VCC Min. < VCC < Max. Min. < VCC < Max. Test Conditions VCC = Min., IOH = –30 mA IOH = –2 mA, VCC = Min. VCC = Min., IOL= 30 mA IOL= 2 mA, VCC = Min. Min. 2.4 2.4 – – –100 2.0 2.0 –0.3 –0.3 – – – –500 –500 Min. < VCC < Max. Min. < VCC < Max. Min. < VCC < Max. 0.87*VCC Max. – – 0.5 0.5 100 VCC + 0.3 VCC + 0.3 0.8 0.8 100 500 500 – – – Unit V V V V µA V V V V µA µA µA µA µA V V V µA µA µA µA µA µA mV V V LVTTL Compatible Output Pins (QFA[0:1], [1:4]Q[A:B][0:1], LOCK) LVTTL Compatible Input Pins (FBKA±, FBKB±, REFA±, REFB±, FBSEL, REFSEL, FBDIS, DIS[1:4]) REFSEL, FBSEL, FBDIS, DIS[1:4] VIN = VCC FBK[A:B]±, REF[A:B]± VCC = Max., VIN = GND REFSEL, FBSEL, FBDIS, DIS[1:4] Three-level Input Pins (FBF0, FBDS[0:1], [1:4]F[0:1], [1:4]DS[0:1], FS, OUTPUT_MODE(TEST)) VIHH VIMM VILL IIHH IIMM IILL Three-level Input HIGH[6] Three-level Input MID Three-level Input HIGH Current Three-level Input MID Current Three-level Input LOW Current [6] Three-level Input LOW[6] FBF0 0.47*VCC 0.53*VCC – 0.13*VCC – – –50 –100 –200 –400 400 1.0 GND 200 400 50 100 – – VCC VCC VCC – 0.4 Three-level input pins excl. FBF0 VIN = VCC Three-level input pins excl. FBF0 VIN = VCC/2 FBF0 Three-level input pins excl. FBF0 VIN = GND FBF0 LVDIFF Input Pins (FBK[A:B]±, REF[A:B]±) VDIFF VIHHP VILLP VCOM Input Differential Voltage Highest Input HIGH Voltage Lowest Input LOW Voltage Common Mode Range (crossing voltage) 0.8 VCC V Notes: 5. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 6. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold the unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time before all data sheet limits are achieved. Document #: 38-07127 Rev. *F Page 8 of 15 RoboClock CY7B993V CY7B994V Electrical Characteristics Over the Operating Range (continued) Parameter ICCI ICCN Description Internal Operating Current Output Current Dissipation/Pair[8] CY7B993V CY7B994V CY7B993V CY7B994V VCC = Max., CLOAD = 25 pF, RLOAD = 50Ω at VCC/2, fMAX Test Conditions VCC = Max., fMAX[7] Min. – – – – Max. 250 250 40 50 Unit mA mA mA mA Operating Current Capacitance Parameter CIN Description Input Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Min. Max. 5 Unit pF Switching Characteristics Over the Operating Range[9, 10, 11, 12, 13] CY7B993/4V-2 Parameter fin fout tSKEWPR tSKEWBNK tSKEW0 tSKEW1 tSKEW2 Clock Input Frequency Clock Output Frequency Matched-Pair Skew[14, 15] Description CY7B993V CY7B994V CY7B993V CY7B994V Intrabank Skew[14, 15] Output-Output Skew (same frequency and phase, rise to rise, fall to fall)[14, 15] Output-Output Skew (same frequency and phase, other banks at different frequency, rise to rise, fall to fall)[14, 15] Output-Output Skew (invert to nominal of different banks, compared banks at same frequency, rising edge to falling edge aligned, other banks at same frequency)[14, 15] Output-Output Skew (all output configurations outside of tSKEW1and tSKEW2)[14, 15] Complementary Outputs Skew (crossing to crossing, complementary outputs of the same bank)[14, 15, 16, 17] Cycle-to-Cycle Jitter (divide by 1 output frequency, FB = divide by 1, 2, 3) Cycle-to-Cycle Jitter (divide by 1 output frequency, FB = divide by 4, 5, 6, 8, 10, 12) Propagation Delay, REF to FB Rise Min. 12 24 12 24 – – – – – Typ. – – – – – – – – – Max. 100 200 100 200 200 200 250 250 250 CY7B993/4V-5 Min. 12 24 12 24 – – – – – Typ. – – – – – – – – – Max. 100 200 100 200 200 250 550 650 700 Unit MHz MHz MHz MHz ps ps ps ps ps tSKEW3 tSKEWCPR tCCJ1-3 tCCJ4-12 tPD – – – – –250 – – 50 50 – 500 200 150 100 250 – – – – –500 – – 50 50 – 800 300 150 100 500 ps ps ps Peak ps Peak ps Notes: 7. ICCI measurement is performed with Bank1 and FB Bank configured to run at maximum frequency (fNOM = 100 MHz for CY7B993V, fNOM = 200 MHz for CY7B994V), and all other clock output banks to run at half the maximum frequency. FS and OUTPUT_MODE are asserted to the HIGH state. 8. This is dependent upon frequency and number of outputs of a bank being loaded. The value indicates maximum ICCN at maximum frequency and maximum load of 25 pF terminated to 50Ω at VCC/2. 9. This is for non-three level inputs. 10. Assumes 25-pF max. load capacitance up to 185 MHz. At 200 MHz the max. load is 10 pF. 11. Both outputs of pair must be terminated, even if only one is being used. 12. Each package must be properly decoupled. 13. AC parameters are measured at 1.5V unless otherwise indicated. 14. Test Load CL= 25 pF, terminated to VCC/2 with 50Ω up to185 MHz and 10-pF load to 200 MHz. 15. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same phase delay has been selected when all outputs are loaded with 25 pF and properly terminated up to 185 MHz. At 200 MHz the max load is 10 pF. 16. Complementary output skews are measured at complementary signal pair intersections. 17. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-07127 Rev. *F Page 9 of 15 RoboClock CY7B993V CY7B994V Switching Characteristics Over the Operating Range[9, 10, 11, 12, 13] (continued) CY7B993/4V-2 Parameter TTB tPDDELTA tREFpwh tREFpwl tr/tf tLOCK tRELOCK1 tRELOCK2 tODCV tPWH tPWL tPDEV tOAZ tOAZ 18] CY7B993/4V-5 Min. – – 2.0 2.0 0.15 – – – –1.0 – – – 1.0 0.5 Typ. – – – – – – Max. 700 200 – – 2.0 10 500 1000 1.0 1.5 2.0 0.025 10 14 Unit ps ps ns ns ns ms µs µs ns ns ns UI ns ns Description Total Timing Budget window (same frequency and phase) [17, Min. – – 2.0 2.0 0.15 – – – –1.0 – – – 1.0 0.5 Typ. – – – – – – Max. 500 200 – – 2.0 10 500 1000 1.0 1.5 2.0 0.025 10 14 Propagation Delay difference between two devices[17] REF input (Pulse Width HIGH) REF input (Pulse Width LOW) Output Rise/Fall Time [20] [19] [19] PLL Lock Time From Power-up PLL Relock Time (from same frequency, different phase) with Stable Power Supply PLL Relock Time (from different frequency, different phase) with Stable Power Supply[21] Output duty cycle deviation from 50%[13] Output HIGH time deviation from 50%[22] Output LOW time deviation from 50%[22] Period deviation when changing from reference to reference[23] DIS[1:4]/FBDIS HIGH to output high-impedance from ACTIVE[14, 24] DIS[1:4]/FBDIS LOW to output ACTIVE from output high-impedance[24, 25] AC Test Loads and Waveform[26] 3.3V For LOCK output only R1 = 910Ω R2 = 910Ω CL < 30 pF OUTPUT For all other outputs R1 = 100Ω CL R2 = 100Ω CL < 25 pF to 185 MHz or 10 pF at 200 MHz (Includes fixture and probe capacitance) R1 R2 (a) LVTTL AC Test Load 3.3V GND < 1 ns 2.0V 0.8V 2.0V 0.8V < 1 ns (b) TTL Input Test Waveform Notes: 18. TTB is the window between the earliest and the latest output clocks with respect to the input reference clock across variations in output frequency, supply voltage, operating temperature, input clock edge rate, and process. The measurements are taken with the AC test load specified and include output-output skew, cycle-cycle jitter, and dynamic phase error. TTB will be equal to or smaller than the maximum specified value at a given frequency. 19. Tested initially and after any design or process changes that may affect these parameters. 20. Rise and fall times are measured between 2.0V and 0.8V. 21. fNOM must be within the frequency range defined by the same FS state. 22. tPWH is measured at 2.0V. tPWL is measured at 0.8V. 23. UI = Unit Interval. Examples: 1 UI is a full period. 0.1UI is 10% of period. 24. Measured at 0.5V deviation from starting voltage. 25. For tOZA minimum, CL = 0 pF. For tOZA maximum, CL= 25 pF to 185 MHz or 10 pF to 200 MHz. 26. These figures are for illustrations only. The actual ATE loads may vary. Document #: 38-07127 Rev. *F Page 10 of 15 RoboClock CY7B993V CY7B994V AC Timing Diagrams[13] tREFpwl tREFpwh REF tPD t PWH 2.0V FB 0.8V tCCJ1-3,4-12 Q [1:4]QA[0:1] t SKEWBNK REF TO DEVICE 1 and 2 [1:4]QB[0:1] tODCV tPD FB DEVICE1 tPDELTA FB DEVICE2 tPDELTA Q t SKEW0,1 Other Q t SKEW0,1 t SKEWBNK t PWL QFA0 or [1:4]Q[A:B]0 t SKEWPR QFA1 or [1:4]Q[A:B]1 t SKEWPR tODCV tSKEWCPR Q tSKEW2 INVERTED Q tSKEW2 COMPLEMENTARY A crossing COMPLEMENTARY B crossing Ordering Information Propagation Max. Speed Delay (ps) (MHz) 250 250 250 250 250 250 250 250 250 250 250 250 100 100 100 100 200 200 200 200 200 200 200 200 Ordering Code CY7B993V-2AC CY7B993V-2ACT CY7B993V-2AI CY7B993V-2AIT CY7B994V-2AC CY7B994V-2ACT CY7B994V-2BBC CY7B994V-2BBCT CY7B994V-2AI CY7B994V-2AIT CY7B994V-2BBI CY7B994V-2BBIT Package Type 100-lead Thin Quad Flat Pack 100-lead Thin Quad Flat Pack - Tape and Reel 100-lead Thin Quad Flat Pack 100-lead Thin Quad Flat Pack - Tape and Reel 100-lead Thin Quad Flat Pack 100-lead Thin Quad Flat Pack - Tape and Reel 100-ball Thin Ball Grid Array 100-ball Thin Ball Grid Array - Tape and Reel 100-lead Thin Quad Flat Pack 100-lead Thin Quad Flat Pack - Tape and Reel 100-ball Thin Ball Grid Array 100-ball Thin Ball Grid Array -Tape and Reel Operating Range Commercial Commercial Industrial Industrial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Document #: 38-07127 Rev. *F Page 11 of 15 RoboClock CY7B993V CY7B994V Ordering Information (continued) Propagation Max. Speed Delay (ps) (MHz) 500 500 500 500 500 500 500 500 500 500 500 500 Lead-free 250 250 250 250 250 250 250 250 250 250 250 250 500 500 500 500 500 500 500 500 500 500 500 500 100 100 100 100 200 200 200 200 200 200 200 200 100 100 100 100 200 200 200 200 200 200 200 200 CY7B993V-2AXC CY7B993V-2AXCT CY7B993V-2AXI CY7B993V-2AXIT CY7B994V-2AXC CY7B994V-2AXCT CY7B994V-2BBXC CY7B994V-2AXI CY7B994V-2AXIT CY7B994V-2BBXI CY7B994V-2BBXIT CY7B993V-5AXC CY7B993V-5AXCT CY7B993V-5AXI CY7B993V-5AXIT CY7B994V-5AXC CY7B994V-5AXCT CY7B994V-5BBXC CY7B994V-5BBXI CY7B994V-5BBXIT CY7B994V-5AXI CY7B994V-5AXIT 100-lead Thin Quad Flat Pack 100-lead Thin Quad Flat Pack - Tape and Reel 100-lead Thin Quad Flat Pack 100-lead Thin Quad Flat Pack - Tape and Reel 100-lead Thin Quad Flat Pack 100-lead Thin Quad Flat Pack - Tape and Reel 100-ball Thin Ball Grid Array 100-lead Thin Quad Flat Pack 100-lead Thin Quad Flat Pack - Tape and Reel 100-ball Thin Ball Grid Array 100-ball Thin Ball Grid Array -Tape and Reel 100-lead Thin Quad Flat Pack 100-lead Thin Quad Flat Pack - Tape and Reel 100-lead Thin Quad Flat Pack 100-lead Thin Quad Flat Pack - Tape and Reel 100-lead Thin Quad Flat Pack 100-lead Thin Quad Flat Pack - Tape and Reel 100-ball Thin Ball Grid Array 100-ball Thin Ball Grid Array 100-ball Thin Ball Grid Array - Tape and Reel 100-lead Thin Quad Flat Pack 100-lead Thin Quad Flat Pack - Tape and Reel Commercial Commercial Industrial Industrial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial 100 100 100 100 200 200 200 200 200 200 200 200 Ordering Code CY7B993V-5AC CY7B993V-5ACT CY7B993V-5AI CY7B993V-5AIT CY7B994V-5AC CY7B994V-5ACT CY7B994V-5BBC CY7B994V-5BBCT CY7B994V-5BBI CY7B994V-5BBIT CY7B994V-5AI CY7B994V-5AIT Package Type 100-lead Thin Quad Flat Pack 100-lead Thin Quad Flat Pack - Tape and Reel 100-lead Thin Quad Flat Pack 100-lead Thin Quad Flat Pack - Tape and Reel 100-lead Thin Quad Flat Pack 100-lead Thin Quad Flat Pack - Tape and Reel 100-ball Thin Ball Grid Array 100-ball Thin Ball Grid Array - Tape and Reel 100-ball Thin Ball Grid Array 100-ball Thin Ball Grid Array -Tape and Reel 100-lead Thin Quad Flat Pack 100-lead Thin Quad Flat Pack - Tape and Reel Operating Range Commercial Commercial Industrial Industrial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial CY7B994V-2BBXCT 100-ball Thin Ball Grid Array - Tape and Reel CY7B994V-5BBXCT 100-ball Thin Ball Grid Array -Tape and Reel Document #: 38-07127 Rev. *F Page 12 of 15 RoboClock CY7B993V CY7B994V Package Diagrams 100-pin Thin Plastic Quad Flat Pack (TQFP) A100 51-85048-*B Document #: 38-07127 Rev. *F Page 13 of 15 RoboClock CY7B993V CY7B994V Package Diagrams (continued) 100-ball Thin Ball Grid Array (11 x 11 x 1.4 mm) BB100 51-85107-*B RoboClock is a registered trademark, and TTB and Total Timing Budget are trademarks, of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07127 Rev. *F Page 14 of 15 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. RoboClock CY7B993V CY7B994V Document History Page Document Title: RoboClock CY7B994V/CY7B993V High-speed Multi-phase PLL Clock Buffer Document Number: 38-07127 REV. ** *A *B *C *D ECN NO. 109957 114376 116570 122794 123694 Issue Date 12/16/01 05/06/02 09/04/02 12/14/02 03/04/03 Orig. of Change SZV CTK HWT RBI RGL Description of Change Changed from Spec number: 38-00747 to 38-07127 Added three industrial packages Added TTB Features Power-up requirements to operating conditions information Added min. Fout value of 12 MHz for CY7B993V and 24 MHz for CY7B994V to switching characteristics table Corrected prop delay limit parameter from (tPDSL,M,H) to tPD in the Lock Detect Output Description paragraph Added clock input frequency (fin) specifications in the switching characteristics table Added Lead-free devices Added typical values for jitter *E *F 128462 391560 07/29/03 See ECN RGL RGL Document #: 38-07127 Rev. *F Page 15 of 15