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CY7B993V/CY7B994V
RoboClock®
High-Speed Multi-Phase PLL Clock Buffer
High-Speed Multi-Phase PLL Clock Buffer
Features
Functional Description
■
500 ps Max Total Timing Budget (TTB™) window
■
12 MHz to 100 MHz (CY7B993V), or 24 MHz to 200 MHz
(CY7B994V) Input/Output Operation
■
Matched Pair Output Skew < 200 ps
■
Zero Input-to-Output Delay
■
18 LVTTL Outputs Driving 50 Terminated Lines
■
16 Outputs at 200 MHz: Commercial Temperature
■
6 Outputs at 200 MHz: Industrial Temperature
■
3.3V LVTTL/LVPECL, Fault-tolerant, and Hot Insertable
Reference Inputs
■
Phase Adjustments in 625 ps/1300 ps Steps Up to ± 10.4 ns
■
Multiply/Divide Ratios of 1–6, 8, 10, 12
■
Individual Output Bank Disable
■
Output High Impedance Option for Testing Purposes
■
Fully Integrated Phase Locked Loop (PLL) with Lock Indicator
■
1100V
Latch up Current .................................................. > ±200 mA
Operating Range
Range
Commercial
Industrial
Ambient Temperature
VCC
0 C to +70 C
3.3 V 10%
–40 C to +85C
3.3 V 10%
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
Min
Max
Unit
LVTTL Compatible Output Pins (QFA[0:1], [1:4]Q[A:B][0:1], LOCK)
VOH
VOL
IOZ
LVTTL HIGH Voltage
LVTTL LOW Voltage
QFA[0:1], [1:4]Q[A:B][0:1]
VCC = Min, IOH = –30 mA
2.4
–
V
LOCK
IOH = –2 mA, VCC = Min
2.4
–
V
QFA[0:1], [1:4]Q[A:B][0:1]
VCC = Min, IOL = 30 mA
–
0.5
V
LOCK
IOL= 2 mA, VCC = Min
–
0.5
V
–100
100
A
2.0
VCC + 0.3
V
2.0
VCC + 0.3
V
–0.3
0.8
V
–0.3
0.8
V
High impedance State Leakage Current
LVTTL Compatible Input Pins (FBKA±, FBKB±, REFA±, REFB±, FBSEL, REFSEL, FBDIS, DIS[1:4])
VIH
LVTTL Input HIGH
FBK[A:B]±, REF[A:B]±
Min < VCC < Max
REFSEL, FBSEL, FBDIS,
DIS[1:4]
VIL
LVTTL Input LOW
FBK[A:B]±, REF[A:B]±
Min < VCC < Max
REFSEL, FBSEL, FBDIS, DIS[1:4]
II
LVTTL VIN >VCC
FBK[A:B]±, REF[A:B]±
VCC = GND, VIN = 3.63 V
–
100
A
IlH
LVTTL Input HIGH
Current
FBK[A:B]±, REF[A:B]±
VCC = Max, VIN = VCC
–
500
A
–
500
A
–500
–
A
–500
–
A
Min < VCC < Max
0.87 × VCC
–
V
Min < VCC < Max
0.47 × VCC 0.53 × VCC
IlL
LVTTL Input LOW
Current
REFSEL, FBSEL, FBDIS, DIS[1:4] VIN = VCC
FBK[A:B]±, REF[A:B]±
VCC = Max, VIN = GND
REFSEL, FBSEL, FBDIS, DIS[1:4]
Three-level Input Pins (FBF0, FBDS[0:1], [1:4]F[0:1], [1:4]DS[0:1], FS, OUTPUT_MODE(TEST))
VIHH
Three-level Input HIGH[6]
Three-level Input
MID[6]
VILL
Three-level Input
LOW[6]
Min < VCC < Max
–
0.13 × VCC
V
IIHH
Three-level Input HIGH Three-level input pins excl. FBF0
Current
FBF0
VIN = VCC
–
200
A
–
400
A
IIMM
Three-level Input MID Three-level input pins excl. FBF0
Current
FBF0
VIN = VCC/2
–50
50
A
–100
100
A
IILL
Three-level Input LOW Three-level input pins excl. FBF0
Current
FBF0
VIN = GND
–200
–
A
–400
–
A
VIMM
V
Notes
5. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power up. Power supply sequencing is NOT required.
6. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold the
unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time before
all data sheet limits are achieved.
Document Number: 38-07127 Rev. *O
Page 11 of 23
CY7B993V/CY7B994V
RoboClock®
Electrical Characteristics (continued)
Over the Operating Range
Parameter
Description
Test Conditions
Min
Max
Unit
400
VCC
mV
LVDIFF Input Pins (FBK[A:B]±, REF[A:B]±)
VDIFF
Input Differential Voltage
VIHHP
Highest Input HIGH Voltage
1.0
VCC
V
VILLP
Lowest Input LOW Voltage
GND
VCC – 0.4
V
VCOM
Common Mode Range (crossing voltage)
0.8
VCC
V
Operating Current
ICCI
ICCN
Internal Operating
Current
CY7B993V
Output Current
Dissipation/Pair[8]
CY7B993V
VCC = Max, fMAX[7]
CY7B994V
CY7B994V
VCC = Max,
CLOAD = 25 pF,
RLOAD = 50 at VCC/2,
fMAX
–
250
mA
–
250
mA
–
40
mA
–
50
mA
Notes
7. ICCI measurement is performed with Bank1 and FB Bank configured to run at maximum frequency (fNOM = 100 MHz for CY7B993V, fNOM = 200 MHz for CY7B994V),
and all other clock output banks to run at half the maximum frequency. FS and OUTPUT_MODE are asserted to the HIGH state.
8. This is dependent upon frequency and number of outputs of a bank being loaded. The value indicates maximum ICCN at maximum frequency and maximum load of
25 pF terminated to 50 at VCC/2.
Document Number: 38-07127 Rev. *O
Page 12 of 23
CY7B993V/CY7B994V
RoboClock®
Capacitance
Parameter
CIN
Description
Test Conditions
TA = 25 C, f = 1 MHz, VCC = 3.3 V
Input capacitance
Min
Max
Unit
–
5
pF
Thermal Resistance
Parameter [9]
Description
θJA
Thermal resistance
(junction to ambient)
θJC
Thermal resistance
(junction to case)
Thin
100-pin TQFP 100-ball
BGA
Test Conditions
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, in accordance with
EIA/JESD51.
Unit
51
42
°C/W
11
16
°C/W
AC Test Loads and Waveforms
Figure 5. AC Test Loads and Waveforms [10]
3.3V
OUTPUT
For all other outputs
R1 = 100
CL
R2 = 100
CL < 25 pF to 185 MHz
or 10 pF at 200 MHz
(Includes fixture and
probe capacitance)
For LOCK output only
R1 = 910
R2 = 910
CL < 30 pF
R1
R2
(a) LVTTL AC Test Load
3.3V
2.0V
0.8V
GND
< 1 ns
2.0V
0.8V
< 1 ns
(b) TTL Input Test Waveform
Notes
9. These parameters are guaranteed by design and are not tested.
10. These figures are for illustrations only. The actual ATE loads may vary.
Document Number: 38-07127 Rev. *O
Page 13 of 23
CY7B993V/CY7B994V
RoboClock®
Switching Characteristics
Over the Operating Range [11, 12, 13, 14, 15]
Parameter
fIN
fOUT
CY7B993/4V-2
Description
Clock Input Frequency
Clock Output Frequency
CY7B993/4V-5
Unit
Min
Typ
Max
Min
Typ
Max
CY7B993V
12
–
100
12
–
100
MHz
CY7B994V
24
–
200
24
–
200
MHz
CY7B993V
12
–
100
12
–
100
MHz
CY7B994V
24
–
200
24
–
200
MHz
[16, 17]
tSKEWPR
Matched-Pair Skew
–
–
200
–
–
200
ps
tSKEWBNK
Intrabank Skew [16, 17]
–
–
200
–
–
250
ps
tSKEW0
Output-Output Skew (same frequency and phase, rise to rise, fall
to fall) [16, 17]
–
–
250
–
–
550
ps
tSKEW1
Output-Output Skew (same frequency and phase, other banks at
different frequency, rise to rise, fall to fall) [16, 17]
–
–
250
–
–
650
ps
tSKEW2
Output-Output Skew (invert to nominal of different banks,
compared banks at same frequency, rising edge to falling edge
aligned, other banks at same frequency) [16, 17]
–
–
250
–
–
700
ps
tSKEW3
Output-Output Skew (all output configurations outside of
tSKEW1and tSKEW2) [16, 17]
–
–
500
–
–
800
ps
tSKEWCPR
Complementary Outputs Skew (crossing to crossing,
complementary outputs of the same bank) [16, 17, 18, 19]
–
–
200
–
–
300
ps
tCCJ1-3
Cycle-to-Cycle Jitter (divide by 1 output frequency,
FB = divide by 1, 2, 3)
–
50
150
–
50
150
ps
Peak
tCCJ4-12
Cycle-to-Cycle Jitter (divide by 1 output frequency,
FB = divide by 4, 5, 6, 8, 10, 12)
–
50
100
–
50
100
ps
Peak
tPD
Propagation Delay, REF to FB Rise
–250
–
250
–500
–
500
ps
Notes
11. This is for non-three level inputs.
12. Assumes 25 pF Max load capacitance up to 185 MHz. At 200 MHz the Max load is 10 pF.
13. Both outputs of pair must be terminated, even if only one is being used.
14. Each package must be properly decoupled.
15. AC parameters are measured at 1.5V unless otherwise indicated.
16. Test Load CL= 25 pF, terminated to VCC/2 with 50up to185 MHz and 10 pF load to 200 MHz.
17. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same phase delay has been selected when all outputs
are loaded with 25 pF and properly terminated up to 185 MHz. At 200 MHz the max load is 10 pF.
18. Complementary output skews are measured at complementary signal pair intersections.
19. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-07127 Rev. *O
Page 14 of 23
CY7B993V/CY7B994V
RoboClock®
Switching Characteristics (continued)
Over the Operating Range [11, 12, 13, 14, 15]
Parameter
Description
CY7B993/4V-2
CY7B993/4V-5
Min
Typ
Max
Min
Typ
Max
Unit
TTB
Total Timing Budget window (same frequency and phase)[19, 20]
–
–
500
–
–
700
ps
tPDDELTA
Propagation Delay difference between two devices[19]
–
–
200
–
–
200
ps
tREFpwh
REF input (Pulse Width HIGH)
[21]
2.0
–
–
2.0
–
–
ns
tREFpwl
REF input (Pulse Width LOW)[21]
2.0
–
–
2.0
–
–
ns
[22]
tr/tf
Output Rise/Fall Time
0.15
–
2.0
0.15
–
2.0
ns
tLOCK
PLL Lock Time from Power up
–
–
10
–
–
10
ms
tRELOCK1
PLL Relock Time (from same frequency, different phase) with
Stable Power Supply
–
–
500
–
–
500
s
tRELOCK2
PLL Relock Time (from different frequency, different phase) with
Stable Power Supply[23]
–
–
1000
–
–
1000
s
tODCV
Output duty cycle deviation from 50%[24]
–1.0
–
1.0
–1.0
–
1.0
ns
tPWH
Output HIGH time deviation from 50%[25]
–
–
1.5
–
–
1.5
ns
tPWL
Output LOW time deviation from
50%[25]
–
–
2.0
–
–
2.0
ns
tPDEV
Period deviation when changing from reference to reference[26]
–
–
0.025
–
–
0.025
UI
tOAZ
DIS[1:4]/FBDIS HIGH to output high impedance
from ACTIVE[27, 28]
1.0
–
10
1.0
–
10
ns
tOAZ
DIS[1:4]/FBDIS LOW to output ACTIVE
from output high impedance [28, 29]
0.5
–
14
0.5
–
14
ns
Notes
20. TTB is the window between the earliest and the latest output clocks with respect to the input reference clock across variations in output frequency, supply voltage,
operating temperature, input clock edge rate, and process. The measurements are taken with the AC test load specified and include output-output skew, cycle-cycle
jitter, and dynamic phase error. TTB is equal to or smaller than the maximum specified value at a given frequency.
21. Tested initially and after any design or process changes that may affect these parameters.
22. Rise and fall times are measured between 2.0V and 0.8V.
23. fNOM must be within the frequency range defined by the same FS state.
24. AC parameters are measured at 1.5V unless otherwise indicated.
25. tPWH is measured at 2.0V. tPWL is measured at 0.8V.
26. UI = Unit Interval. Examples: 1 UI is a full period. 0.1UI is 10% of period.
27. Test Load CL= 25 pF, terminated to VCC/2 with 50up to185 MHz and 10 pF load to 200 MHz.
28. Measured at 0.5V deviation from starting voltage.
29. For tOZA minimum, CL = 0 pF. For tOZA maximum, CL= 25 pF to 185 MHz or 10 pF to 200 MHz.
Document Number: 38-07127 Rev. *O
Page 15 of 23
CY7B993V/CY7B994V
RoboClock®
AC Timing Diagrams
Figure 6. AC Timing Diagrams [30]
tREFpwl
QFA0 or
[1:4]Q[A:B]0
tREFpwh
REF
t SKEWPR
t SKEWPR
t PWH
tPD
t PWL
2.0V
FB
QFA1 or
[1:4]Q[A:B]1
0.8V
tCCJ1-3,4-12
Q
[1:4]QA[0:1]
t SKEWBNK
t SKEWBNK
[1:4]QB[0:1]
REF TO DEVICE 1 and 2
tODCV
tPD
tODCV
Q
FB DEVICE1
tPDELTA
tPDELTA
t SKEW0,1
t SKEW0,1
Other Q
FB DEVICE2
tSKEWCPR
COMPLEMENTARY A
Q
tSKEW2
tSKEW2
COMPLEMENTARY B
crossing
crossing
INVERTED Q
Note
30. AC parameters are measured at 1.5V unless otherwise indicated.
Document Number: 38-07127 Rev. *O
Page 16 of 23
CY7B993V/CY7B994V
RoboClock®
Ordering Information
Propagation Max Speed
Delay (ps)
(MHz)
Ordering Code
Package Type
Operating Range
250
200
CY7B994V-2BBI
100-ball Thin BGA
Industrial, –40 °C to 85 °C
250
200
CY7B994V-2BBIT
100-ball Thin BGA – Tape and Reel
Industrial, –40 °C to 85 °C
500
200
CY7B994V-5BBC
100-ball Thin BGA
Commercial, 0 °C to 70 °C
500
200
CY7B994V-5BBCT
100-ball Thin BGA – Tape and Reel
Commercial, 0 °C to 70 °C
250
100
CY7B993V-2AXC
100-pin TQFP
Commercial, 0 °C to 70 °C
250
100
CY7B993V-2AXCT
100-pin TQFP – Tape and Reel
Commercial, 0 °C to 70 °C
250
100
CY7B993V-2AXI
100-pin TQFP
Industrial, –40 °C to 85 °C
250
200
CY7B994V-2AXC
100-pin TQFP
Commercial, 0 °C to 70 °C
250
200
CY7B994V-2AXCT
100-pin TQFP – Tape and Reel
Commercial, 0 °C to 70 °C
250
200
CY7B994V-2AXI
100-pin TQFP
Industrial, –40 °C to 85 °C
250
200
CY7B994V-2AXIT
100-pin TQFP – Tape and Reel
Industrial, –40 °C to 85 °C
250
200
CY7B994V-2BBXI
100-ball Thin BGA
Industrial, –40 °C to 85 °C
250
200
CY7B994V-2BBXIT
100-ball Thin BGA – Tape and Reel
Industrial, –40 °C to 85 °C
500
100
CY7B993V-5AXC
100-pin TQFP
Commercial, 0 °C to 70 °C
500
100
CY7B993V-5AXCT
100-pin TQFP – Tape and Reel
Commercial, 0 °C to 70 °C
500
100
CY7B993V-5AXI
100-pin TQFP
Industrial, –40 °C to 85 °C
500
100
CY7B993V-5AXIT
100-pin TQFP – Tape and Reel
Industrial, –40 °C to 85 °C
500
200
CY7B994V-5AXC
100-pin TQFP
Commercial, 0 °C to 70 °C
500
200
CY7B994V-5AXCT
100-pin TQFP – Tape and Reel
Commercial, 0 °C to 70 °C
500
200
CY7B994V-5BBXI
100-ball Thin BGA
Industrial, –40 °C to 85 °C
500
200
CY7B994V-5BBXIT
100-ball Thin BGA – Tape and Reel
Industrial, –40 °C to 85 °C
500
200
CY7B994V-5AXI
100-pin TQFP
Industrial, –40 °C to 85 °C
500
200
CY7B994V-5AXIT
100-pin TQFP – Tape and Reel
Industrial, –40 °C to 85 °C
Pb-free
Ordering Code Definitions
CY 7B99XV - X
XX
X
X
X
X = blank or T
blank = Standard; T = Tape and Reel
Temperature Range: X = I or C
I = Industrial = –40 °C to 85 °C; C = Commercial = 0 °C to 70 °C
X = Pb-free indicator (blank = leaded)
Package Type: XX = BB or A
A = 100-pin TQFP; BB = 100-ball BGA
Propagation delay: X = 2 or 5
2 = 250 ps max; 5 = 500 ps max
Base part number
Company ID: CY = Cypress
Document Number: 38-07127 Rev. *O
Page 17 of 23
CY7B993V/CY7B994V
RoboClock®
Package Diagrams
Figure 7. 100-pin TQFP (14 × 14 × 1.4 mm) A100SA Package Outline, 51-85048
51-85048 *J
Document Number: 38-07127 Rev. *O
Page 18 of 23
CY7B993V/CY7B994V
RoboClock®
Package Diagrams (continued)
Figure 8. 100-ball Thin BGA (11 × 11 × 1.4 mm) BB100 Package Outline, 51-85107
51-85107 *E
Document Number: 38-07127 Rev. *O
Page 19 of 23
CY7B993V/CY7B994V
RoboClock®
Acronyms
Acronym
Document Conventions
Description
Units of Measure
BGA
Ball Grid Array
FS
Frequency Select
°C
degree Celsius
I/O
Input/Output
KHz
kilohertz
LVPECL
Low Voltage Positive Emitter Coupled Logic
K
kilohm
LVTTL
Low Voltage Transistor-Transistor Logic
MHz
megahertz
PLL
Phase-Locked Loop
µA
microampere
TQFP
Thin Quad Flat Pack
mA
milliampere
TTL
Transistor-Transistor Logic
ms
millisecond
VCO
Voltage Controlled Oscillator
mV
millivolt
ns
nanosecond
ohm
%
percent
pF
picofarad
ps
picosecond
V
volt
W
watt
Document Number: 38-07127 Rev. *O
Symbol
Unit of Measure
Page 20 of 23
CY7B993V/CY7B994V
RoboClock®
Document History Page
Document Title: CY7B993V/CY7B994V RoboClock®, High-Speed Multi-Phase PLL Clock Buffer
Document Number: 38-07127
Revision
ECN
Orig. of
Change
Submission
Date
**
109957
SZV
12/16/01
Changed from Spec number: 38-00747 to 38-07127
*A
114376
CTK
05/06/02
Updated Ordering Information:
Updated part numbers.
*B
116570
HWT
09/04/02
Updated Switching Characteristics:
Added TTB parameter and its details.
*C
122794
RBI
12/14/02
Updated Absolute Maximum Conditions:
Added Note 5 and referred the same note next to “maximum ratings” in the
description below heading.
*D
123694
RGL
03/04/03
Updated Block Diagram Description:
Updated Lock Detect Output Description:
Replaced “(tPDSL, M, H)” with “(tPD)”.
Updated Switching Characteristics:
Added minimum value of Fout parameter.
*E
128462
RGL
07/29/03
Updated Switching Characteristics:
Added fin parameter and its details.
*F
391560
RGL
See ECN
Updated Features:
Replaced “Low cycle-to-cycle jitter (< 100-ps peak-peak)” with “