CY7B995AI

CY7B995 2.5/3.3V 200-MHz High-Speed Multi-Phase PLL Clock Buffer Features • 2.5V or 3.3V operation • Split output bank power supplies • Output frequency range: 6 MHz to 200 MHz • Output-output skew < 100 ps • Cycle-cycle jitter 100 MHz, Measured at VDD/2 Measured at 2.0V for VDD = 3.3V and at 1.7V for VDD = 2.5V. Measured at 0.8V for VDD = 3.3V and at 0.7V for VDD = 2.5V. Measured at 0.8V-2.0V for VDD = 3.3V and 0.7V–1.7V for VDD = 2.5V Condition Skew between the outputs of any two devices under identical settings and conditions (VDDQ, VDD, temp, air flow, frequency, etc.) Min. – –250 48 45 – – 0.15 – – – Max. 750 +250 52 55 1.5 2.0 1.5 0.5 100 150 Unit ps ps % ns ns ns ms ps ps Notes: 14. tPD is measured at 1.5V for VDD = 3.3V and at 1.25V for VDD = 2.5V with REF rise/fall times of 0.5ns between 0.8V–2.0V. 15. tLOCK is the time that is required before outputs synchronize to REF. This specification is valid with stable power supplies which are within normal operating limits. 16. Lock detector circuit may be unreliable for input frequencies lower than 4MHz, or for input signals which contain significant jitter. Document #: 38-07337 Rev. *A Page 7 of 11 CY7B995 AC Timing Definitions tREF tPWH tPWL REF tPD t0DCV t0DCV FB tCCJ1-12 Q tSKEWPR tSKEW0,1 tSKEWPR tSKEW0,1 OTHER Q tSKEW1 tSKEW1 INVERTED Q tSKEW3 tSKEW3 tSKEW3 REF DIVIDED BY 2 tSKEW1,3,4 tSKEW1,3,4 REF DIVIDED BY 4 Document #: 38-07337 Rev. *A Page 8 of 11 CY7B995 AC TEST LOADS AND WAVEFORMS VDDQ Output 20pF Output 150Ω 150Ω 20pF For Lock Output Figure 1. tORISE tOFALL For All Other Outputs tORISE tOFALL 2.0V VTH =1.5V 0.8V tPWL tPWH 1.7V VTH =1.25V 0.7V tPWH tPWL 3.3V LVTTL OUTPUT WAVEFORM 2.5V LVTTL OUTPUT WAVEFORM Figure 2. ≤ 1ns 3.0V 2.0V VTH =1.5V 0.8V 0V ≤ 1ns 2.5V 1.7V VTH =1.25V 0.7V 0V ≤ 1ns ≤ 1ns 3.3V LVTTL INPUT TEST WAVEFORM Figure 3. 2.5V LVTTL INPUT TEST WAVEFORM Ordering Information Part Number CY7B995AC CY7B995ACT CY7B995AI CY7B995AIT 44 TQFP 44 TQFP – Tape and Reel 44 TQFP 44 TQFP – Tape and Reel Package Type Product Flow Commercial, 0° to 70°C Commercial, 0° to 70°C Industrial, –40° to 85°C Industrial, –40° to 85°C Document #: 38-07337 Rev. *A Page 9 of 11 CY7B995 Package Drawing and Dimension 44-lead Thin Plastic Quad Flat Pack (10 x 10 x 1.0 mm) A44SB 51-85155*A RoboClock is a registered trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07337 Rev. *A Page 10 of 11 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7B995 Document History Page Document Title:CY7B995 Roboclock® 2.5/3.3V 200-MHz High-speed Multi-phase PLL Clock Buffer Document Number: 38-07337 REV. ** *A ECN No. 122626 205743 Issue Date 01/10/03 See ECN Orig. of Change RGL RGL New Data Sheet Changed Pin 5 from VDD to VDDQ4, Pin 16 from VDD to VDDQ3 and Pin 29 from VDD to VDDQ1 Added pin 1 indicator in the Pin Configuration Drawing Description of Change Document #: 38-07337 Rev. *A Page 11 of 11