CY7C007A16K × 8 Dual-Port Static RAM
CY7C006A
16K × 8 Dual-Port Static RAM
16K × 8 Dual-Port Static RAM
Features
■
On-chip arbitration logic
■
True dual-ported memory cells which allow simultaneous
access of the same memory location
■
Semaphores included to permit software handshaking
between ports
■
16K × 8 organization (CY7C006A)
■
INT flags for port-to-port communication
■
0.35-micron CMOS for optimum speed/power
■
Pin select for Master or Slave
■
High-speed access: 20 ns
■
Commercial temperature range
■
Low operating power
❐ Active: ICC = 180 mA (typical)
❐ Standby: ISB3 = 0.05 mA (typical)
■
Available in 68-pin PLCC (CY7C006A), 64-pin TQFP
(CY7C006A)
■
Pb-free packages available
■
Fully asynchronous operation
Functional Description
■
Automatic power-down
■
Expandable data bus to 16 bits or more using Master/Slave
chip select when using more than one device
For a complete list of related documentation, click here.
Logic Block Diagram
R/WL
R/WR
CEL
CER
OEL
OER
8
8
I/O0L–I/O7L
I/O0R–I/O7R
I/O
Control
14
A0L–A13L
Address
Decode
I/O
Control
Address
Decode
True Dual-Ported
RAM Array
14
A0R–A13R
14
A0L–A13L
CEL
OEL
R/WL
SEML
BUSYL
INTL
14
A0R–A13R
CER
OER
R/WR
SEMR
Interrupt
Semaphore
Arbitration
[1]
[1]
BUSYR
INTR
M/S
Note
1. BUSY is an output in master mode and an input in slave mode.
Cypress Semiconductor Corporation
Document Number: 38-06045 Rev. *K
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 5, 2018
CY7C006A
Contents
Pin Configurations ........................................................... 3
Selection Guide ................................................................ 4
Pin Definitions .................................................................. 4
Architecture ...................................................................... 4
Functional Overview ........................................................ 4
Write Operation ........................................................... 4
Read Operation ........................................................... 5
Interrupts ..................................................................... 5
Busy ............................................................................ 5
Master/Slave ............................................................... 5
Semaphore Operation ................................................. 5
Maximum Ratings ............................................................. 6
Operating Range ............................................................... 6
Electrical Characteristics ................................................. 6
Capacitance ...................................................................... 7
AC Test Loads and Waveforms ....................................... 7
Data Retention Mode ........................................................ 7
Timing ................................................................................ 7
Switching Characteristics ................................................ 8
Switching Waveforms .................................................... 10
Document Number: 38-06045 Rev. *K
Non-Contending Read/Write .......................................... 16
Interrupt Operation Example ......................................... 16
Semaphore Operation Example .................................... 16
Ordering Information ...................................................... 17
16K × 8 Asynchronous Dual-Port SRAM .................. 17
Ordering Code Definitions ......................................... 17
Package Diagrams .......................................................... 18
Acronyms ........................................................................ 20
Document Conventions ................................................. 20
Units of Measure ....................................................... 20
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support ....................... 22
Products .................................................................... 22
PSoC® Solutions ...................................................... 22
Cypress Developer Community ................................. 22
Technical Support ..................................................... 22
Page 2 of 22
CY7C006A
Pin Configurations
I/O2L
I/O3L
I/O4L
10
I/O5L
GND
I/O6L
I/O7L
13
VCC
A11L
A10L
A9L
A8L
A7L
A6L
64
63
62
61
65
A12L
VCC
68
67
66
CEL
NC
A13L
SEML
4
2
1
R/WL
5
3
I/O0L
NC
OEL
7
6
I/O1L
8
9
Figure 1. 68-pin PLCC pinout
Top View
60
59
11
58
12
57
56
55
14
15
CY7C006A (16K × 8)
16
17
53
BUSYL
GND
M/S
52
19
51
50
I/O2R
VCC
21
22
23
24
49
48
47
42
43
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
A6R
A5R
41
40
A8R
A7R
A9R
38
39
37
36
A11R
A10R
35
33
34
NC
A12R
32
GND
31
CER
A13R
30
NC
SEMR
44
29
26
OER
R/WR
46
45
27
28
25
I/O7R
A0L
INTL
18
I/O3R
I/O4R
I/O5R
I/O6R
A3L
A2L
A1L
54
GND
I/O0R
I/O1R
20
A5L
A4L
A6L
A5L
49
54
A7L
A12L
56
55
51
50
VCC
57
A8L
CEL
A13L
59
52
SEML
A9L
R/WL
60
53
OEL
62
61
A11L
A10L
I/O0L
63
58
I/O1L
64
Figure 2. 64-pin TQFP pinout
Top View
I/O2L
1
48
A4L
I/O3L
I/O4L
2
47
3
4
46
45
A3L
A2L
5
44
A0L
I/O6L
I/O7L
6
43
7
42
INTL
BUSYL
GND
M/S
I/O5L
GND
CY7C006A (16K × 8)
A1L
A2R
I/O5R
16
33
A4R
Document Number: 38-06045 Rev. *K
30
31
A7R
32
29
A8R
BUSYR
A3R
A6R
A5R
28
41
A9R
A11R
A10R
R/WR
27
35
34
25
26
14
15
A12R
I/O3R
I/O4R
24
A0R
A1R
GND
36
23
13
22
VCC
CER
A13R
37
21
12
SEMR
INTR
I/O2R
19
20
38
OER
11
18
40
39
17
9
10
I/O6R
8
I/O7R
VCC
GND
I/O0R
I/O1R
Page 3 of 22
CY7C006A
Selection Guide
CY7C006A
-20
Unit
Maximum Access Time
20
ns
Typical Operating Current
180
mA
Typical Standby Current for ISB1 (Both Ports TTL Level)
45
mA
0.05
mA
Description
Typical Standby Current for ISB3 (Both Ports CMOS Level)
Pin Definitions
Left Port
Right Port
Description
CEL
CER
Chip Enable
R/WL
R/WR
Read/Write Enable
OEL
OER
Output Enable
A0L–A13L
A0R–A13R
Address
I/O0L–I/O7L
I/O0R–I/O7R
Data Bus Input/Output
SEML
SEMR
Semaphore Enable
INTL
INTR
Interrupt Flag
BUSYL
BUSYR
Busy Flag
M/S
Master or Slave Select
VCC
Power
GND
Ground
NC
No Connect
Architecture
The CY7C006A consists of an array 16K words of 8 bits of
dual-port RAM cells, I/O and address lines, and control signals
(CE, OE, R/W). These control pins permit independent access
for reads or writes to any location in memory. To handle
simultaneous writes/reads to the same location, a BUSY pin is
provided on each port. Two Interrupt (INT) pins can be utilized
for port-to-port communication. Two Semaphore (SEM) control
pins are used for allocating shared resources. With the M/S pin,
the devices can function as a master (BUSY pins are outputs) or
as a slave (BUSY pins are inputs). The devices also have an
automatic power-down feature controlled by CE. Each port is
provided with its own Output Enable control (OE), which allows
data to be read from the device.
Functional Overview
The CY7C006A is low-power CMOS 16K × 8 dual-port static
RAMs. Various arbitration schemes are included on the devices
to handle situations when multiple processors access the same
piece of data. Two ports are provided, permitting independent,
asynchronous access for reads and writes to any location in
memory. The devices can be utilized as standalone 8-bit
dual-port static RAMs or multiple devices can be combined in
order to function as a 16-bit or wider master/slave dual-port static
RAM. An M/S pin is provided for implementing 16-bit or wider
Document Number: 38-06045 Rev. *K
memory applications without the need for separate master and
slave devices or additional discrete logic. Application areas
include interprocessor/multiprocessor designs, communications
status buffering, and dual-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE), Read
or Write Enable (R/W), and Output Enable (OE). Two flags are
provided on each port (BUSY and INT). BUSY signals that the
port is trying to access the same location currently being
accessed by the other port. The Interrupt flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from one
port to the other to indicate that a shared resource is in use. The
semaphore logic is comprised of eight shared latches. Only one
side can control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power-down feature is controlled independently on
each port by a Chip Select (CE) pin.
The CY7C006A is available in 68-pin PLCC package, the
CY7C006A is also available in 64-pin TQFP package.
Write Operation
Data must be set up for a duration of tSD before the rising edge
of R/W in order to guarantee a valid write. A write operation is
controlled by either the R/W pin (see Write Cycle No. 1
waveform) or the CE pin (see Write Cycle No. 2 waveform).
Required inputs for non-contention operations are summarized
Page 4 of 22
CY7C006A
in Non-Contending Read/Write on page 16.
If a location is being written to by one port and the opposite port
attempts to read that location, a port-to-port flowthrough delay
must occur before the data is read on the output; otherwise the
data read is not deterministic. Data will be valid on the port tDDD
after the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE and
CE pins. Data will be available tACE after CE or tDOE after OE is
asserted. If the user wishes to access a semaphore flag, then the
SEM pin must be asserted instead of the CE pin, and OE must
also be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (3FFF) is the mailbox for
the right port and the second-highest memory location (3FFE) is
the mailbox for the left port. When one port writes to the other
port’s mailbox, an interrupt is generated to the owner. The
interrupt is reset when the owner reads the contents of the
mailbox. The message is user defined.
Each port can read the other port’s mailbox without resetting the
interrupt. The active state of the busy signal (to a port) prevents
the port from setting the interrupt to the winning port. Also, an
active busy to a port prevents that port from reading its own
mailbox and, thus, resetting the interrupt to it.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin. The operation of the interrupts and their interaction with
Busy are summarized in Interrupt Operation Example on page 16.
Busy
The CY7C006A provides on-chip arbitration to resolve
simultaneous memory location access (contention). If both ports’
CEs are asserted and an address match occurs within tPS of
each other, the busy logic will determine which port has access.
If tPS is violated, one port will definitely gain permission to the
location, but it is not predictable which port will get that
permission. BUSY will be asserted tBLA after an address match
or tBLC after CE is taken LOW.
Master/Slave
A M/S pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to the BUSY input of the slave.
This will allow the device to interface to a master device with no
external components. Writing to slave devices must be delayed
until after the BUSY input has settled (tBLC or tBLA), otherwise,
Document Number: 38-06045 Rev. *K
the slave chip may begin a write cycle during a contention
situation. When tied HIGH, the M/S pin allows the device to be
used as a master and, therefore, the BUSY line is an output.
BUSY can then be used to send the arbitration outcome to a
slave.
Semaphore Operation
The CY7C006A provides eight semaphore latches, which are
separate from the dual-port memory locations. Semaphores are
used to reserve resources that are shared between the two ports.
The state of the semaphore indicates that a resource is in use.
For example, if the left port wants to request a given resource, it
sets a latch by writing a zero to a semaphore location. The left
port then verifies its success in setting the latch by reading it.
After writing to the semaphore, SEM or OE must be deasserted
for tSOP before attempting to read the semaphore. The
semaphore value will be available tSWRD + tDOE after the rising
edge of the semaphore write. If the left port was successful
(reads a zero), it assumes control of the shared resource,
otherwise (reads a one) it assumes the right port has control and
continues to poll the semaphore. When the right side has
relinquished control of the semaphore (by writing a one), the left
side will succeed in gaining control of the semaphore. If the left
side no longer requires the semaphore, a one is written to cancel
its request.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A0–2 represents the
semaphore address. OE and R/W are used in the same manner
as a normal memory access. When writing or reading a
semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O0 is used. If a zero is
written to the left port of an available semaphore, a one will
appear at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes control
by writing a one to the semaphore, the semaphore will be set to
one for both sides. However, if the right port had requested the
semaphore (written a zero) while the left port had control, the
right port would immediately own the semaphore as soon as the
left port released it. Semaphore Operation Example on page 16
shows sample semaphore operations.
When reading a semaphore, all data lines output the semaphore
value. The read value is latched in an output register to prevent
the semaphore from changing state during a write from the other
port. If both ports attempt to access the semaphore within tSPS
of each other, the semaphore will definitely be obtained by one
side or the other, but there is no guarantee which side will control
the semaphore.
Page 5 of 22
CY7C006A
DC Input Voltage [3] .....................................–0.5 V to +7.0 V
Maximum Ratings
Exceeding maximum ratings [2] may shorten the useful life of the
device. User guidelines are not tested.
Output Current into Outputs (LOW) ............................ 20 mA
Static Discharge Voltage .......................................... > 2001V
Storage Temperature ............................... –65 °C to +150 °C
Latch-Up Current ................................................... > 200 mA
Ambient Temperature
with Power Applied .................................. –55 °C to +125 °C
Operating Range
Supply Voltage to Ground Potential .............–0.3 V to +7.0 V
DC Voltage Applied to Outputs
in High Z State .............................................–0.5 V to +7.0 V
Range
Commercial
Ambient Temperature
VCC
0 °C to +70 °C
5 V 10%
Electrical Characteristics
Over the Operating Range
CY7C006A
Parameter
Description
-20
Unit
Min
Typ
Max
–
–
V
0.4
V
VOH
Output HIGH Voltage (VCC = Min, IOH = –4.0 mA)
2.4
VOL
Output LOW Voltage (VCC = Min, IOH = +4.0 mA)
–
VIH
Input HIGH Voltage
2.2
–
V
VIL
Input LOW Voltage
–
0.8
V
IOZ
Output Leakage Current
–10
10
A
ICC
Operating Current (VCC = Max, IOUT = 0 mA),
Outputs Disabled
Commercial
275
mA
ISB1
Standby Current (Both Ports TTL Level),
CEL & CER VIH, f = fMAX
Commercial
ISB2
Standby Current (One Port TTL Level),
CEL | CER VIH, f = fMAX
Commercial
ISB3
Standby Current (Both Ports CMOS Level),
CEL & CER VCC 0.2 V, f = 0
Commercial
Standby Current (One Port CMOS Level),
CEL | CER VIH, f = fMAX[3, 4]
Commercial
ISB4
–
180
Industrial
–
45
Industrial
–
110
Industrial
–
–
mA
mA
140
–
mA
mA
0.5
100
mA
mA
160
0.05
Industrial
Industrial
mA
65
mA
mA
Notes
2. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
3. Pulse width < 20 ns.
4. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby
ISB3.
Document Number: 38-06045 Rev. *K
Page 6 of 22
CY7C006A
Capacitance
Parameter [5]
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = 5.0 V
Max
Unit
10
pF
10
pF
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
5V
5V
R1 = 893
OUTPUT
C = 30 pF
R2 = 347
OUTPUT
RTH = 250
R1 = 893
OUTPUT
C = 30 pF
C = 5 pF
R2 = 347
VTH = 1.4 V
(a) Normal Load (Load 1)
(c) Three-State Delay (Load 2)
(Used for tLZ, tHZ, tHZWE, & tLZWE
including scope and jig)
(b) Thévenin Equivalent (Load 1)
Data Retention Mode
The CY7C006A is designed with battery backup in mind. Data
retention voltage and supply current are guaranteed over
temperature. The following rules ensure data retention:
1. Chip Enable (CE) must be held HIGH during data retention,
within VCC to VCC – 0.2 V.
2. CE must be kept between VCC – 0.2 V and 70% of VCC during
the power-up and power-down transitions.
3. The RAM can begin operation >tRC after VCC reaches the
minimum operating voltage (4.5 V).
Timing
Data Retention Mode
VCC
CE
Parameter
ICCDR1
4.5V
VCC 2.0V
4.5V
tRC
VCC to VCC – 0.2V
Test Conditions [6]
@ VCCDR = 2 V
V
IH
Max
Unit
1.5
mA
Notes
5. Tested initially and after any design or process changes that may affect these parameters.
6. CE = VCC, Vin = GND to VCC, TA = 25°C. This parameter is guaranteed but not tested.
Document Number: 38-06045 Rev. *K
Page 7 of 22
CY7C006A
Switching Characteristics
Over the Operating Range
CY7C006A
Parameter
[7]
Description
-20
Unit
Min
Max
READ CYCLE
tRC
Read Cycle Time
20
–
ns
tAA
Address to Data Valid
–
20
ns
tOHA
Output Hold From Address Change
3
–
ns
tACE[8]
CE LOW to Data Valid
–
20
ns
tDOE
OE LOW to Data Valid
–
12
ns
OE LOW to Low Z
3
–
ns
OE HIGH to High Z
–
12
ns
CE LOW to Low Z
3
–
ns
CE HIGH to High Z
–
12
ns
CE LOW to Power-Up
0
–
ns
CE HIGH to Power-Down
–
20
ns
tLZOE
[9, 10, 11]
tHZOE[9, 10, 11]
tLZCE[9, 10, 11]
tHZCE[9, 10, 11]
tPU[11]
tPD[11]
WRITE CYCLE
tWC
Write Cycle Time
20
–
ns
tSCE[8]
CE LOW to Write End
15
–
ns
tAW
Address Valid to Write End
15
–
ns
tHA
Address Hold From Write End
0
–
ns
tSA[8]
Address Set-Up to Write Start
0
–
ns
tPWE
Write Pulse Width
15
–
ns
tSD
Data Set-Up to Write End
15
–
ns
tHD[12]
Data Hold From Write End
0
–
ns
tHZWE[10, 11]
tLZWE[10, 11]
tWDD[13]
tDDD[13]
R/W LOW to High Z
–
12
ns
R/W HIGH to Low Z
3
–
ns
Write Pulse to Data Delay
–
45
ns
Write Data Valid to Read Data Valid
–
30
ns
Notes
7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOI/IOH
and 30-pF load capacitance.
8. To access RAM, CE = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time.
9. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
10. Test conditions used are Load 3.
11. This parameter is guaranteed but not tested.
12. For 15 ns industrial parts tHD Min. is 0.5 ns.
13. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
Document Number: 38-06045 Rev. *K
Page 8 of 22
CY7C006A
Switching Characteristics (continued)
Over the Operating Range
CY7C006A
Parameter
[7]
Description
-20
Unit
Min
Max
BUSY TIMING [14]
tBLA
BUSY LOW from Address Match
–
20
ns
tBHA
BUSY HIGH from Address Mismatch
–
20
ns
tBLC
BUSY LOW from CE LOW
–
20
ns
tBHC
BUSY HIGH from CE HIGH
–
17
ns
tPS
Port Set-Up for Priority
5
–
ns
tWB
R/W HIGH after BUSY (Slave)
0
–
ns
tWH
R/W HIGH after BUSY HIGH (Slave)
15
–
ns
tBDD[15]
BUSY HIGH to Data Valid
–
20
ns
INTERRUPT TIMING
[14]
tINS
INT Set Time
–
20
ns
tINR
INT Reset Time
–
20
ns
SEMAPHORE TIMING
tSOP
SEM Flag Update Pulse (OE or SEM)
10
–
ns
tSWRD
SEM Flag Write to Read Time
5
–
ns
tSPS
SEM Flag Contention Window
5
–
ns
tSAA
SEM Address Access Time
–
20
ns
Notes
14. Test conditions used are Load 2.
15. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).
Document Number: 38-06045 Rev. *K
Page 9 of 22
CY7C006A
Switching Waveforms
Figure 4. Read Cycle No. 1 (Either Port Address Access) [16, 17, 18]
tRC
ADDRESS
tOHA
DATA OUT
tAA
tOHA
PREVIOUS DATA VALID
DATA VALID
Figure 5. Read Cycle No. 2 (Either Port CE/OE Access) [16, 19, 20]
tACE
CE
tHZCE
tDOE
OE
tHZOE
tLZOE
DATA VALID
DATA OUT
tLZCE
tPU
tPD
ICC
CURRENT
ISB
Figure 6. Read Cycle No. 3 (Either Port) [16, 18, 19, 20]
tRC
ADDRESS
tOHA
tAA
tLZCE
tABE
CE
tHZCE
tACE
tLZCE
DATA OUT
Notes
16. R/W is HIGH for read cycles.
17. Device is continuously selected CE = VIL. This waveform cannot be used for semaphore reads.
18. OE = VIL.
19. Address valid prior to or coincident with CE transition LOW.
20. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.
Document Number: 38-06045 Rev. *K
Page 10 of 22
CY7C006A
Switching Waveforms (continued)
Figure 7. Write Cycle No. 1 (R/W Controlled Timing) [21, 22, 23, 24]
tWC
ADDRESS
tHZOE [26]
OE
CE
tAW
[25]
tPWE[24]
tSA
tHA
R/W
tHZWE[26]
DATA OUT
tLZWE
NOTE 27
NOTE 27
tSD
tHD
DATA IN
Figure 8. Write Cycle No. 2 (CE Controlled Timing) [21, 22, 23, 28]
tWC
ADDRESS
tAW
CE
[25]
tSA
tSCE
tHA
R/W
tSD
tHD
DATA IN
Notes
21. R/W or CE must be HIGH during all address transitions.
22. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM.
23. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
24. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified tPWE.
25. To access RAM, CE = VIL, SEM = VIH.
26. Transition is measured ±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
27. During this period, the I/O pins are in the output state, and input signals must not be applied.
28. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
Document Number: 38-06045 Rev. *K
Page 11 of 22
CY7C006A
Switching Waveforms (continued)
Figure 9. Semaphore Read After Write Timing, Either Side [29]
tAA
A 0–A 2
VALID ADRESS
VALID ADRESS
tAW
tACE
tHA
SEM
tOHA
tSCE
tSOP
tSD
I/O0
DATAIN VALID
tSA
tPWE
DATAOUT VALID
tHD
R/W
tSWRD
tDOE
tSOP
OE
WRITE CYCLE
READ CYCLE
Figure 10. Timing Diagram of Semaphore Contention [30, 31, 32]
A0L –A2L
MATCH
R/WL
SEM L
tSPS
A 0R –A 2R
MATCH
R/WR
SEM R
Notes
29. CE = HIGH for the duration of the above timing (both write and read cycle).
30. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH.
31. Semaphores are reset (available to both ports) at cycle start.
32. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.
Document Number: 38-06045 Rev. *K
Page 12 of 22
CY7C006A
Switching Waveforms (continued)
Figure 11. Timing Diagram of Read with BUSY (M/S = HIGH) [33]
tWC
ADDRESSR
MATCH
tPWE
R/WR
tSD
DATA INR
tHD
VALID
tPS
ADDRESSL
MATCH
tBLA
tBHA
BUSYL
tBDD
tDDD
DATA OUTL
VALID
tWDD
Figure 12. Write Timing with Busy Input (M/S = LOW)
tPWE
R/W
BUSY
tWB
tWH
Note
33. CEL = CER = LOW.
Document Number: 38-06045 Rev. *K
Page 13 of 22
CY7C006A
Switching Waveforms (continued)
Figure 13. Busy Timing Diagram No. 1 (CE Arbitration) [34]
CELValid First:
ADDRESS L,R
ADDRESS MATCH
CEL
tPS
CER
tBLC
tBHC
BUSYR
CER Valid First:
ADDRESS L,R
ADDRESS MATCH
CER
tPS
CE L
tBLC
tBHC
BUSY L
Figure 14. Busy Timing Diagram No. 2 (Address Arbitration) [34]
Left Address Valid First:
tRC or tWC
ADDRESS L
ADDRESS MATCH
ADDRESS MISMATCH
tPS
ADDRESSR
tBLA
tBHA
BUSY R
Right Address Valid First:
tRC or tWC
ADDRESSR
ADDRESS MATCH
ADDRESS MISMATCH
tPS
ADDRESSL
tBLA
tBHA
BUSY L
Note
34. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
Document Number: 38-06045 Rev. *K
Page 14 of 22
CY7C006A
Switching Waveforms (continued)
Figure 15. Interrupt Timing Diagrams
Left Side Sets INTR:
tWC
ADDRESSL
WRITE 3FFF
tHA[35]
CE L
R/W L
INT R
tINS [36]
Right Side Clears INTR:
tRC
READ 3FFF
ADDRESSR
CE R
tINR [36]
R/WR
OE R
INTR
Right Side Sets INTL:
tWC
ADDRESSR
WRITE 3FFE
tHA[35]
CE R
R/W R
INT L
tINS[36]
Left Side Clears INTL:
tRC
READ 3FFE
ADDRESSR
CE L
tINR[36]
R/W L
OE L
INT L
Notes
35. tHA depends on which enable pin (CEL or R/WL) is deasserted first.
36. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
Document Number: 38-06045 Rev. *K
Page 15 of 22
CY7C006A
Non-Contending Read/Write
Inputs
Outputs
CE
R/W
OE
SEM
H
X
X
H
High Z
Deselected: Power-Down
H
H
L
L
Data Out
Read Data in Semaphore Flag
X
X
H
X
High Z
I/O Lines Disabled
X
L
Data In
Write into Semaphore Flag
H
I/O0–I/O8
Operation
L
H
L
H
Data Out
Read
L
L
X
H
Data In
Write
L
X
X
L
Not Allowed
Interrupt Operation Example
(Assumes BUSYL = BUSYR = HIGH)
Left Port
Function
Right Port
R/WL
CEL
OEL
A0L–14L
INTL
R/WR
CER
OER
A0R–14R
INTR
Set Right INTR Flag
L
L
X
3FFF
X
X
X
X
X
L[37]
Reset Right INTR Flag
X
X
X
X
X
X
L
L
3FFF
H[38]
Set Left INTL Flag
X
X
X
X
L[38]
L
L
X
3FFE
X
3FFE
H[37]
X
X
X
X
X
Reset Left INTL Flag
X
L
L
Semaphore Operation Example
I/O0–I/O8 Left
I/O0–I/O8Right
No action
Function
1
1
Semaphore free
Status
Left port writes 0 to semaphore
0
1
Left Port has semaphore token
Right port writes 0 to semaphore
0
1
No change. Right side has no write access to semaphore
Left port writes 1 to semaphore
1
0
Right port obtains semaphore token
Left port writes 0 to semaphore
1
0
No change. Left port has no write access to semaphore
Right port writes 1 to semaphore
0
1
Left port obtains semaphore token
Left port writes 1 to semaphore
1
1
Semaphore free
Right port writes 0 to semaphore
1
0
Right port has semaphore token
Right port writes 1 to semaphore
1
1
Semaphore free
Left port writes 0 to semaphore
0
1
Left port has semaphore token
Left port writes 1 to semaphore
1
1
Semaphore free
Notes
37. If BUSYL = L, then no change.
38. If BUSYR = L, then no change.
Document Number: 38-06045 Rev. *K
Page 16 of 22
CY7C006A
Ordering Information
16K × 8 Asynchronous Dual-Port SRAM
Speed
(ns)
20
Package
Name
Ordering Code
Package Type
Operating
Range
CY7C006A-20AXC
A65
64-pin TQFP (Pb-free)
Commercial
CY7C006A-20AXI
A65
64-pin TQFP (Pb-free)
Industrial
CY7C006A-20JXC
J81
68-pin PLCC (Pb-free)
Commercial
Ordering Code Definitions
CY 7
C
0 06A - 20
X X
X
Temperature Range: X = C or I
C = Commercial; I = Industrial
X = Pb-free (RoHS Compliant)
Package Type: X = A or J
A = 64-pin TQFP
J = 68-pin PLCC
Speed Grade: 20 ns
Depth: 06A = 16K
Width: 0 = × 8
Technology Code: C = CMOS
Marketing Code: 7 = Dual Port SRAM
Company ID: CY = Cypress
Document Number: 38-06045 Rev. *K
Page 17 of 22
CY7C006A
Package Diagrams
Figure 16. 64-pin TQFP (14 × 14 × 1.4 mm) A64SA Package Outline, 51-85046
ș1
ș
ș2
SYMBOL
DIMENSIONS
MIN. NOM. MAX.
A
1.60
A1
0.05
A2
1.35 1.40 1.45
0.15
D
15.75 16.00 16.25
D1
13.95 14.00 14.05
E
15.75 16.00 16.25
E1
13.95 14.00 14.05
R1
0.08
0.20
R2
0.08
0.20
ș
0°
7°
ș1
0°
ș2
11°
13°
12°
b
0.30 0.35 0.40
L
0.45 0.60 0.75
L2
L3
e
1. JEDEC STD REF MS-026
2. BODY LENGTH DIMENSION DOES NOT
INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL
NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC
BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0.20
c
L1
NOTE:
1.00 REF
0.25 BSC
0.20
0.80 TYP
51-85046 *H
Document Number: 38-06045 Rev. *K
Page 18 of 22
CY7C006A
Package Diagrams (continued)
Figure 17. 68-pin PLCC (0.958 × 0.958 Inches) Package Outline, 51-85005
51-85005 *D
Document Number: 38-06045 Rev. *K
Page 19 of 22
CY7C006A
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CE
Chip Enable
CMOS
Complementary Metal Oxide Semiconductor
°C
degree Celsius
I/O
Input/Output
µA
microampere
INT
Interrupt
mA
milliampere
OE
Output Enable
ns
nanosecond
PLCC
Plastic Leaded Chip Carrier
ohm
R/W
Read/Write
%
percent
SRAM
Static Random Access Memory
pF
picofarad
TQFP
Thin Quad Flat Pack
V
volt
TTL
Transistor-Transistor Logic
W
watt
Document Number: 38-06045 Rev. *K
Symbol
Unit of Measure
Page 20 of 22
CY7C006A
Document History Page
Document Title: CY7C006A, 16K × 8 Dual-Port Static RAM
Document Number: 38-06045
Rev.
ECN No.
Orig. of
Change
Issue Date
**
110197
SZV
09/29/2001
Changed from Spec number: 38-00831 to 38-06045.
*A
122295
RBI
12/27/2002
Updated Maximum Ratings:
Added Note 2 and referred the same note in “maximum ratings” in description
below the heading.
*B
237620
YDT
06/25/2004
Updated Features:
Removed “Pin-compatible and functionally equivalent to IDT7006 and
IDT7007”.
*C
345376
AEQ
04/19/2005
Removed Industrial Temperature Range related information across the
document.
Updated Ordering Information:
Updated part numbers.
*D
387333
PCX
08/11/2005
Included Pb-Free Logo at the top of the document.
Added Industrial Temperature Range related information across the
document.
Updated Ordering Information:
Updated part numbers.
*E
2896210
RAME
03/22/2010
Updated Ordering Information:
Updated part numbers.
Updated Package Diagrams:
spec 51-85046 – Changed revision from *B to *D.
spec 51-85065 – Changed revision from *B to *C.
spec 51-85005 – Changed revision from *A to *B.
*F
3110296
EYB
12/14/2010
Updated Ordering Information:
Updated part numbers.
Added Ordering Code Definitions.
Minor edits.
Updated to new template.
*G
3889996
SMCH
01/30/2013
Removed CY7C007A, CY7C016A, CY7C017A related information across the
document.
Updated Package Diagrams:
spec 51-85046 – Changed revision from *D to *E.
Removed spec 51-85065 *C (corresponding to 80-pin TQFP package).
spec 51-85005 – Changed revision from *B to *C.
Added Acronyms and Units of Measure.
*H
4227411
SMCH
12/20/2013
Updated Ordering Information (Updated part numbers).
Updated to new template.
Completing Sunset Review.
*I
4580622
SMCH
11/26/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Package Diagrams:
spec 51-85046 – Changed revision from *E to *F.
*J
5553780
NILE
12/14/2016
Updated Package Diagrams:
spec 51-85046 – Changed revision from *F to *G.
spec 51-85005 – Changed revision from *C to *D.
Updated to new template.
Completing Sunset Review.
*K
6015072
NILE
01/05/2018
Updated Package Diagrams:
spec 51-85046 – Changed revision from *G to *H.
Updated to new template.
Document Number: 38-06045 Rev. *K
Description of Change
Page 21 of 22
CY7C006A
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Arm® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
Internet of Things
Memory
cypress.com/clocks
cypress.com/interface
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
Cypress Developer Community
Community | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2001-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 38-06045 Rev. *K
Revised January 5, 2018
Page 22 of 22
