CY7C024E
CY7C025E
CY7C0251E
4K × 16 and 8K × 16/18
Dual-Port Static RAM with SEM, INT, BUSY
4K × 16 and 8K × 16/18 Dual-Port Static RAM with SEM, INT, BUSY
Features
Functional Description
■
True dual-ported memory cells that allow simultaneous reads
of the same memory location
■
4K × 16 organization (CY7C024E)
■
8K × 16 organization (CY7C025E)
■
8K × 18 organization (CY7C0251E)
■
0.35-µ complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■
High-speed access: 15 ns
■
Low operating power: ICC = 180 mA (typ), ISB3 = 0.05 mA (typ)
■
Fully asynchronous operation
■
Automatic power-down
The CY7C024E and CY7C025E/CY7C0251E are low-power
CMOS 4K × 16 and 8K × 16/18 dual-port static RAMs. Various
arbitration schemes are included on the CY7C024E and
CY7C025E/CY7C0251E to handle situations when multiple
processors access the same piece of data. Two ports are
provided, permitting independent, asynchronous access for
reads and writes to any location in memory. The CY7C024E and
CY7C025E/CY7C0251E can be used as standalone 16 or 18-bit
dual-port static RAMs or multiple devices can be combined to
function as a 32-/36-bit or wider master/ slave dual-port static
RAM. An M/S pin is provided for implementing 32-/36-bit or wider
memory applications without the need for separate master and
slave devices or additional discrete logic. Application areas
include interprocessor/multiprocessor designs, communications
status buffering, and dual-port video/graphics memory.
■
Expandable data bus to 32/36 bits or more using master/slave
chip select when using more than one device
■
On-chip arbitration logic
■
Semaphores included to permit software handshaking
between ports
■
INT flag for port-to-port communication
■
Separate upper-byte and lower-byte control
■
Pin select for master or slave
■
Available in Pb-free 100-pin thin quad flatpack (TQFP) package
Each port has independent control pins: Chip Enable (CE), Read
or Write Enable (R/W), and Output Enable (OE). Two flags are
provided on each port (BUSY and INT). BUSY signals that the
port is trying to access the same location currently being
accessed by the other port. The Interrupt Flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from one
port to the other to indicate that a shared resource is in use. The
semaphore logic is comprised of eight shared latches. Only one
side can control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power-down feature is controlled independently on
each port by a CE pin.
The CY7C024E and CY7C025E/CY7C0251E are available in
100-pin Pb-free TQFP.
For a complete list of related documentation, click here.
Selection Guide
-15
-25
-55
Maximum access time (ns)
Parameter
15
25
55
Typical operating current (mA)
190
170
150
Typical standby current for ISB1 (mA)
50
40
20
Cypress Semiconductor Corporation
Document Number: 001-62932 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 17, 2017
CY7C024E
CY7C025E
CY7C0251E
Logic Block Diagram
R/WL
UB L
R/WR
UB R
LB L
CE L
LBR
CE
R
OE R
OE L
[10]
I/O 8L – I/O 15L
I/O8R – I/O 15R[3]
I/O
CONTROL
I/O
CONTROL
[9]
I/O 0R – I/O 7R [2]
I/O 0L – I/O 7L
BUSYL
[6]
BUSYR
[1]
A12R (CY7C025E/0251E)
(CY7C025E/0251E) A12L
A11L
ADDRESS
DECODER
MEMORY
ARRAY
A11R
ADDRESS
DECODER
A0L
A 0R
CE L
OE L
INTERRUPT
SEMAPHORE
ARBITRATION
UB L
LB L
R/W L
SEML
INTL
CE R
OE R
UB R
LB R
R/W R
SEM R
M/S
INT R
Notes
1. BUSY is an output in master mode and an input in slave mode.
2. I/O0–I/O8 on the CY7C0251E.
3. I/O9–I/O17 on the CY7C0251E.
Document Number: 001-62932 Rev. *H
Page 2 of 24
CY7C024E
CY7C025E
CY7C0251E
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Architecture ...................................................................... 6
Functional Overview ........................................................ 6
Write Operation ........................................................... 6
Read Operation ........................................................... 7
Interrupts ..................................................................... 7
Busy ............................................................................ 8
Master/Slave ............................................................... 8
Semaphore Operation ................................................. 8
Maximum Ratings ............................................................. 9
Operating Range ............................................................... 9
Electrical Characteristics ................................................. 9
Capacitance .................................................................... 10
AC Test Loads and Waveforms ..................................... 10
Data Retention Mode ...................................................... 10
Data Retention Timing ................................................... 10
Document Number: 001-62932 Rev. *H
Switching Characteristics .............................................. 11
Switching Waveforms .................................................... 13
Ordering Information ...................................................... 19
4K × 16 Dual-Port SRAM .......................................... 19
8K × 16 Dual-Port SRAM .......................................... 19
Ordering Code Definitions ......................................... 19
Package Diagrams .......................................................... 20
Acronyms ........................................................................ 21
Document Conventions ................................................. 21
Units of Measure ....................................................... 21
Document History Page ................................................. 22
Sales, Solutions, and Legal Information ...................... 24
Worldwide Sales and Design Support ....................... 24
Products .................................................................... 24
PSoC® Solutions ...................................................... 24
Cypress Developer Community ................................. 24
Technical Support ..................................................... 24
Page 3 of 24
CY7C024E
CY7C025E
CY7C0251E
Pin Configurations
A7L
A6L
A9L
A8L
UBL
LBL
NC [4]
A11L
A10L
OEL
VCC
R/WL
SEML
CEL
I/O1L
I/O0L
I/O4L
I/O3L
I/O2L
GND
I/O9L
I/O8L
I/O7L
I/O6L
I/O5L
Figure 1. 100-pin TQFP pinout (Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CY7C024E/CY7C025E
NC
NC
NC
NC
A5L
A4L
A3L
A2L
A1L
A0L
INTL
BUSYL
GND
M/S
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
NC
NC
NC
NC
A7R
A6R
A5R
NC[5]
A11R
A10R
A9R
A8R
R/WR
GND
SEMR
CER
UBR
LBR
GND
I/O15R
ŒR
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
I/O7R
I/O8R
I/O9R
I/O10R
I/O11R
I/O12R
VCC
GND
I/O0R
I/O1R
I/O2R
VCC
I/O3R
I/O4R
I/O5R
I/O6R
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
I/O13R
I/O14R
NC
NC
NC
NC
I/O10L
I/O11L
I/O12L
I/O13L
GND
I/O14L
I/O15L
Notes
4. A12L on the CY7C025E/CY7C0251E.
5. A12R on the CY7C025E/CY7C0251E.
Document Number: 001-62932 Rev. *H
Page 4 of 24
CY7C024E
CY7C025E
CY7C0251E
Figure 2. 100-pin TQFP pinout (Top View)
A7L
A6L
A9L
A8L
UBL
LBL
NC [6]
A11L
A10L
OEL
VCC
R/WL
SEML
CEL
I/O1L
I/O0L
I/O4L
I/O3L
I/O2L
GND
I/O10L
I/O9L
I/O7L
I/O6L
I/O5L
100-Pin TQFP
Top View
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
CY7C0251E
NC
NC
NC
NC
A5L
A4L
A3L
A2L
A1L
A0L
INTL
BUSYL
GND
M/S
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
NC
NC
NC
NC
A7R
A6R
A5R
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
I/O7R
I/O9R
NC
NC
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC[7]
A11R
A10R
A9R
A8R
VCC
GND
I/O0R
I/O1R
I/O2R
VCC
I/O3R
I/O4R
I/O5R
I/O6R
I/O8R
I/O17R
I/O10R
I/O11R
I/O12R
I/O13R
I/O14R
I/O15R
GND
I/O16R
OER
R/WR
GND
SEMR
CER
UBR
LBR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
NC
NC
I/O8L
I/O17L
I/O11L
I/O12L
I/O13L
I/O14L
GND
I/O15L
I/O16L
Pin Definitions
Left Port
Right Port
Description
CEL
CER
Chip enable
R/WL
R/WR
Read/write enable
OEL
OER
Output enable
A0L–A11/12L
A0R–A11/12R
Address
I/O0L–I/O15/17L
I/O0R–I/O15/17R
Data bus input/output
SEML
SEMR
Semaphore enable
UBL
UBR
Upper byte select
LBL
LBR
Lower byte select
INTL
INTR
BUSYL[8]
BUSYR
Interrupt flag
[8]
Busy flag
M/S
Master or slave select
VCC
Power
GND
Ground
Notes
6. A12L on the CY7C025E/CY7C0251E.
7. A12R on the CY7C025E/CY7C0251E.
8. BUSY is an output in master mode and an input in slave mode.
Document Number: 001-62932 Rev. *H
Page 5 of 24
CY7C024E
CY7C025E
CY7C0251E
Architecture
Functional Overview
The CY7C024E and CY7C025E/CY7C0251E consist of an array
of 4K words of 16 bits each and 8K words of 16/18 bits each of
dual-port RAM cells, I/O and address lines, and control signals
(CE, OE, R/W). These control pins permit independent access
for reads or writes to any location in memory. To handle
simultaneous writes/reads to the same location, a BUSY pin is
provided on each port. Two interrupt (INT) pins can be used for
port-to-port communication. Two semaphore (SEM) control pins
are used for allocating shared resources. With the M/S pin, the
CY7C024E and CY7C025E/CY7C0251E can function as a
master (BUSY pins are outputs) or as a slave (BUSY pins are
inputs). The CY7C024E and CY7C025E/CY7C0251E have an
automatic power-down feature controlled by CE. Each port is
provided with its own output enable control (OE), which allows
data to be read from the device.
Write Operation
Data must be set up for a duration of tSD before the rising edge
of R/W to guarantee a valid write. A write operation is controlled
by either the R/W pin (see Figure 7) or the CE pin (see Figure 8).
Required inputs for non-contention operations are summarized
in Table 1.
If a location is being written to by one port and the opposite port
attempts to read that location, a port-to-port flowthrough delay
must occur before the data is read on the output; otherwise the
data read is not deterministic. Data is valid on the port tDDD after
the data is presented on the other port.
Table 1. Non-Contending Read/Write
Inputs
Outputs
I/O0–I/O7
[9]
Operation
I/O8–I/O15[10]
CE
R/W
OE
UB
LB
SEM
H
X
X
X
X
H
X
X
X
H
H
H
High Z
High Z
Deselected: power-down
L
L
X
L
H
H
High Z
Data in
Write to upper byte only
L
L
X
H
L
H
Data in
High Z
Write to lower byte only
L
L
X
L
L
H
Data in
Data in
Write to both bytes
L
H
L
L
H
H
High Z
Data out
Read upper byte only
L
H
L
H
L
H
Data out
High Z
Read lower byte only
L
H
L
L
L
H
Data out
Data out
Read both bytes
X
X
H
X
X
X
High Z
High Z
Outputs disabled
H
H
L
X
X
L
Data out
Data out
Read data in semaphore flag
X
H
L
H
H
L
Data out
Data out
Read data in semaphore flag
H
X
X
X
L
Data in
Data in
Write DIN0 into semaphore flag
X
X
H
H
L
Data in
Data in
Write DIN0 into semaphore flag
High Z
High Z
Deselected: power-down
L
X
X
L
X
L
Not allowed
L
X
X
X
L
L
Not allowed
Notes
9. I/O0–I/O8 on the CY7C0251E.
10. I/O9–I/O17 on the CY7C0251E.
Document Number: 001-62932 Rev. *H
Page 6 of 24
CY7C024E
CY7C025E
CY7C0251E
Read Operation
When reading the device, the user must assert both the OE and
CE pins. Data is available tACE after CE or tDOE after OE is
asserted.
If
the
user
of
the
CY7C024E
and
CY7C025E/CY7C0251E wishes to access a semaphore flag,
then the SEM pin must be asserted instead of the CE pin, and
OE must also be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (FFF for the CY7C024E,
1FFF for the CY7C025E/CY7C0251E) is the mailbox for the right
port and the second-highest memory location (FFE for the
CY7C024E, 1FFE for the CY7C025E/CY7C0251E) is the
mailbox for the left port. When one port writes to the other port’s
mailbox, an interrupt is generated to the owner. The interrupt is
reset when the owner reads the contents of the mailbox. The
message is user-defined.
Each port can read the other port’s mailbox without resetting the
interrupt. The active state of the BUSY signal (to a port) prevents
the port from setting the interrupt to the winning port. Also, an
active BUSY to a port prevents that port from reading its own
mailbox and thus resetting the interrupt to it.
If your application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin.
The operation of the interrupts and their interaction with Busy are
summarized in Table 2.
Table 2. Interrupt Operation Example (Assumes BUSYL=BUSYR=HIGH)[11]
Function
Left Port
Right Port
R/WL
CEL
OEL
A0L–11L
INTL
R/WR
CER
OER
A0R–11R
INTR
Set right INTR flag
L
L
X
(1)FFF
X
X
X
X
X
L[12]
Reset right INTR flag
X
X
X
X
X
X
L
L
(1)FFF
H[13]
Set left INTL flag
X
X
X
X
L[13]
L
L
X
(1)FFE
X
Reset left INTL flag
X
L
L
(1)FFE
H[12]
X
X
X
X
X
Notes
11. A0L–12L and A0R–12R, 1FFF/1FFE for the CY7C025E/CY7C0251E.
12. If BUSYL = L, then no change.
13. If BUSYR = L, then no change.
Document Number: 001-62932 Rev. *H
Page 7 of 24
CY7C024E
CY7C025E
CY7C0251E
Busy
The CY7C024E and CY7C025E/CY7C0251E provide on-chip
arbitration to resolve simultaneous memory location access
(contention). If both ports’ CEs are asserted and an address
match occurs within tPS of each other, the busy logic determines
which port has access. If tPS is violated, one port definitely gains
permission to the location, but which one is not predictable.
BUSY is asserted tBLA after an address match or tBLC after CE
is taken LOW.
Master/Slave
A M/S pin is provided to expand the word width by configuring
the device as either a master or a slave. The BUSY output of the
master is connected to the BUSY input of the slave. This allows
the device to interface to a master device with no external
components. Writing to slave devices must be delayed until after
the BUSY input has settled (tBLC or tBLA). Otherwise, the slave
chip may begin a write cycle during a contention situation. When
tied HIGH, the M/S pin allows the device to be used as a master
and, therefore, the BUSY line is an output. BUSY can then be
used to send the arbitration outcome to a slave.
Semaphore Operation
The CY7C024E and CY7C025E/CY7C0251E provide eight
semaphore latches, which are separate from the dual-port
memory locations. Semaphores are used to reserve resources
that are shared between the two ports. The state of the
semaphore indicates that a resource is in use. For example, if
the left port wants to request a given resource, it sets a latch by
writing a zero to a semaphore location. The left port then verifies
its success in setting the latch by reading it. After writing to the
semaphore, SEM or OE must be deasserted for tSOP before
attempting to read the semaphore. The semaphore value is
available tSWRD + tDOE after the rising edge of the semaphore
write. If the left port was successful (reads a zero), it assumes
control of the shared resource, otherwise (reads a one) it
assumes the right port has control and continues to poll the
semaphore. When the right side has relinquished control of the
semaphore (by writing a one), the left side succeeds in gaining
control of the semaphore. If the left side no longer requires the
semaphore, a one is written to cancel its request.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A0–2 represents the
semaphore address. OE and R/W are used in the same manner
as a normal memory access. When writing or reading a
semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O0 is used. If a zero is
written to the left port of an available semaphore, a one appears
at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes control
by writing a one to the semaphore, the semaphore is set to one
for both sides. However, if the right port had requested the
semaphore (written a zero) while the left port had control, the
right port immediately owns the semaphore as soon as the left
port releases it. Table 3 shows sample semaphore operations.
When reading a semaphore, all 16/18 data lines output the
semaphore value. The read value is latched in an output register
to prevent the semaphore from changing state during a write
from the other port. If both ports attempt to access the
semaphore within tSPS of each other, the semaphore is definitely
obtained by one side or the other, but there is no guarantee which
side controls the semaphore.
Table 3. Semaphore Operation Example
I/O0–I/O15/17
Left
I/O0–I/O15/17
Right
No action
1
1
Semaphore-free
Left port writes 0 to semaphore
0
1
Left port has semaphore token
Right port writes 0 to semaphore
0
1
No change. Right side has no write access to
semaphore.
Left port writes 1 to semaphore
1
0
Right port obtains semaphore token
Left port writes 0 to semaphore
1
0
No change. Left port has no write access to
semaphore
Right port writes 1 to semaphore
0
1
Left port obtains semaphore token
Left port writes 1 to semaphore
1
1
Semaphore-free
Right port writes 0 to semaphore
1
0
Right port has semaphore token
Right port writes 1 to semaphore
1
1
Semaphore-free
Left port writes 0 to semaphore
0
1
Left port has semaphore token
Left port writes 1 to semaphore
1
1
Semaphore-free
Function
Document Number: 001-62932 Rev. *H
Status
Page 8 of 24
CY7C024E
CY7C025E
CY7C0251E
DC input voltage[15] .....................................–0.5 V to +7.0 V
Maximum Ratings
Exceeding maximum ratings[14] may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage
(per MIL-STD-883, Method 3015) ......................... > 2001 V
Latch-up current ................................................... > 200 mA
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Operating Range
Supply voltage to ground potential ..............–0.3 V to +7.0 V
Range
DC voltage applied to outputs
in high Z state ...............................................–0.5 V to +7.0 V
Ambient Temperature
VCC
0 °C to +70 °C
5 V 10%
–40 °C to +85 °C
5 V 10%
Commercial
Industrial
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
-15
-25
-55
Min Typ Max Min Typ Max Min Typ Max
Unit
VOH
Output HIGH
voltage
VCC = Min, IOH = –4.0 mA
VOL
Output LOW
voltage
VCC = Min, IOL = 4.0 mA
VIH
Input HIGH voltage
VIL
Input LOW voltage
–
IIX
Input leakage
current
GND VI VCC
–10
IOZ
Output leakage
current
Output disabled,
GND VO VCC
–10
–
ICC
Operating current
VCC = Max, IOUT = 0 mA,
Outputs Disabled
Commercial
–
190 285
–
170 250
–
150 230 mA
Industrial
–
215 305
–
180 290
–
180 290
ISB1
Standby current
(both ports TTL
levels)
CEL and CER VIH,
f = fMAX[16]
Commercial
–
50
70
–
40
60
–
20
50
Industrial
–
65
95
–
55
80
–
55
80
Commercial
–
120 180
–
100 150
–
75
135 mA
Industrial
–
135 205
–
120 175
–
120 175
ISB2
ISB3
ISB4
Standby current
CEL or CER VIH,
(one port TTL level) f = fMAX[16]
Standby current
Both Ports CE and CER
Commercial
(both ports CMOS VCC – 0.2 V, VIN VCC – 0.2 V
Industrial
or VIN 0.2 V, f = 0[16]
levels)
Standby current
One Port CEL or
Commercial
(both ports CMOS CER VCC – 0.2 V,
Industrial
levels)
VIN VCC – 0.2 V or VIN 0.2 V,
[16]
Active Port Outputs, f = fMAX
2.4
–
–
2.4
–
–
2.4
–
–
V
–
–
0.4
–
–
0.4
–
–
0.4
V
2.2
–
–
2.2
–
–
2.2
–
–
V
–
0.8
–
–
0.8
–
–
0.8
V
–
+10 –10
–
+10 –10
–
+10
A
+10 –10
–
+10 –10
–
+10
A
mA
–
0.05 0.5
–
0.05 0.50
–
0.05 0.50 mA
–
0.05 0.5
–
0.05 0.50
–
0.05 0.50
–
110 160
–
90
130
–
70
–
125 175
–
110 150
–
110 150
120 mA
Notes
14. The voltage on any input or I/O pin cannot exceed the power pin during power-up.
15. Pulse width < 20 ns.
16. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level
standby ISB3.
Document Number: 001-62932 Rev. *H
Page 9 of 24
CY7C024E
CY7C025E
CY7C0251E
Capacitance
Parameter [17]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz,
VCC = 5.0 V
Max
Unit
10
pF
10
pF
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
5V
5V
R1 = 893
RTH = 250
OUTPUT
OUTPUT
R1 = 893
OUTPUT
C = 30 pF
C = 30 pF
R2 = 347
C = 5 pF
R2 = 347
VTH = 1.4 V
(a) Normal Load (Load 1)
(c) Three-State Delay(Load 3)
(b) Thévenin Equivalent (Load 1)
ALL INPUT PULSES
OUTPUT
3.0 V
C = 30 pF
GND
10%
90%
10%
90%
3 ns
3 ns
Load (Load 2)
Data Retention Mode
The CY7C024E is designed with battery backup in mind. Data
retention voltage and supply current are guaranteed over
temperature. The following rules insure data retention:
1. Chip enable (CE) must be held HIGH during data retention,
within VCC to VCC – 0.2 V.
2. CE must be kept between VCC – 0.2 V and 70% of VCC during
the power up and power down transitions.
3. The RAM can begin operation >tRC after VCC reaches the
minimum operating voltage (4.5 V).
Data Retention Timing
Data Retention Mode
VCC
4.5 V
VCC 2.0 V
4.5 V
VCC to VCC – 0.2 V
CE
Parameter
ICCDR1
Test Conditions[18]
At VCCDR = 2 V
tRC
V
IH
Max
Unit
1.5
mA
Notes
17. Tested initially and after any design or process changes that may affect these parameters.
18. CE = VCC, Vin = GND to VCC, TA = 25C. This parameter is guaranteed but not tested.
Document Number: 001-62932 Rev. *H
Page 10 of 24
CY7C024E
CY7C025E
CY7C0251E
Switching Characteristics
Over the Operating Range
Parameter [19]
Description
-15
-25
-55
Min
Max
Min
Max
Min
Max
Unit
Read Cycle
tRC
Read cycle time
15
–
25
–
55
–
ns
tAA
Address to data valid
–
15
–
25
–
55
ns
tOHA
Output hold from address change
3
–
3
–
3
–
ns
tACE[20]
CE LOW to data valid
–
15
–
25
–
55
ns
tDOE
OE LOW to data valid
–
10
–
13
–
25
ns
tLZOE[21, 22, 23]
tHZOE[21, 22, 23]
tLZCE[21, 22, 23]
tHZCE[21, 22, 23]
tPU[23]
tPD[23]
tABE[20]
OE low to low Z
3
–
3
–
3
–
ns
OE HIGH to high Z
–
10
–
15
–
25
ns
CE LOW to low Z
3
–
3
–
3
–
ns
CE HIGH to High Z
–
10
–
15
–
25
ns
CE LOW to power-up
0
–
0
–
0
–
ns
CE HIGH to power-down
–
15
–
25
–
55
ns
Byte enable access time
–
15
–
25
–
55
ns
tWC
Write cycle time
15
–
25
–
55
–
ns
tSCE[20]
CE LOW to write end
12
–
20
–
35
–
ns
tAW
Address setup to write end
12
–
20
–
35
–
ns
tHA
Address hold from write end
0
–
0
–
0
–
ns
tSA[24]
Address setup to write start
0
–
0
–
0
–
ns
tPWE
Write pulse width
12
–
20
–
35
–
ns
tSD
Data setup to write end
10
–
15
–
20
–
ns
tHD
Data hold from write end
0
–
0
–
0
–
ns
tHZWE[25, 26]
tLZWE[25, 26]
tWDD[27]
tDDD[27]
R/W LOW to high Z
–
10
–
15
–
25
ns
R/W HIGH to low Z
3
–
3
–
3
–
ns
Write pulse to data delay
–
30
–
50
–
70
ns
Write data valid to read
data valid
–
25
–
35
–
45
ns
Write Cycle
Notes
19. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOI/IOH
and 30 pF load capacitance.
20. To access RAM, CE=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire tSCE time.
21. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
22. Test conditions used are Load 3.
23. This parameter is guaranteed but not tested.
24. To access RAM, CE=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire tSCE time.
25. Test conditions used are Load 3.
26. This parameter is guaranteed but not tested.
27. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Figure 11 on page 16.
Document Number: 001-62932 Rev. *H
Page 11 of 24
CY7C024E
CY7C025E
CY7C0251E
Switching Characteristics (continued)
Over the Operating Range
Parameter [19]
Description
-15
-25
-55
Min
Max
Min
Max
Min
Max
Unit
Busy Timing[28]
tBLA
BUSY LOW from Address Match
–
15
–
20
–
45
ns
tBHA
BUSY HIGH from Address
Mismatch
–
15
–
20
–
40
ns
tBLC
BUSY LOW from CE LOW
–
15
–
20
–
40
ns
tBHC
BUSY HIGH from CE HIGH
–
15
–
20
–
35
ns
tPS
Port Setup for Priority
5
–
5
–
5
–
ns
tWB
R/W HIGH after BUSY (Slave)
0
–
0
–
0
–
ns
tWH
R/W HIGH after BUSY HIGH (Slave)
13
–
20
–
40
–
ns
tBDD[29]
BUSY HIGH to Data Valid
–
Note 29
Note 29
ns
Interrupt
Note 29
Timing[28]
tINS
INT Set Time
–
15
–
20
–
30
ns
tINR
INT Reset Time
–
15
–
20
–
30
ns
Semaphore Timing
tSOP
SEM Flag Update Pulse (OE or SEM)
10
–
12
–
20
–
ns
tSWRD
SEM Flag Write to Read Time
5
–
10
–
15
–
ns
tSPS
SEM Flag Contention Window
5
–
10
–
15
–
ns
tSAA
SEM Address Access Time
–
15
25
–
55
ns
Notes
28. Test conditions used are Load 2.
29. tBDD is a calculated parameter and is the greater of tWDD– tPWE (actual) or tDDD– tSD (actual).
Document Number: 001-62932 Rev. *H
Page 12 of 24
CY7C024E
CY7C025E
CY7C0251E
Switching Waveforms
Figure 4. Read Cycle No. 1 (Either Port Address Access) [30, 31, 32]
tRC
ADDRESS
tOHA
DATA OUT
tAA
tOHA
PREVIOUS DATA VALID
DATA VALID
Figure 5. Read Cycle No. 2 (Either Port CE/OE Access) [30, 33, 34]
tACE
CE and
LB or UB
tHZCE
tDOE
OE
tHZOE
tLZOE
DATA VALID
DATA OUT
tLZCE
tPU
tPD
ICC
CURRENT
ISB
Figure 6. Read Cycle No. 3 (Either Port) [30, 32, 33, 34]
tRC
ADDRESS
tAA
tOHA
UB or LB
tHZCE
tLZCE
tABE
CE
tHZCE
tACE
tLZCE
DATA OUT
Notes
30. R/W is HIGH for read cycles.
31. Device is continuously selected CE = VIL and UB or LB = VIL. This waveform cannot be used for semaphore reads.
32. OE = VIL.
33. Address valid prior to or coincident with CE transition LOW.
34. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.
Document Number: 001-62932 Rev. *H
Page 13 of 24
CY7C024E
CY7C025E
CY7C0251E
Switching Waveforms (continued)
Figure 7. Write Cycle No. 1 (R/W Controlled Timing) [35, 36, 37, 38]
tWC
ADDRESS
tHZOE [41]
OE
tAW
CE
[39,40]
tPWE[38]
tSA
tHA
R/W
tHZWE[41]
DATA OUT
tLZWE
NOTE 42
NOTE 42
tSD
tHD
DATA IN
Figure 8. Write Cycle No. 2 (CE Controlled Timing) [35, 36, 37, 43]
tWC
ADDRESS
tAW
CE
[39,40]
tSA
tSCE
tHA
R/W
tSD
tHD
DATA IN
Notes
35. R/W must be HIGH during all address transitions.
36. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM and a LOW UB or LB.
37. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
38. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to
be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified tPWE.
39. To access RAM, CE = VIL, SEM = VIH.
40. To access upper byte, CE = VIL, UB = VIL, SEM = VIH.
To access lower byte, CE = VIL, LB = VIL, SEM = VIH.
41. Transition is measured ±500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100% tested.
42. During this period, the I/O pins are in the output state, and input signals must not be applied.
43. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.
Document Number: 001-62932 Rev. *H
Page 14 of 24
CY7C024E
CY7C025E
CY7C0251E
Switching Waveforms (continued)
Figure 9. Semaphore Read After Write Timing, Either Side [44]
tOHA
tAA
A 0–A 2
VALID ADRESS
VALID ADRESS
tAW
tACE
tHA
SEM
tSCE
tSOP
tSD
I/O 0
DATAIN VALID
tSA
tPWE
DATAOUT VALID
tHD
R/W
tSWRD
tDOE
tSOP
OE
WRITE CYCLE
READ CYCLE
Figure 10. Timing Diagram of Semaphore Contention [45, 46, 47]
A0L –A2L
MATCH
R/WL
SEM L
tSPS
A 0R –A 2R
MATCH
R/WR
SEM R
Notes
44. CE = HIGH for the duration of the above timing (both write and read cycle).
45. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH.
46. Semaphores are reset (available to both ports) at cycle start.
47. If tSPS is violated, the semaphore is definitely obtained by one side or the other, but which side gets the semaphore is unpredictable.
Document Number: 001-62932 Rev. *H
Page 15 of 24
CY7C024E
CY7C025E
CY7C0251E
Switching Waveforms (continued)
Figure 11. Timing Diagram of Read with BUSY (M/S = HIGH) [48]
tWC
ADDRESSR
MATCH
tPWE
R/WR
tHD
tSD
DATA INR
VALID
tPS
ADDRESSL
MATCH
tBLA
tBHA
BUSYL
tBDD
tDDD
DATA OUTL
VALID
tWDD
Figure 12. Write Timing with Busy Input (M/S = LOW)
tPWE
R/W
BUSY
tWB
tWH
Note
48. CEL = CER = LOW.
Document Number: 001-62932 Rev. *H
Page 16 of 24
CY7C024E
CY7C025E
CY7C0251E
Switching Waveforms (continued)
Figure 13. Busy Timing Diagram No. 1 (CE Arbitration) [49]
CELValid First:
ADDRESS L,R
ADDRESS MATCH
CEL
tPS
CER
tBLC
tBHC
BUSYR
CER Valid First:
ADDRESS L,R
ADDRESS MATCH
CER
tPS
CE L
tBLC
tBHC
BUSY L
Figure 14. Busy Timing Diagram No. 2 (Address Arbitration) [49]
Left Address Valid First:
tRC or tWC
ADDRESS L
ADDRESS MATCH
ADDRESS MISMATCH
tPS
ADDRESSR
tBLA
tBHA
BUSY R
Right Address Valid First:
tRC or tWC
ADDRESSR
ADDRESS MATCH
ADDRESS MISMATCH
tPS
ADDRESSL
tBLA
tBHA
BUSY L
Note
49. If tPS is violated, the busy signal is asserted on one side or the other, but there is no guarantee to which side BUSY is asserted.
Document Number: 001-62932 Rev. *H
Page 17 of 24
CY7C024E
CY7C025E
CY7C0251E
Switching Waveforms (continued)
Figure 15. Interrupt Timing Diagrams
Left Side Sets INTR :
ADDRESSL
tWC
WRITE FFF (1FFF CY7C025)
tHA[50]
CE L
R/W L
INT R
tINS [51]
Right Side Clears INT R :
tRC
READ FFF
(1FFF CY7C025)
ADDRESSR
CE R
tINR [51]
R/WR
OE R
INTR
Right Side Sets INT L:
tWC
ADDRESSR
WRITE FFE (1FFE CY7C025)
tHA[50]
CE R
R/W R
INT L
[51]
tINS
Left Side Clears INT L:
tRC
READ FFE
(1FFE CY7C025)
ADDRESSR
CE L
tINR[51]
R/W L
OE L
INT L
Notes
50. tHA depends on which enable pin (CEL or R/WL) is deasserted first.
51. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
Document Number: 001-62932 Rev. *H
Page 18 of 24
CY7C024E
CY7C025E
CY7C0251E
Ordering Information
4K × 16 Dual-Port SRAM
Speed
(ns)
Package
Name
Ordering Code
Package Type
Operating
Range
15
CY7C024E-15AXC
A100
100-pin TQFP (Pb-free)
Commercial
25
CY7C024E-25AXC
A100
100-pin TQFP (Pb-free)
Commercial
CY7C024E-25AXI
A100
100-pin TQFP (Pb-free)
Industrial
CY7C024E-55AXC
A100
100-pin TQFP (Pb-free)
Commercial
55
8K × 16 Dual-Port SRAM
Speed
(ns)
25
Package
Name
Ordering Code
Package Type
Operating
Range
CY7C025E-25AXC
A100
100-pin TQFP (Pb-free)
Commercial
CY7C025E-25AXI
A100
100-pin TQFP (Pb-free)
Industrial
Ordering Code Definitions
CY 7 C 02X
X
E - XX
A
X X
Temperature Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Type: A = 100-pin TQFP
Speed: XX = 15 ns or 25 ns or 55 ns
Die Revision
Data width: X = blank or 1
blank = × 16; 1 = × 18
Density: 02X = 024 or 025
024 = 4-Kbit; 025 = 8-Kbit
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-62932 Rev. *H
Page 19 of 24
CY7C024E
CY7C025E
CY7C0251E
Package Diagrams
Figure 16. 100-pin TQFP (14 × 14 × 1.4 mm) A100SA Package Outline, 51-85048
51-85048 *J
Document Number: 001-62932 Rev. *H
Page 20 of 24
CY7C024E
CY7C025E
CY7C0251E
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CE
Chip Enable
CMOS
Complementary Metal Oxide Semiconductor
°C
degree Celsius
I/O
Input/Output
MHz
megahertz
OE
Output Enable
A
microampere
SRAM
Static Random Access Memory
mA
milliampere
TQFP
Thin Quad Flat Pack
ns
nanosecond
ohm
%
percent
pF
picofarad
V
volt
W
watt
Document Number: 001-62932 Rev. *H
Symbol
Unit of Measure
Page 21 of 24
CY7C024E
CY7C025E
CY7C0251E
Document History Page
Document Title: CY7C024E/CY7C025E/CY7C0251E, 4K × 16 and 8K × 16/18 Dual-Port Static RAM with SEM, INT, BUSY
Document Number: 001-62932
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
2975554
RAME
07/09/2010
New data sheet.
*A
3056347
ADMU
10/28/2010
Updated Selection Guide:
Changed Typical Operating current (mA) from 180 mA to 170 mA
(corresponding to speed bin -25).
Changed Typical standby current for ISB1 (mA) from 45 mA to 40 mA
(corresponding to speed bin -25).
Changed Typical Operating current (mA) from 180 mA to 150 mA
(corresponding to speed bin -55).
Changed Typical standby current for ISB1 (mA) from 45 mA to 20 mA
(corresponding to speed bin -55).
Updated Electrical Characteristics:
Separated values corresponding to speed bins -25 and -55 into two separate
columns.
Changed typical value of ICC parameter from 180 mA to 170 mA
(corresponding to speed bin -25 and test condition “Commercial”).
Changed maximum value of ICC parameter from 275 mA to 250 mA
(corresponding to speed bin -25 and test condition “Commercial”).
Changed typical value of ICC parameter from 180 mA to 150 mA
(corresponding to speed bin -55 and test condition “Commercial”).
Changed maximum value of ICC parameter from 275 mA to 230 mA
(corresponding to speed bin -55 and test condition “Commercial”).
Changed typical value of ISB1 parameter from 45 mA to 40 mA (corresponding
to speed bin -25 and test condition “Commercial”).
Changed maximum value of ISB1 parameter from 65 mA to 60 mA
(corresponding to speed bin -25 and test condition “Commercial”).
Changed typical value of ISB1 parameter from 45 mA to 20 mA (corresponding
to speed bin -55 and test condition “Commercial”).
Changed maximum value of ISB1 parameter from 65 mA to 50 mA
(corresponding to speed bin -55 and test condition “Commercial”).
Changed typical value of ISB2 parameter from 110 mA to 100 mA
(corresponding to speed bin -25 and test condition “Commercial”).
Changed maximum value of ISB2 parameter from 160 mA to 150 mA
(corresponding to speed bin -25 and test condition “Commercial”).
Changed typical value of ISB2 parameter from 110 mA to 75 mA (corresponding
to speed bin -55 and test condition “Commercial”).
Changed maximum value of ISB2 parameter from 160 mA to 135 mA
(corresponding to speed bin -55 and test condition “Commercial”).
Changed typical value of ISB4 parameter from 100 mA to 90 mA (corresponding
to speed bin -25 and test condition “Commercial”).
Changed maximum value of ISB4 parameter from 140 mA to 130 mA
(corresponding to speed bin -25 and test condition “Commercial”).
Changed typical value of ISB4 parameter from 100 mA to 70 mA (corresponding
to speed bin -55 and test condition “Commercial”).
Changed maximum value of ISB4 parameter from 140 mA to 120 mA
(corresponding to speed bin -55 and test condition “Commercial”).
Updated Ordering Information:
Updated part numbers.
*B
3247559
ADMU
05/04/2011
Updated Electrical Characteristics:
Removed minimum value of VIL parameter (for all speed bins).
Updated Ordering Code Definitions under Ordering Information.
Updated Package Diagrams:
spec 51-85048 – Changed revision from *D to *E.
Document Number: 001-62932 Rev. *H
Description of Change
Page 22 of 24
CY7C024E
CY7C025E
CY7C0251E
Document History Page (continued)
Document Title: CY7C024E/CY7C025E/CY7C0251E, 4K × 16 and 8K × 16/18 Dual-Port Static RAM with SEM, INT, BUSY
Document Number: 001-62932
Rev.
ECN No.
Orig. of
Change
Submission
Date
*C
3864478
ADMU
01/10/2013
Updated Ordering Information:
Updated part numbers.
Updated Package Diagrams:
spec 51-85048 – Changed revision from *E to *G.
*D
4075480
ADMU
07/24/2013
Updated Logic Block Diagram.
Updated Pin Configurations.
Updated to new template.
Completing Sunset Review.
*E
4093991
ADMU
08/13/2013
Updated Package Diagrams:
spec 51-85048 – Changed revision from *G to *H.
Added Units of Measure.
*F
4447806
ADMU
07/18/2014
Removed CY7C0241E related information in all instances across the
document.
Updated Ordering Information:
Updated part numbers.
Updated Package Diagrams:
spec 51-85048 – Changed revision from *H to *I.
*G
4580426
ADMU
11/24/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*H
5856565
VINI
08/17/2017
Updated Ordering Information:
Updated part numbers.
Updated Package Diagrams:
spec 51-85048 – Changed revision from *I to *J.
Updated to new template.
Completing Sunset Review.
Document Number: 001-62932 Rev. *H
Description of Change
Page 23 of 24
CY7C024E
CY7C025E
CY7C0251E
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
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cypress.com/arm
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cypress.com/clocks
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cypress.com/iot
cypress.com/memory
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cypress.com/mcu
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Cypress Developer Community
Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components
Technical Support
cypress.com/support
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Touch Sensing
cypress.com/touch
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Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2010–2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
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permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
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are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-62932 Rev. *H
Revised August 17, 2017
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