CY7C026AV-20AXC

CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV 3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM Features • True dual-ported memory cells which allow simultaneous access of the same memory location • 4/8/16K × 16 organization (CY7C024AV/025AV/026AV) • 4/8K × 18 organization (CY7C0241AV/0251AV) • 16K × 18 organization (CY7C036AV) • 0.35-micron CMOS for optimum speed/power • High-speed access: 20 and 25 ns • Low operating power — Active: ICC = 115 mA (typical) — Standby: ISB3 = 10 μA (typical) • Fully asynchronous operation • Automatic power-down • Expandable data bus to 32/36 bits or more using Master/Slave chip select when using more than one device • On-chip arbitration logic • Semaphores included to permit software handshaking between ports • INT flag for port-to-port communication • Separate upper-byte and lower-byte control • Pin select for Master or Slave • Commercial and industrial temperature ranges • Available in 100-pin Lead (Pb)-free TQFP and 100-pin TQFP Logic Block Diagram R/WL UBL R/WR UBR CEL LBL OEL 8/9 8/9 8/9 CER LBR OER [1] I/O8/9L–I/O15/17L I/O0L–I/O7/8L [2] [1] I/O Control I/O Control 8/9 I/O8/9L–I/O15/17R [2] I/O0L–I/O7/8R A0L–A11/1213L [3] 12/13/14 Address Decode 12/13/14 True Dual-Ported RAM Array Address Decode 12/13/14 12/13/14 A0R–A11/12/13R [3] [3] [3] A0L–A11/12/13L CEL OEL R/WL SEML [4] BUSYL INTL UBL LBL Notes: 1. I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices. 2. I/O0–I/O7 for x16 devices; I/O0–I/O8 for x18 devices. 3. A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices. 4. BUSY is an output in master mode and an input in slave mode. Interrupt Semaphore Arbitration A0R–A11/12/13R CER OER R/WR SEMR [4] M/S BUSYR INTR UBR LBR Cypress Semiconductor Corporation Document #: 38-06052 Rev. *H • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised June 15, 2005 CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV Pin Configurations 100-Pin TQFP Top View OEL VCC R/WL SEML CEL UBL LBL NC [5] A11L A10L I/O4L I/O3L I/O2L GND I/O9L I/O8L I/O7L I/O6L I/O5L I/O1L I/O0L A9L A8L A7L A6L 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC NC NC NC I/O10L I/O11L I/O12L I/O13L GND I/O14L I/O15L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 NC NC NC NC A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R NC NC NC NC CY7C024AV (4K × 16) CY7C025AV (8K × 16) 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 I/O7R I/O8R I/O9R I/O10R I/O11R I/O12R I/O13R I/O14R GND I/O15R ŒR R/WR GND SEMR CER UBR LBR NC[6] A11R A10R A9R A8R Notes: 5. A12L on the CY7C025AV. 6. A12R on the CY7C025AV. Document #: 38-06052 Rev. *H A7R A6R A5R Page 2 of 19 CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV Pin Configurations (continued) 100-Pin TQFP I/O10L I/O9L I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L GND I/O1L I/O0L Top View UBL LBL NC [7] A11L A10L A9L A8L A7L A6L 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC NC I/O8L I/O17L I/O11L I/O12L I/O13L I/O14L GND I/O15L I/O16L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R I/O8R I/O17R NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 NC NC NC NC A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R NC NC NC NC CY7C0241AV (4K × 18) CY7C0251AV (8K × 18) 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC NC NC NC I/O10L I/O11L I/O12L I/O13L GND I/O14L I/O15L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R NC NC NC NC 75 1 74 2 73 3 72 4 71 5 6 70 69 7 8 68 9 67 10 66 11 65 12 64 13 63 14 62 61 15 60 16 59 17 18 58 19 57 20 56 21 55 22 54 23 53 24 52 25 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC NC NC A6L A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R A5R NC NC NC Notes: 7. A12L on the CY7C0251AV. 8. A12R on the CY7C0251AVC. Document #: 38-06052 Rev. *H I/O7R I/O8R I/O9R I/O10R I/O11R I/O12R I/O13R I/O14R GND I/O15R OER R/WR GND SEMR CER UBR LBR A13R A12R A11R A10R A9R A8R A7R A6R I/O9L I/O7R I/O8L I/O9R I/O7L I/O10R I/O6L I/O11R I/O5L I/O12R I/O4L I/O13R I/O3L I/O14R I/O2L I/O15R GND GND I/O1L I/O16R I/O0L OER OEL R/WR GND VCC SEMR R/WL CER SEML UBR CEL LBR UBL NC [8] LBL A11R A13L A10R A12L A9R A11L A8R A10L A7R A9L A6R A8L A5R A7L CY7C026AV (16K × 16) OEL VCC R/WL SEML CEL Page 3 of 19 CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV Pin Configurations (continued) 100-Pin TQFP Top View I/O10L I/O9L I/O7L I/O6L I/O5L OEL VCC R/WL SEML CEL I/O4L I/O3L I/O2L GND I/O1L I/O0L UBL LBL A12L A11L A10L A9L A8L A7L A6L 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC NC I/O8L I/O17L I/O11L I/O12L I/O13L I/O14L GND I/O15L I/O16L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R I/O8R I/O17R NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 NC NC NC A13L A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R A13R NC NC NC CY7C036AV (16K × 18) 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 I/O7R I/O9R I/O10R I/O11R I/O12R I/O13R I/O14R I/O15R GND I/O16R OER R/WR GND SEMR CER UBR LBR A12R A11R A10R A9R A8R Selection Guide CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV -20 Maximum Access Time Typical Operating Current Typical Standby Current for ISB1 (Both ports TTL Level) Typical Standby Current for ISB3 (Both ports CMOS Level) 20 120 35 10 CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV -25 25 115 30 10 Unit ns mA mA μA Document #: 38-06052 Rev. *H A7R A6R A5R Page 4 of 19 CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV Pin Definitions Left Port CEL R/WL OEL A0L–A13L I/O0L–I/O17L SEML UBL LBL INTL BUSYL M/S VCC GND NC CER R/WR OER A0R–A13R I/O0R–I/O17R SEMR UBR LBR INTR BUSYR Right Port Chip Enable. Read/Write Enable. Output Enable. Address (A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K). Data Bus Input/Output. Semaphore Enable. Upper Byte Select (I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices). Lower Byte Select (I/O0–I/O7 for x16 devices; I/O0–I/O8 for x18 devices). Interrupt Flag. Busy Flag. Master or Slave Select. Power. Ground. No Connect. currently being accessed by the other port. The Interrupt flag (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a Chip Select (CE) pin. The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV/ 036AV are available in 100-pin Lead (Pb)-free Thin Quad Flat Pack (TQFP) and 100-pin TQFP. Write Operation Data must be set up for a duration of tSD before the rising edge of R/W in order to guarantee a valid write. A write operation is controlled by either the R/W pin (see Write Cycle No. 1 waveform) or the CE pin (see Write Cycle No. 2 waveform). Required inputs for non-contention operations are summarized in Table 1. If a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is read on the output; otherwise the data read is not deterministic. Data will be valid on the port tDDD after the data is presented on the other port. Read Operation When reading the device, the user must assert both the OE and CE pins. Data will be available tACE after CE or tDOE after OE is asserted. If the user wishes to access a semaphore flag, then the SEM pin must be asserted instead of the CE pin, and OE must also be asserted. Interrupts The upper two memory locations may be used for message passing. The highest memory location (FFF for the CY7C024AV/41AV, 1FFF for the CY7C025AV/51AV, 3FFF for Page 5 of 19 Description Architecture The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV/ 036AV consist of an array of 4K, 8K, and 16K words of 16 and 18 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. Two Interrupt (INT) pins can be utilized for port-to-port communication. Two Semaphore (SEM) control pins are used for allocating shared resources. With the M/S pin, the devices can function as a master (BUSY pins are outputs) or as a slave (BUSY pins are inputs). The devices also have an automatic power-down feature controlled by CE. Each port is provided with its own output enable control (OE), which allows data to be read from the device. Functional Description The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV /036AV are low-power CMOS 4K, 8K, and 16K ×16/18 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as standalone 16/18-bit dual-port static RAMs or multiple devices can be combined in order to function as a 32/36-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 32/36-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. Each port has independent control pins: Chip Enable (CE), Read or Write Enable (R/W), and Output Enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location Document #: 38-06052 Rev. *H CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV the CY7C026AV/36AV) is the mailbox for the right port and the second-highest memory location (FFE for the CY7C024AV/ 41AV, 1FFE for the CY7C025AV/51AV, 3FFE for the CY7C026AV/36AV) is the mailbox for the left port. When one port writes to the other port’s mailbox, an interrupt is generated to the owner. The interrupt is reset when the owner reads the contents of the mailbox. The message is user defined. Each port can read the other port’s mailbox without resetting the interrupt. The active state of the busy signal (to a port) prevents the port from setting the interrupt to the winning port. Also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. If an application does not require message passing, do not connect the interrupt pin to the processor’s interrupt request input pin. The operation of the interrupts and their interaction with Busy are summarized in Table 2. Busy The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV/ 036AV provide on-chip arbitration to resolve simultaneous memory location access (contention). If both ports’ CEs are asserted and an address match occurs within tPS of each other, the busy logic will determine which port has access. If tPS is violated, one port will definitely gain permission to the location, but it is not predictable which port will get that permission. BUSY will be asserted tBLA after an address match or tBLC after CE is taken LOW. Master/Slave A M/S pin is provided in order to expand the word width by configuring the device as either a master or a slave. The BUSY output of the master is connected to the BUSY input of the slave. This will allow the device to interface to a master device with no external components. Writing to slave devices must be delayed until after the BUSY input has settled (tBLC or tBLA), otherwise, the slave chip may begin a write cycle during a contention situation. When tied HIGH, the M/S pin allows the device to be used as a master and, therefore, the BUSY line is an output. BUSY can then be used to send the arbitration outcome to a slave. Semaphore Operation The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV/ 036AV provide eight semaphore latches, which are separate from the dual-port memory locations. Semaphores are used to reserve resources that are shared between the two ports. The state of the semaphore indicates that a resource is in use. For example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. The left port then verifies its success in setting the latch by reading it. After writing to the semaphore, SEM or OE must be deasserted for tSOP before attempting to read the semaphore. The semaphore value will be available tSWRD + tDOE after the rising edge of the semaphore write. If the left port was successful (reads a zero), it assumes control of the shared resource, otherwise (reads a one) it assumes the right port has control and continues to poll the semaphore. When the right side has relinquished control of the semaphore (by writing a one), the left side will succeed in gaining control of the semaphore. If the left side no longer requires the semaphore, a one is written to cancel its request. Semaphores are accessed by asserting SEM LOW. The SEM pin functions as a chip select for the semaphore latches (CE must remain HIGH during SEM LOW). A0–2 represents the semaphore address. OE and R/W are used in the same manner as a normal memory access. When writing or reading a semaphore, the other address pins have no effect. When writing to the semaphore, only I/O0 is used. If a zero is written to the left port of an available semaphore, a one will appear at the same semaphore address on the right port. That semaphore can now only be modified by the side showing zero (the left port in this case). If the left port now relinquishes control by writing a one to the semaphore, the semaphore will be set to one for both sides. However, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. Table 3 shows sample semaphore operations. When reading a semaphore, all sixteen/eighteen data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. If both ports attempt to access the semaphore within tSPS of each other, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore. Document #: 38-06052 Rev. *H Page 6 of 19 CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV Table 1. Non-Contending Read/Write Inputs CE H X L L L L L L X H X H X L L X X R/W X X L L L H H H X H H OE X X X X X L L L H L L X X X X UB X H L H L L H L X X H X H L X LB X H H L L H L L X X H X H X L SEM H H H H H H H H X L L L L L L I/O9–I/O17 High Z High Z Data In High Z Data In Data Out High Z Data Out High Z Data Out Data Out Data In Data In Outputs I/O0–I/O8 High Z High Z High Z Data In Data In High Z Data Out Data Out High Z Data Out Data Out Data In Data In Operation Deselected: Power-Down Deselected: Power-Down Write to Upper Byte Only Write to Lower Byte Only Write to Both Bytes Read Upper Byte Only Read Lower Byte Only Read Both Bytes Outputs Disabled Read Data in Semaphore Flag Read Data in Semaphore Flag Write DIN0 into Semaphore Flag Write DIN0 into Semaphore Flag Not Allowed Not Allowed Table 2. Interrupt Operation Example (assumes BUSYL = BUSYR = HIGH)[9] Left Port Function Set Right INTR Flag Reset Right INTR Flag Set Left INTL Flag Reset Left INTL Flag R/WL L X X X CEL L X X L OEL X X X L A0L–13L FFF[12] X X 1FFE[12] INTL X X L[10] H[11] R/WR X X L X CER X L L X Right Port OER X L X X A0R–13R X FFF (or 1/3FFF) 1FFE (or 1/3FFE) X INTR L[11] H[10] X X Table 3. Semaphore Operation Example Function No action Left port writes 0 to semaphore Right port writes 0 to semaphore Left port writes 1 to semaphore Left port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 1 to semaphore Right port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 0 to semaphore Left port writes 1 to semaphore I/O0–I/O17 Left I/O0–I/O17 Right 1 0 0 1 1 0 1 1 1 0 1 1 1 1 0 0 1 1 0 1 1 1 Semaphore-free Left Port has semaphore token No change. Right side has no write access to semaphore Right port obtains semaphore token No change. Left port has no write access to semaphore Left port obtains semaphore token Semaphore-free Right port has semaphore token Semaphore free Left port has semaphore token Semaphore-free Status Notes: 9. See Functional Description for specific highest memory locations by device. 10. If BUSYR=L, then no change. 11. If BUSYL=L, then no change. 12. See Functional Description for specific addresses by device. Document #: 38-06052 Rev. *H Page 7 of 19 CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV Maximum Ratings[13] (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential ............... –0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State..........................–0.5V to VCC + 0.5V DC Input Voltage[14]............................... –0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V Latch-up Current.................................................... > 200 mA Operating Range Range Commercial Industrial[15] Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 3.3V ± 300 mV 3.3V ± 300 mV Electrical Characteristics Over the Operating Range CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV -20 Parameter VOH VOL VIH VIL IOZ IIX ICC ISB1 ISB2 ISB3 ISB4 Output LOW Voltage Input HIGH Voltage Input LOW Voltage Output Leakage Current Input Leakage Current Operating Current (VCC = Max., IOUT = 0 mA) Outputs Disabled Standby Current (Both Ports TTL Level) CEL & CER ≥ VIH, f = fMAX Standby Current (One Port TTL Level) CEL | CER ≥ VIH, f = fMAX Com’l. Ind. [15] -25 Max. 0.4 Min. 2.4 0.4 2.0 0.8 10 10 –10 –10 115 135 30 40 65 75 10 10 60 70 0.8 10 10 165 185 40 50 95 105 500 500 80 90 Typ. Max. Unit V V V V μA μA mA mA mA mA mA mA μA μA mA mA Description Output HIGH Voltage (VCC=3.3V) Min. 2.4 2.0 –0.3[16] –10 –10 Typ. 120 35 75 10 70 175 45 110 500 95 Com’l. Ind.[15] Com’l. Ind. [15] Standby Current (Both Ports CMOS Level) Com’l. CEL & CER ≥ VCC−0.2V, f = 0 Ind.[15] Standby Current (One Port CMOS Level) CEL | CER ≥ VIH, f = fMAX[17] Com’l. Ind. [15] Capacitance[18] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max. 10 10 Unit pF pF Notes: 13. The Voltage on any input or I/O pin can not exceed the power pin during power-up. 14. Pulse width < 20 ns. 15. Industrial parts are available in CY7C026AV and CY7C036AV only. 16. VIL > –1.5V for pulse width less than 10ns. 17. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3. 18. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-06052 Rev. *H Page 8 of 19 CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV AC Test Loads and Waveforms 3.3V 3.3V R1 = 590Ω OUTPUT C = 30 pF R2 = 435Ω OUTPUT C = 30pF VTH = 1.4V RTH = 250Ω R1 = 590Ω OUTPUT C = 5 pF R2 = 435Ω (a) Normal Load (Load 1) (b) Thévenin Equivalent (Load 1) ALL INPUT PULSES 3.0V GND 10% ≤ 3 ns 90% 90% 10% ≤ 3 ns (c) Three-State Delay (Load 2) (Used for tLZ, tHZ, tHZWE, and tLZWE including scope and jig) Switching Characteristics Over the Operating Range [19] CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV -20 Parameter Read Cycle tRC tAA tOHA tACE[20] tDOE tLZOE[21, 22, 23] tHZOE[21, 22, 23] tLZCE[21, 22, 23] tHZCE[21, 22, 23] tPU[23] tPD[23] tABE[20] Write Cycle tWC tSCE[20] tAW tHA tSA[20] tPWE Write Cycle Time CE LOW to Write End Address Valid to Write End Address Hold From Write End Address Set-up to Write Start Write Pulse Width 20 15 15 0 0 15 25 20 20 0 0 20 ns ns ns ns ns ns Read Cycle Time Address to Data Valid Output Hold From Address Change CE LOW to Data Valid OE LOW to Data Valid OE Low to Low Z OE HIGH to High Z CE LOW to Low Z CE HIGH to High Z CE LOW to Power-Up CE HIGH to Power-Down Byte Enable Access Time 0 20 20 3 12 0 25 25 3 12 3 15 3 20 12 3 15 20 20 3 25 13 25 25 ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Min. -25 Max. Unit Notes: 19. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOI/IOH and 30-pF load capacitance. 20. To access RAM, CE = L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time. 21. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 22. Test conditions used are Load 3. 23. This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. Document #: 38-06052 Rev. *H Page 9 of 19 CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV Switching Characteristics Over the Operating Range (continued)[19] CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV -20 Parameter tSD tHD tHZWE[22, 23] tLZWE[22, 23] tWDD[24] tDDD[24] Busy Timing tBLA tBHA tBLC tBHC tPS tWB tWH tBDD[26] Interrupt Timing tINS tINR tSOP tSWRD tSPS tSAA [25] -25 Max. Min. 15 0 12 15 0 45 30 20 20 20 17 50 35 20 20 20 17 5 0 17 20 20 20 25 20 20 12 5 5 20 25 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Data Set-up to Write End Data Hold From Write End R/W LOW to High Z R/W HIGH to Low Z Write Pulse to Data Delay Write Data Valid to Read Data Valid BUSY LOW from Address Match BUSY HIGH from Address Mismatch BUSY LOW from CE LOW BUSY HIGH from CE HIGH Port Set-up for Priority R/W HIGH after BUSY (Slave) R/W HIGH after BUSY HIGH (Slave) BUSY HIGH to Data Valid [25] Min. 15 0 3 5 0 15 INT Set Time INT Reset Time SEM Flag Update Pulse (OE or SEM) SEM Flag Write to Read Time SEM Flag Contention Window SEM Address Access Time 10 5 5 Semaphore Timing Data Retention Mode The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV/ 036AV are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip Enable (CE) must be held HIGH during data retention, within VCC to VCC – 0.2V. 2. CE must be kept between VCC – 0.2V and 70% of VCC during the power-up and power-down transitions. 3. The RAM can begin operation >tRC after VCC reaches the minimum operating voltage (3.0V). Timing Data Retention Mode VCC 3.0V VCC > 2.0V 3.0V tRC V IH CE VCC to VCC – 0.2V Parameter ICCDR1 Test Conditions[27] @ VCCDR = 2V Max. 50 Unit μA Notes: 24. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 25. Test conditions used are Load 2. 26. tBDD is a calculated parameter and is the greater of tWDD – tPWE (actual) or tDDD – tSD (actual). 27. CE = VCC, Vin = GND to VCC, TA = 25°C. This parameter is guaranteed but not tested. Document #: 38-06052 Rev. *H Page 10 of 19 CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV Switching Waveforms Read Cycle No. 1 (Either Port Address Access)[28, 29, 30] tRC ADDRESS tOHA DATA OUT tAA DATA VALID tOHA PREVIOUS DATA VALID Read Cycle No. 2 (Either Port CE/OE Access)[28, 31, 32] CE and LB or UB OE tLZOE DATA OUT tLZCE tPU ICC CURRENT ISB tPD DATA VALID tACE tHZCE tDOE tHZOE Read Cycle No. 3 (Either Port)[28, 30, 31, 32] tRC ADDRESS tAA UB or LB tHZCE tLZCE tABE CE tACE tLZCE DATA OUT tHZCE tOHA Notes: 28. R/W is HIGH for read cycles. 29. Device is continuously selected CE = VIL and UB or LB = VIL. This waveform cannot be used for semaphore reads. 30. OE = VIL. 31. Address valid prior to or coincident with CE transition LOW. 32. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL. Document #: 38-06052 Rev. *H Page 11 of 19 CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV Switching Waveforms (continued) Write Cycle No. 1: R/W Controlled Timing[33, 34, 35, 36] tWC ADDRESS tHZOE [39] OE tAW CE [37, 38] tSA R/W tHZWE[39] DATA OUT NOTE 40 tPWE[36] tHA tLZWE NOTE 40 tSD tHD DATA IN Write Cycle No. 2: CE Controlled Timing[33, 34, 35, 41] tWC ADDRESS tAW CE [37, 38] tSA R/W tSCE tHA tSD DATA IN tHD Notes: 33. R/W must be HIGH during all address transitions. 34. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM and a LOW UB or LB. 35. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle. 36. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tPWE. 37. To access RAM, CE = VIL, SEM = VIH. 38. To access upper byte, CE = VIL, UB = VIL, SEM = VIH. To access lower byte, CE = VIL, LB = VIL, SEM = VIH. 39. Transition is measured ±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested. 40. During this period, the I/O pins are in the output state, and input signals must not be applied. 41. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state. Document #: 38-06052 Rev. *H Page 12 of 19 CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV Switching Waveforms (continued) Semaphore Read After Write Timing, Either Side[42] tSAA A 0–A 2 VALID ADRESS tAW SEM tSCE tSD I/O 0 tSA R/W tSWRD OE WRITE CYCLE tSOP READ CYCLE tDOE DATAIN VALID tPWE tHD DATAOUT VALID tHA tSOP VALID ADRESS tACE tOHA Timing Diagram of Semaphore Contention[43, 44, 45] A0L –A2L MATCH R/WL SEM L tSPS A 0R –A 2R MATCH R/WR SEM R Notes: 42. CE = HIGH for the duration of the above timing (both write and read cycle). 43. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH. 44. Semaphores are reset (available to both ports) at cycle start. 45. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable. Document #: 38-06052 Rev. *H Page 13 of 19 CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV Switching Waveforms (continued) Timing Diagram of Read with BUSY (M/S=HIGH)[46] tWC ADDRESSR R/WR MATCH tPWE tSD DATA INR tPS ADDRESSL MATCH tBLA BUSYL tDDD DATA OUTL tWDD VALID tHD tBHA tBDD VALID Write Timing with Busy Input (M/S=LOW) R/W tWB tPWE BUSY tWH Note: 46. CEL = CER = LOW. Document #: 38-06052 Rev. *H Page 14 of 19 CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV Switching Waveforms (continued) Busy Timing Diagram No.1 (CE Arbitration)[47] CELValid First: ADDRESS L,R CEL tPS CER tBLC BUSYR tBHC ADDRESS MATCH CER Valid First: ADDRESS L,R CER tPS CE L tBLC BUSY L tBHC ADDRESS MATCH Busy Timing Diagram No.2 (Address Arbitration)[47] Left Address Valid First: tRC or tWC ADDRESS L ADDRESS MATCH tPS ADDRESSR tBLA BUSY R tBHA ADDRESS MISMATCH Right Address Valid First: tRC or tWC ADDRESSR ADDRESS MATCH tPS ADDRESSL tBLA BUSY L tBHA ADDRESS MISMATCH Note: 47. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted. Document #: 38-06052 Rev. *H Page 15 of 19 CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV Switching Waveforms (continued) Interrupt Timing Diagrams Left Side Sets INTR : ADDRESSL CE L R/W L INT R tINS [49] tWC WRITE 1FFF (OR 1/3FFF) tHA[48] Right Side Clears INT R : ADDRESSR CE R tINR [49] R/WR OE R INTR tRC READ 7FFF (OR 1/3FFF) Right Side Sets INT L: tWC ADDRESSR CE R R/W R INT L tINS[49] WRITE 1FFE (OR 1/3FFE) tHA[48] Left Side Clears INT L: ADDRESSR CE L tINR[49] R/W L OE L INT L Notes: 48. tHA depends on which enable pin (CEL or R/WL) is deasserted first. 49. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last. tRC READ 7FFE OR 1/3FFE) Document #: 38-06052 Rev. *H Page 16 of 19 CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV Ordering Information 4K x16 3.3V Asynchronous Dual-Port SRAM Speed (ns) 15 20 Ordering Code CY7C024AV-15AI CY7C024AV-15AXI CY7C024AV-20AC CY7C024AV-20AXC CY7C024AV-20AI CY7C024AV-20AXI 25 CY7C024AV-25AC CY7C024AV-25AXC CY7C024AV-25AI CY7C024AV-25AXI 8K x16 3.3V Asynchronous Dual-Port SRAM Speed (ns) 20 Ordering Code CY7C025AV-20AC CY7C025AV-20AXC CY7C025AV-20AXI 25 CY7C025AV-25AC CY7C025AV-25AXC CY7C025AV-25AI CY7C025AV-25AXI 16K x16 3.3V Asynchronous Dual-Port SRAM Speed (ns) 20 Ordering Code CY7C026AV-20AC CY7C026AV-20AXC CY7C026AV-20AXI 25 CY7C026AV-25AC CY7C026AV-25AXC CY7C026AV-25AI CY7C026AV-25AXI 4K x18 3.3V Asynchronous Dual-Port SRAM Speed (ns) 20 25 Ordering Code CY7C0241AV-20AC CY7C0241AV-25AC Package Name A100 A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack Operating Range Commercial Commercial Package Name A100 A100 A100 A100 A100 A100 A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Lead-free Thin Quad Flat Pack 100-Pin Lead-free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Lead-free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Lead-free Thin Quad Flat Pack Industrial Industrial Commercial Operating Range Commercial Package Name A100 A100 A100 A100 A100 A100 A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Lead-free Thin Quad Flat Pack 100-Pin Lead-free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Lead-free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Lead-free Thin Quad Flat Pack Industrial Industrial Commercial Operating Range Commercial Package Name A100 A100 A100 A100 A100 A100 A100 A100 A100 A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Lead-free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Lead-free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Lead-free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Lead-free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Lead-free Thin Quad Flat Pack Industrial Commercial Industrial Commercial Operating Range Industrial 8K x18 3.3V Asynchronous Dual-Port SRAM Speed (ns) 20 25 Ordering Code CY7C0251AV-20AC CY7C0251AV-25AC Package Name A100 A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack Operating Range Commercial Commercial Document #: 38-06052 Rev. *H Page 17 of 19 CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV 16K x18 3.3V Asynchronous Dual-Port SRAM Speed (ns) 20 25 Ordering Code CY7C036AV-20AC CY7C036AV-25AC CY7C036AV-25AXC CY7C036AV-25AI Package Name A100 A100 A100 A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Lead-free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack Industrial Operating Range Commercial Commercial Package Diagram 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 100-Pin Lead (Pb)-free Thin Plastic Quad Flat Pack (TQFP) A100 51-85048-*B All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-06052 Rev. *H Page 18 of 19 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV Document History Page Document Title: CY7C024AV/CY7C025AV/CY7C026AV/CY7C0241AV/CY7C0251AV/CY7C036AV 3.3V 4K/8K/16K x 16/18 Dual Port Static RAM Document Number: 38-06052 REV. ** *A *B *C *D *E *F ECN NO. 110204 122302 128958 237622 241968 276451 279452 Issue Date 11/11/01 12/27/02 9/03/03 See ECN See ECN See ECN See ECN Orig. of Change SZV RBI JFU YDT WWZ SPN RUY Description of Change Change from Spec number: 38-00838 to 38-06052 Power-up requirements added to Maximum Ratings Information Added CY7C025AV-25AI to Ordering Information Removed cross information from features section Added CY7C024AV-25AI to Ordering Information Corrected x18 for 026AV to x16 Added lead (Pb)-free packaging information Corrected pin A113L to A13L on CY7C026AV pin list Added minimum VIL of 0.3V and note 16 Corrected CY7C024AC-25AXC to CY7C024AV-25AXC in Ordering Information Added to Part Ordering information: CY7C024AV-15AI, CY7C024AV-15AXI, CY7C024AV-20AI, CY7C024AV-20AXI, CY7C025AV-20AXI, CY7C026AV-20AXI *G *H 373580 380476 See ECN See ECN RUY PCX Document #: 38-06052 Rev. *H Page 19 of 19