CY7C028-15AXC

CY7C027/028 CY7C037/03832K/64K x 16/18 Dual-Port Static RAM CY7C027/028 CY7C037/038 32K/64K x 16/18 Dual-Port Static RAM Features ■ ■ ■ True dual-ported memory cells which allow simultaneous access of the same memory location ■ 32K x 16 organization (CY7C027) ■ 64K x 16 organization (CY7C028) ■ 32K x 18 organization (CY7C037) ■ 64K x 18 organization (CY7C038) ■ 0.35 micron CMOS for optimum speed and power [1] ■ High speed access: 12 , 15, and 20 ns ■ Low operating power ■ Active: ICC = 180 mA (typical) ■ Standby: ISB3 = 0.05 mA (typical) ■ Fully asynchronous operation ■ ■ ■ ■ ■ ■ ■ ■ ■ Automatic power down Expandable data bus to 32 and 36 bits or more using Master/Slave chip select when using more than one device On-chip arbitration logic Semaphores included to permit software handshaking between ports INT flags for port-to-port communication Separate upper-byte and lower-byte control Dual chip enables Pin select for Master or Slave Commercial and industrial temperature ranges Available in 100-pin TQFP Pb-free packages available Logic Block Diagram R/WL UBL R/WR UBR CE0L CE1L CE0R CE1R CEL CER LBL LBR OEL OER [2] I/O8/9L–I/O15/17L [3] 8/9 8/9 8/9 8/9 I/O Control I/O0L–I/O7/8L [4] A0L–A14/15L [4] 15/16 Address Decode I/O Control 15/16 [3] I/O0L–I/O7/8R Address Decode True Dual-Ported RAM Array [2] I/O8/9L–I/O15/17R 15/16 [4] A0R–A14/15R 15/16 A0L–A14/15L CEL OEL R/WL SEML [4] A0R–A14/15R CER OER R/WR SEMR Interrupt Semaphore Arbitration [5] BUSYL[5] INTL UBL LBL M/S BUSYR INTR UBR LBR Notes 1. See page 6 for Load Conditions. 2. I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices. 3. I/O0–I/O7 for x16 devices; I/O0–I/O8 for x18 devices. 4. A0–A14 for 32K; A0–A15 for 64K devices. 5. BUSY is an output in master mode and an input in slave mode. Cypress Semiconductor Corporation Document #: 38-06042 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised December 10, 2008 [+] Feedback CY7C027/028 CY7C037/038 Functional Description Each port has independent control pins: dual chip enables (CE0 and CE1), read or write enable (R/W), and output enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being accessed by the other port. The interrupt flag (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power down feature is controlled independently on each port by the chip enable pins. The CY7C027/028 and CY7C037/038 are low power CMOS 32K, 64K x 16/18 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be used as standalone 16 and 18-bit dual-port static RAMs or multiple devices can be combined to function as a 32/36-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 32/36-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor and multiprocessor designs, communications status buffering, and dual-port video/graphics memory. The CY7C027/028 and CY7C037/038 are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages. Pin Configurations A8R A7R A6R A5R A4R A3R A1R A2R INTR A0R BUSYR M/S GND INTL BUSYL A0L NC A2L A1L A3L A4L A5L A6L A7L A8L Figure 1. 100-Pin TQFP (Top View) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A9L 1 75 A9R A10L 2 74 A10R A11L 3 73 A11R A12L 4 72 A12R A13L 5 71 A13R A14L 6 70 A14R [6] A15L 7 69 A15R [6] NC 8 68 NC NC 9 67 NC LBL 10 66 LBR UBL 11 65 UBR CE0L 12 64 CE0R CE1L 13 SEML 14 CY7C028 (64K x 16) CY7C027 (32K x 16) 63 CE1R 62 SEMR GND VCC 15 61 R/WL 16 60 R/WR OEL 17 59 OER GND 18 58 GND GND 19 57 GND I/O15L 20 56 I/O15R I/O14L 21 55 I/O14R I/O13L 22 54 I/O13R I/O12L 23 53 I/O12R I/O11L 24 52 I/O11R I/O10L 25 51 I/O10R NC I/O9R I/O8R I/O7R VCC I/O6R I/O5R I/O4R I/O3R I/O2R I/01R GND I/O0R I/O0L I/O1L GND I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L VCC I/O8L I/O9L 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note 6. This pin is NC for CY7C027. Document #: 38-06042 Rev. *D Page 2 of 19 [+] Feedback CY7C027/028 CY7C037/038 Pin Configurations (continued) A7R A6R A5R A4R A3R A2R A1R A0R INTR M/S BUSYR VCC GND GND INTL BUSYL A1L A0L A2L A3L A4L A5L A6L A7L A8L Figure 2. 100-Pin TQFP (Top View) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A9L 1 75 A8R A10L 2 74 A9R A11L 3 73 A10R A12L 4 72 A11R A13L 5 71 A12R A14L 6 70 A13R [7]A15L 7 69 A14R LBL 8 68 A15R [7] LBR UBL 9 67 CE0L 10 66 UBR CE1L 11 65 CE0R SEML 12 64 CE1R R/WL 13 OEL 14 CY7C038 (64K x 18) CY7C037 (32K x 18) 63 SEMR 62 R/WR GND VCC 15 61 GND 16 60 OER I/O17L 17 59 GND I/O16L 18 58 I/O17R GND 19 57 GND I/O15L 20 56 I/O16R I/O14L 21 55 I/O15R I/O13L 22 54 I/O14R I/O12L 23 53 I/O13R I/O11L 24 52 I/O12R I/O10L 25 51 I/O11R I/O10R I/O9R I/O8R I/O7R VCC I/O6R I/O5R I/O4R I/O3R I/O2R I/01R I/O0R GND I/O0L GND I/O1L I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L VCC I/O8L I/O9L 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Selection Guide CY7C027/028 CY7C037/038 -12[1] CY7C027/028 CY7C037/038 -15 CY7C027/028 CY7C037/038 -20 Unit Maximum Access Time 12 15 20 ns Typical Operating Current 195 190 180 mA Typical Standby Current for ISB1 (Both ports TTL level) 55 50 45 mA 0.05 0.05 0.05 mA Parameter Typical Standby Current for ISB3 (Both ports CMOS level) Note 7. This pin is NC for CY7C037. Document #: 38-06042 Rev. *D Page 3 of 19 [+] Feedback CY7C027/028 CY7C037/038 Pin Definitions Left Port Right Port Description CE0L, CE1L CE0R, CE1R Chip Enable (CE is LOW when CE0 ≤ VIL and CE1 ≥ VIH) R/WL R/WR Read/Write Enable OEL OER Output Enable A0L–A15L A0R–A15R Address (A0–A14 for 32K; A0–A15 for 64K devices) I/O0L–I/O17L I/O0R–I/O17R Data Bus Input/Output (I/O0–I/O15 for x16 devices; I/O0–I/O17 for x18) SEML SEMR Semaphore Enable UBL UBR Upper Byte Select (I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices) LBL LBR Lower Byte Select (I/O0–I/O7 for x16 devices; I/O0–I/O8 for x18 devices) INTL INTR Interrupt Flag BUSYL BUSYR Busy Flag M/S Master or Slave Select VCC Power GND Ground NC No Connect Document #: 38-06042 Rev. *D Page 4 of 19 [+] Feedback CY7C027/028 CY7C037/038 Input Voltage[9] ...............................................–0.5V to +7.0V Maximum Ratings[8] Output Current into Outputs (LOW)............................. 20 mA Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Static Discharge Voltage........................................... >1100V Storage Temperature ................................. –65°C to +150°C Latch-Up Current .................................................... >200 mA Ambient Temperature with Power Applied ............................................ –55°C to +125°C Operating Range Supply Voltage to Ground Potential................–0.3V to +7.0V Ambient Temperature Range DC Voltage Applied to Outputs in High Z State .............................................–0.5V to +7.0DC VCC Commercial 0°C to +70°C 5V ± 10% Industrial[10] –40°C to +85°C 5V ± 10% Electrical Characteristics Over the Operating Range CY7C027/028 CY7C037/038 Symbol Parameter -12[1] Min VOH Output HIGH Voltage (VCC = Min, IOH = –4.0 mA) VOL Output LOW Voltage (VCC = Min, IOH = +4.0 mA) VIH Input HIGH Voltage VIL Input LOW Voltage IOZ Output Leakage Current ICC Operating Current (VCC=Max, IOUT=0 mA) Outputs Disabled Ind.[10] Standby Current (Both Ports TTL Level) CEL & CER ≥ VIH, f = fMAX Ind.[10] ISB1 Typ -15 Max 2.4 Min Typ 0.4 Com’l. 10 195 55 325 75 Typ Max V 0.4 2.2 –10 Min 2.4 0.4 V 0.8 V 2.2 0.8 Com’l. Max 2.4 2.2 Unit -20 V 0.8 –10 10 190 50 280 70 10 μA 180 265 mA 305 290 mA 45 65 mA 60 80 mA –10 ISB2 Standby Current (One Port TTL Com’l. Level) CEL | CER ≥ VIH, f = fMAX Ind.[10] 125 205 120 180 110 160 mA 125 175 mA ISB3 Com’l. Standby Current (Both Ports CMOS Level) CEL & CER ≥ VCC Ind.[10] – 0.2V, f = 0 0.05 0.5 0.05 0.5 0.05 0.5 mA 0.05 0.5 mA Standby Current (One Port CMOS Level) CEL | CER ≥ VIH, f = fMAX[11] 115 100 140 mA 115 155 mA ISB4 Com’l. Ind.[10] 185 110 160 Notes 8. The voltage on any input or I/O pin cannot exceed the power pin during power up. 9. Pulse width < 20 ns. 10. Industrial parts are available in CY7C028 and CY7C038 only. 11. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3. Document #: 38-06042 Rev. *D Page 5 of 19 [+] Feedback CY7C027/028 CY7C037/038 Capacitance[12] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max Unit 10 pF 10 pF Figure 3. AC Test Loads and Waveforms 5V 5V R1 = 893Ω RTH = 250Ω OUTPUT OUTPUT R1 = 893Ω OUTPUT C = 30 pF C = 30 pF R2 = 347Ω C = 5 pF R2 = 347Ω VTH = 1.4V (a) Normal Load (Load 1) (c) Three-State Delay (Load 2) (Used for tCKLZ, tOLZ, & tOHZ including scope and jig) (b) Thévenin Equivalent (Load 1) ALL INPUT PULSES 3.0V GND 90% 10% 90% 10% ≤ 3 ns ≤ 3 ns AC Test Loads (Applicable to -12 only)[13] 1.00 0.90 R = 50Ω C VTH = 1.4V (a) Load 1 (-12 only) Δ (ns) for all -12 access times Z0 = 50Ω OUTPUT 0.80 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0.00 0 5 10 15 20 25 30 Capacitance (pF) (b) Load Derating Curve Notes 12. Tested initially and after any design or process changes that may affect these parameters. 13. Test conditions: C = 0 pF. Document #: 38-06042 Rev. *D Page 6 of 19 [+] Feedback CY7C027/028 CY7C037/038 Switching Characteristics Over the Operating Range[14] CY7C027/028 CY7C037/038 Parameter Description -12[1] Min -15 Max Min Unit -20 Max Min Max Read Cycle tRC Read Cycle Time tAA Address to Data Valid 12 tOHA Output Hold From Address Change tACE[15] CE LOW to Data Valid 12 15 20 ns tDOE OE LOW to Data Valid 8 10 12 ns tLZOE[16, 17, 18] tHZOE[16, 17, 18] tLZCE[16, 17, 18] tHZCE[16, 17, 18] tPU[18] tPD[18] tABE[15] OE LOW to Low Z 12 ns 12 ns 3 3 CE LOW to Power Up 3 0 ns 3 10 0 ns ns 3 10 10 ns 20 3 3 10 CE HIGH to High Z 20 15 3 3 OE HIGH to High Z CE LOW to Low Z 15 12 ns 0 ns CE HIGH to Power Down 12 15 20 ns Byte Enable Access Time 12 15 20 ns Write Cycle tWC Write Cycle Time 12 15 20 ns tSCE[15] CE LOW to Write End 10 12 15 ns tAW Address Valid to Write End 10 12 15 ns tHA Address Hold From Write End 0 0 0 ns tSA[15] Address Setup to Write Start 0 0 0 ns tPWE Write Pulse Width 10 12 15 ns tSD Data Setup to Write End 10 10 15 ns tHD Data Hold From Write End 0 0 0 ns tHZWE[17, 18] tLZWE[17, 18] tWDD[19] tDDD[19] R/W LOW to High Z R/W HIGH to Low Z 10 3 10 3 12 3 ns ns Write Pulse to Data Delay 25 30 45 ns Write Data Valid to Read Data Valid 20 25 30 ns Busy Timing[20] tBLA BUSY LOW from Address Match 12 15 20 ns tBHA BUSY HIGH from Address Mismatch 12 15 20 ns tBLC BUSY LOW from CE LOW 12 15 20 ns tBHC BUSY HIGH from CE HIGH 12 15 17 ns tPS Port Setup for Priority 5 5 5 ns tWB R/W HIGH after BUSY (Slave) 0 0 0 ns tWH R/W HIGH after BUSY HIGH (Slave) 11 tBDD[21] BUSY HIGH to Data Valid 13 12 15 15 ns 20 ns Notes 14. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOI/IOH and 30 pF load capacitance. 15. To access RAM, CE=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire tSCE time. 16. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 17. Test conditions used are Load 2. 18. This parameter is guaranteed by design, but it is not production tested. 19. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Figure 11. 20. Test conditions used are Load 1. Document #: 38-06042 Rev. *D Page 7 of 19 [+] Feedback CY7C027/028 CY7C037/038 Switching Characteristics Over the Operating Range[14] (continued) CY7C027/028 CY7C037/038 Parameter Description -12[1] Min INTERRUPT TIMING -15 Max Min Unit -20 Max Min Max [20] tINS INT Set Time 12 15 20 ns tINR INT Reset Time 12 15 20 ns SEMAPHORE TIMING tSOP SEM Flag Update Pulse (OE or SEM) 10 10 10 ns tSWRD SEM Flag Write to Read Time 5 5 5 ns tSPS SEM Flag Contention Window 5 5 5 ns tSAA SEM Address Access Time Data Retention Mode The CY7C027/028 and CY7C037/038 are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip enable (CE) must be held HIGH during data retention, within VCC to VCC – 0.2V. 2. CE must be kept between VCC – 0.2V and 70% of VCC during the power up and power down transitions. 3. The RAM can begin operation >tRC after VCC reaches the minimum operating voltage (4.5V). 12 15 20 ns Timing Data Retention Mode VCC 4.5V VCC > 2.0V 4.5V VCC to VCC – 0.2V CE Parameter ICCDR1 Test Conditions[22] At VCCDR = 2V tRC V IH Max Unit 1.5 mA Notes 21. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual). 22. CE = VCC, Vin = GND to VCC, TA = 25°C. This parameter is guaranteed but not tested. Document #: 38-06042 Rev. *D Page 8 of 19 [+] Feedback CY7C027/028 CY7C037/038 Switching Waveforms Figure 4. Read Cycle No. 1 (Either Port Address Access)[23 ,24, 25] tRC ADDRESS tOHA DATA OUT tAA tOHA PREVIOUS DATA VALID DATA VALID Figure 5. Read Cycle No. 2 (Either Port CE/OE Access)[23, 26, 27] tACE CE and LB or UB tHZCE tDOE OE tHZOE tLZOE DATA VALID DATA OUT tLZCE tPU tPD ICC CURRENT ISB Figure 6. Read Cycle No. 3 (Either Port)[23, 25, 26, 27] tRC ADDRESS tAA tOHA UB or LB tHZCE tLZCE tABE CE tHZCE tACE tLZCE DATA OUT Notes 23. R/W is HIGH for read cycles. 24. Device is continuously selected CE = VIL and UB or LB = VIL. This waveform cannot be used for semaphore reads. 25. OE = VIL. 26. Address valid prior to or coincident with CE transition LOW. 27. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL. Document #: 38-06042 Rev. *D Page 9 of 19 [+] Feedback CY7C027/028 CY7C037/038 Switching Waveforms (continued) Figure 7. Write Cycle No. 1: R/W Controlled Timing[28, 29, 30, 31] tWC ADDRESS tHZOE [34] OE tAW CE [32,33] tPWE[31] tSA tHA R/W tHZWE[34] DATA OUT tLZWE NOTE 35 NOTE 35 tSD tHD DATA IN Figure 8. Write Cycle No. 2: CE Controlled Timing[28, 29, 30, 34, 35] tWC ADDRESS tAW CE [32,33] tSA tSCE tHA R/W tSD tHD DATA IN Notes 28. R/W must be HIGH during all address transitions. 29. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM and a LOW UB or LB. 30. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle. 31. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tPWE. 32. To access RAM, CE = VIL, SEM = VIH. 33. To access upper byte, CE = VIL, UB = VIL, SEM = VIH. To access lower byte, CE = VIL, LB = VIL, SEM = VIH. 34. Transition is measured ±500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100% tested. 35. During this period, the I/O pins are in the output state, and input signals must not be applied. 36. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state. Document #: 38-06042 Rev. *D Page 10 of 19 [+] Feedback CY7C027/028 CY7C037/038 Switching Waveforms (continued) Figure 9. Semaphore Read After Write Timing, Either Side[37] tSAA A 0–A 2 VALID ADRESS VALID ADRESS tAW tACE tHA SEM tOHA tSCE tSOP tSD I/O0 DATAIN VALID tSA tPWE DATAOUT VALID tHD R/W tSWRD tDOE tSOP OE WRITE CYCLE READ CYCLE Figure 10. Timing Diagram of Semaphore Contention[38, 39, 40] A0L –A2L MATCH R/WL SEM L tSPS A 0R –A 2R MATCH R/WR SEM R Notes 37. CE = HIGH for the duration of the above timing (both write and read cycle). 38. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH. 39. Semaphores are reset (available to both ports) at cycle start. 40. If tSPS is violated, the semaphore is definitely obtained by one side or the other, but which side gets the semaphore is unpredictable. Document #: 38-06042 Rev. *D Page 11 of 19 [+] Feedback CY7C027/028 CY7C037/038 Switching Waveforms (continued) Figure 11. Timing Diagram of Read with BUSY (M/S=HIGH)[41] tWC ADDRESSR MATCH tPWE R/WR tSD DATA INR tHD VALID tPS ADDRESSL MATCH tBLA tBHA BUSYL tBDD tDDD DATA OUTL VALID tWDD Figure 12. Write Timing with Busy Input (M/S=LOW) tPWE R/W BUSY tWB tWH Note 41. CEL = CER = LOW. Document #: 38-06042 Rev. *D Page 12 of 19 [+] Feedback CY7C027/028 CY7C037/038 Switching Waveforms (continued) Figure 13. Busy Timing Diagram No.1 (CE Arbitration)[42] CELValid First: ADDRESS L,R ADDRESS MATCH CEL tPS CER tBLC tBHC BUSYR CER Valid First: ADDRESS L,R ADDRESS MATCH CER tPS CE L tBLC tBHC BUSY L Figure 14. Busy Timing Diagram No. 2 (Address Arbitration)[42] Left Address Valid First: tRC or tWC ADDRESS L ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESSR tBLA tBHA BUSY R Right Address Valid First: tRC or tWC ADDRESSR ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESSL tBLA tBHA BUSY L Note 42. If tPS is violated, the busy signal is asserted on one side or the other, but there is no guarantee to which side BUSY is asserted. Document #: 38-06042 Rev. *D Page 13 of 19 [+] Feedback CY7C027/028 CY7C037/038 Switching Waveforms (continued) Figure 15. Interrupt Timing Diagrams Left Side Sets INTR: ADDRESSL tWC WRITE 7FFF (FFFF for CY7C028/38) tHA[43] CE L R/W L INT R tINS [44] Right Side Clears INTR: tRC READ 7FFF (FFFF for CY7C028/38) ADDRESSR CE R tINR [44] R/WR OE R INTR Right Side Sets INT L: tWC ADDRESSR WRITE 7FFE (FFFE for CY7C028/38) tHA[43] CE R R/W R INT L [44] tINS Left Side Clears INTL: tRC READ 7FFE (FFFE for CY7C028/38) ADDRESSR CE L tINR[44] R/W L OE L INT L Notes 43. tHA depends on which enable pin (CEL or R/WL) is deasserted first. 44. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last. Document #: 38-06042 Rev. *D Page 14 of 19 [+] Feedback CY7C027/028 CY7C037/038 Architecture Busy The CY7C027/028 and CY7C037/038 consist of an array of 32K and 64K words of 16 and 18 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. Two interrupt (INT) pins can be used for port-to-port communication. Two semaphore (SEM) control pins are used for allocating shared resources. With the M/S pin, the devices can function as a master (BUSY pins are outputs) or as a slave (BUSY pins are inputs). The devices also have an automatic power down feature controlled by CE. Each port is provided with its own output enable control (OE), which allows data to be read from the device. The CY7C027/028 and CY7C037/038 provide on-chip arbitration to resolve simultaneous memory location access (contention). If both ports’ CEs are asserted and an address match occurs within tPS of each other, the busy logic determines which port has access. If tPS is violated, one port definitely gains permission to the location, but it is not predictable which port gets that permission. BUSY is asserted tBLA after an address match or tBLC after CE is taken LOW. Functional Description Write Operation Data must be set up for a duration of tSD before the rising edge of R/W to guarantee a valid write. A write operation is controlled by either the R/W pin (see Figure 7) or the CE pin (see Figure 8). Required inputs for non-contention operations are summarized in Table 1. If a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is read on the output; otherwise the data read is not deterministic. Data is valid on the port tDDD after the data is presented on the other port. Read Operation When reading the device, the user must assert both the OE and CE pins. Data is available tACE after CE or tDOE after OE is asserted. If the user wishes to access a semaphore flag, then the SEM pin must be asserted instead of the CE pin, and OE must also be asserted. Interrupts The upper two memory locations may be used for message passing. The highest memory location (7FFF for the CY7C027/37, FFFF for the CY7C028/38) is the mailbox for the right port and the second-highest memory location (7FFE for the CY7C027/37, FFFE for the CY7C028/38) is the mailbox for the left port. When one port writes to the other port’s mailbox, an interrupt is generated to the owner. The interrupt is reset when the owner reads the contents of the mailbox. The message is user defined. Each port can read the other port’s mailbox without resetting the interrupt. The active state of the busy signal (to a port) prevents the port from setting the interrupt to the winning port. Also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. If an application does not require message passing, do not connect the interrupt pin to the processor’s interrupt request input pin. The operation of the interrupts and their interaction with Busy is summarized in Table 2. Document #: 38-06042 Rev. *D Master/Slave A M/S pin is provided to expand the word width by configuring the device as either a master or a slave. The BUSY output of the master is connected to the BUSY input of the slave. This allows the device to interface to a master device with no external components. Writing to slave devices must be delayed until after the BUSY input has settled (tBLC or tBLA), otherwise, the slave chip may begin a write cycle during a contention situation. When tied HIGH, the M/S pin allows the device to be used as a master and, therefore, the BUSY line is an output. BUSY can then be used to send the arbitration outcome to a slave. Semaphore Operation The CY7C027/028 and CY7C037/038 provide eight semaphore latches, which are separate from the dual-port memory locations. Semaphores are used to reserve resources that are shared between the two ports.The state of the semaphore indicates that a resource is in use. For example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. The left port then verifies its success in setting the latch by reading it. After writing to the semaphore, SEM or OE must be deasserted for tSOP before attempting to read the semaphore. The semaphore value is available tSWRD + tDOE after the rising edge of the semaphore write. If the left port was successful (reads a zero), it assumes control of the shared resource, otherwise (reads a one) it assumes the right port has control and continues to poll the semaphore. When the right side has relinquished control of the semaphore (by writing a one), the left side succeeds in gaining control of the semaphore. If the left side no longer requires the semaphore, a one is written to cancel its request. Semaphores are accessed by asserting SEM LOW. The SEM pin functions as a chip select for the semaphore latches (CE must remain HIGH during SEM LOW). A0–2 represents the semaphore address. OE and R/W are used in the same manner as a normal memory access. When writing or reading a semaphore, the other address pins have no effect. When writing to the semaphore, only I/O0 is used. If a zero is written to the left port of an available semaphore, a one appears at the same semaphore address on the right port. That semaphore can now only be modified by the side showing zero (the left port in this case). If the left port now relinquishes control by writing a one to the semaphore, the semaphore is set to one for both sides. However, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. Table 3 shows sample semaphore operations. When reading a semaphore, all sixteen/eighteen data lines output the semaphore value. The read value is latched in an Page 15 of 19 [+] Feedback CY7C027/028 CY7C037/038 output register to prevent the semaphore from changing state during a write from the other port. If both ports attempt to access the semaphore within tSPS of each other, the semaphore is definitely obtained by one side or the other, but there is no guarantee which side controls the semaphore. Table 1. Non-Contending Read/Write Inputs Outputs CE R/W OE UB LB SEM H X X X X H I/O9–I/O17 I/O0–I/O8 X X X H H H High Z High Z Deselected: Power Down L L X L H H Data In High Z Write to Upper Byte Only L L X H L H High Z Data In Write to Lower Byte Only L L X L L H Data In Data In Write to Both Bytes L H L L H H Data Out High Z Read Upper Byte Only L H L H L H High Z Data Out Read Lower Byte Only High Z Operation High Z Deselected: Power Down L H L L L H Data Out Data Out Read Both Bytes X X H X X X High Z High Z Outputs Disabled H H L X X L Data Out Data Out Read Data in Semaphore Flag X H L H H L Data Out Data Out Read Data in Semaphore Flag H X X X L Data In Data In Write DIN0 into Semaphore Flag X X H H L Data In Data In Write DIN0 into Semaphore Flag L X X L X L Not Allowed L X X X L L Not Allowed Table 2. Interrupt Operation Example (assumes BUSYL = BUSYR = HIGH)[23] Left Port Function Right Port R/WL CEL OEL A0L–14L INTL R/WR CER OER A0R–14R INTR Set Right INTR Flag L L X 7FFF X X X X X L[25] Reset Right INTR Flag X X X X X X L L 7FFF H[24] Set Left INTL Flag X X X X L[24] L L X 7FFE X Reset Left INTL Flag X L L 7FFE H[25] X X X X X Table 3. Semaphore Operation Example Function I/O0–I/O17 Left I/O0–I/O17 Right Status No action 1 1 Semaphore free Left port writes 0 to semaphore 0 1 Left port has semaphore token Right port writes 0 to semaphore 0 1 No change. Right side has no write access to semaphore Left port writes 1 to semaphore 1 0 Right port obtains semaphore token Left port writes 0 to semaphore 1 0 No change. Left port has no write access to semaphore Right port writes 1 to semaphore 0 1 Left port obtains semaphore token Left port writes 1 to semaphore 1 1 Semaphore free Right port writes 0 to semaphore 1 0 Right port has semaphore token Right port writes 1 to semaphore 1 1 Semaphore free Left port writes 0 to semaphore 0 1 Left port has semaphore token Left port writes 1 to semaphore 1 1 Semaphore free Notes 23. A0L–15L and A0R–15R, FFFF/FFFE for the CY7C028/038. 24. If BUSYR = L, then no change. 25. If BUSYL = L, then no change. Document #: 38-06042 Rev. *D Page 16 of 19 [+] Feedback CY7C027/028 CY7C037/038 Ordering Information 32K x16 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 12[1] CY7C027-12AC A100 100-Pin Thin Quad Flat Pack Commercial 15 CY7C027-15AC A100 100-Pin Thin Quad Flat Pack Commercial 20 CY7C027-15AXI A100 100-Pin Pb-Free Thin Quad Flat Pack Industrial CY7C027-20AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C027-20AXC A100 100-Pin Pb-Free Thin Quad Flat Pack Commercial 64K x16 Asynchronous Dual-Port SRAM Speed (ns) 12[1] 15 20 Ordering Code Package Name CY7C028-12AC A100 Package Type 100-Pin Thin Quad Flat Pack Operating Range Commercial CY7C028-12AXC A100 100-Pin Pb-Free Thin Quad Flat Pack Commercial CY7C028-15AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C028-15AXC A100 100-Pin Pb-Free Thin Quad Flat Pack Commercial CY7C028-15AI A100 100-Pin Thin Quad Flat Pack Industrial CY7C028-15AXI A100 100-Pin Pb-Free Thin Quad Flat Pack Industrial CY7C028-20AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C028-20AI A100 100-Pin Thin Quad Flat Pack Industrial 32K x18 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 12[1] CY7C037-12AC A100 100-Pin Thin Quad Flat Pack Commercial 15 CY7C037-15AC A100 100-Pin Thin Quad Flat Pack Commercial 20 CY7C037-20AC A100 100-Pin Thin Quad Flat Pack Commercial 64K x18 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 12[1] CY7C038-12AC A100 100-Pin Thin Quad Flat Pack Commercial 15 CY7C038-15AC A100 100-Pin Thin Quad Flat Pack Commercial 20 CY7C038-20AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C038-20AI A100 100-Pin Thin Quad Flat Pack Industrial Document #: 38-06042 Rev. *D Page 17 of 19 [+] Feedback CY7C027/028 CY7C037/038 Package Diagram Figure 16. 100-Pin Pb-Free Thin Plastic Quad Flat Pack (TQFP) A100 51-85048-*C Document #: 38-06042 Rev. *D Page 18 of 19 [+] Feedback CY7C027/028 CY7C037/038 Document History Page Document Title: CY7C027/028, CY7C037/038 32K/64K x 16/18 Dual-Port Static RAM Document Number: 38-06042 Rev. ECN No. Orig. of Change Submission Date ** 110190 SZV 09/29/01 Description of Change Change from Spec number: 38-00666 to 38-06042 *A 122292 RBI 12/27/02 Power up requirements added to Maximum Ratings Information *B 236765 YDT 6/23/04 Removed cross information from features section *C 377454 PCX See ECN Added Pb-Free Logo Added Pb-Free parts to ordering information: CY7C027-20AXC, CY7C028-12AXC, CY7C028-15AXC, CY7C028-15AI, CY7C028-15AXI *D 2623540 VKN/PYRS 12/17/08 Added CY7C027-15AXI in the Ordering information table Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. 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Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-06042 Rev. *D Revised December 10, 2008 Page 19 of 19 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback