CY7C027V/027AV/028V/028AV
CY7C037AV/038V
3.3 V, 32K/64K × 16/18 Dual-Port
Static RAM
3.3 V, 32K/64K × 16/18 Dual-Port Static RAM
Features
Functional Description
True dual-ported memory cells which allow simultaneous
access of the same memory location
[1]
■ 32K × 16 organization (CY7C027V/027AV )
[1]
■ 64K × 16 organization (CY7C028V/028AV )
■ 32K × 18 organization (CY7C037AV)
■ 64K × 18 organization (CY7C038V)
■ 0.35 micron Complementary metal oxide semiconductor
(CMOS) for optimum speed and power
■ High speed access: 15, 20, and 25 ns
■ Low operating power
■ Active: ICC = 115 mA (typical)
■ Standby: ISB3 = 10 A (typical)
■ Fully asynchronous operation
■ Automatic power-down
■ Expandable data bus to 32/36 bits or more using Master/Slave
chip select when using more than one device
■ On-chip arbitration logic
■ Semaphores included to permit software handshaking
between ports
■ INT flag for port-to-port communication
■ Separate upper-byte and lower-byte control
■ Dual chip enables
■ Pin select for Master or Slave
■ Commercial and Industrial temperature ranges
■ 100-pin Pb-free Thin quad plastic flatpack (TQFP) and 100-pin
TQFP
The CY7C027V/027AV/028V/028AV and CY7037AV/038V are
low power CMOS 32K, 64K × 16/18 dual-port static RAMs.
Various arbitration schemes are included on the devices to
handle situations when multiple processors access the same
piece of data. Two ports are provided, permitting independent,
asynchronous access for reads and writes to any location in
memory. The devices can be utilized as stand-alone 16/18-bit
dual-port static RAMs or multiple devices can be combined to
function as a 32/36-bit or wider master/slave dual-port static
RAM. An M/S pin is provided for implementing 32/36-bit or wider
memory applications without the need for separate master and
slave devices or additional discrete logic. Application areas
include interprocessor/multiprocessor designs, communications
status buffering, and dual-port video/graphics memory.
■
Each port has independent control pins: Chip Enable (CE), Read
or Write Enable (R/W), and Output Enable (OE). Two flags are
provided on each port (BUSY and INT). BUSY signals that the port is
trying to access the same location currently being accessed by the other
port. The interrupt flag (INT) permits communication between ports or
systems by means of a mail box. The semaphores are used to pass a
flag, or token, from one port to the other to indicate that a shared
resource is in use. The semaphore logic is comprised of eight shared
latches. Only one side can control the latch (semaphore) at any time.
Control of a semaphore indicates that a shared resource is in use. An
automatic power down feature is controlled independently on each port
by a chip select (CE) pin.
The CY7C027V/027AV/028V/028AV and CY7037AV/038V are
available in 100-pin Thin Quad Plastic Flatpacks (TQFP).
For a complete list of related documentation, click here.
Selection Guide
-15
-20
-25
Unit
Maximum access time
Parameter
15
20
25
ns
Typical operating current
125
120
115
mA
Typical standby current for ISB1 (Both ports TTL level)
35
35
30
mA
Typical standby current for ISB3 (Both ports CMOS level)
10
10
10
A
Note
1. CY7C027V, and CY7C027AV are functionally identical. CY7C028V and CY7C028AV are functionally identical.
Cypress Semiconductor Corporation
Document Number: 38-06078 Rev. *J
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 24, 2018
CY7C027V/027AV/028V/028AV
CY7C037AV/038V
Logic Block Diagram
R/WL
UBL
R/WR
UBR
CE0L
CE1L
CEL
CE0R
CE1R
CER
LBL
LBR
OEL
OER
[2]
I/O8/9L–I/O15/17L
[3]
8/9
8/9
8/9
8/9
I/O
Control
I/O0L–I/O7/8L
[4]
A0L–A14/15L
[4]
15/16
Address
Decode
True Dual-Ported
RAM Array
15/16
A0L–A14/15L
CEL
OEL
R/WL
SEML
BUSYL
INTL
UBL
LBL
I/O
Control
[2]
I/O8/9L–I/O15/17R
[3]
I/O0L–I/O7/8R
Address
Decode
15/16
[4]
A0R–A14/15R
15/16
Interrupt
Semaphore
Arbitration
[5]
[4]
A0R–A14/15R
CER
OER
R/WR
SEMR
[5]
M/S
BUSYR
INTR
UBR
LBR
Notes
2. I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices.
3. I/O0–I/O7 for x16 devices; I/O0–I/O8 for x18 devices.
4. A0–A14 for 32K; A0–A15 for 64K devices.
5. BUSY is an output in master mode and an input in slave mode.
Document Number: 38-06078 Rev. *J
Page 2 of 26
CY7C027V/027AV/028V/028AV
CY7C037AV/038V
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 6
Architecture ...................................................................... 6
Functional Overview ........................................................ 6
Write Operation ........................................................... 6
Read Operation ........................................................... 6
Interrupts ..................................................................... 6
Busy ............................................................................ 6
Master/Slave ............................................................... 7
Semaphore Operation ................................................. 7
Maximum Ratings ............................................................. 8
Operating Range ............................................................... 8
Electrical Characteristics ................................................. 8
Capacitance ...................................................................... 8
AC Test Loads and Waveforms ....................................... 9
Data Retention Mode ........................................................ 9
Timing ................................................................................ 9
Switching Characteristics .............................................. 10
Switching Waveforms .................................................... 12
Non-Contending Read/Write .......................................... 18
Document Number: 38-06078 Rev. *J
Interrupt Operation Example ......................................... 18
Semaphore Operation Example .................................... 19
Ordering Information ...................................................... 20
32K × 16 3.3 V Asynchronous Dual-Port SRAM ....... 20
64K × 16 3.3 V Asynchronous Dual-Port SRAM ....... 20
32K × 18 3.3 V Asynchronous Dual-Port SRAM ....... 20
64K × 18 3.3 V Asynchronous Dual-Port SRAM ....... 20
Ordering Code Definitions ......................................... 21
Package Diagram ............................................................ 22
Acronyms ........................................................................ 23
Document Conventions ................................................. 23
Units of Measure ....................................................... 23
Document History Page ................................................. 24
Sales, Solutions, and Legal Information ...................... 26
Worldwide Sales and Design Support ....................... 26
Products .................................................................... 26
PSoC® Solutions ...................................................... 26
Cypress Developer Community ................................. 26
Technical Support ..................................................... 26
Page 3 of 26
CY7C027V/027AV/028V/028AV
CY7C037AV/038V
Pin Configurations
A8R
A7R
A6R
A5R
A4R
A3R
A2R
A1R
A0R
INTR
BUSYR
M/S
GND
BUSYL
INTL
NC
A0L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
Figure 1. 100-pin TQFP pinout (Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
A9L
1
75
A9R
A10L
2
74
A10R
A11L
3
73
A11R
A12L
4
72
A12R
A13L
5
71
A13R
A14L
6
70
A14R
[6] A15L
7
69
A15R [6]
NC
8
68
NC
NC
9
67
NC
LBL
10
66
LBR
UBL
11
65
UBR
CE0L
12
64
CE0R
CE1L
13
63
CE1R
SEML
14
62
SEMR
VCC
15
61
GND
R/WL
16
60
R/WR
OEL
17
59
OER
GND
18
58
GND
GND
19
57
GND
I/O15L
20
56
I/O15R
I/O14L
21
55
I/O14R
I/O13L
22
54
I/O13R
I/O12L
23
53
I/O12R
I/O11L
24
52
I/O11R
I/O10L
25
51
I/O10R
CY7C028V/028AV (64K × 16)
CY7C027V/027AV (32K × 16)
NC
I/O9R
I/O8R
I/O7R
VCC
I/O6R
I/O5R
I/O4R
I/O3R
I/O2R
I/01R
I/O0R
GND
I/O0L
I/O1L
GND
I/O2L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
VCC
I/O8L
I/O9L
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note
6. This pin is NC for CY7C027V/027AV.
Document Number: 38-06078 Rev. *J
Page 4 of 26
CY7C027V/027AV/028V/028AV
CY7C037AV/038V
Pin Configurations(continued)
A7R
A6R
A5R
A4R
A3R
A2R
A1R
A0R
INTR
BUSYR
M/S
VCC
GND
GND
BUSYL
INTL
A0L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
Figure 2. 100-pin TQFP pinout (Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
[7]
A9L
1
75
A8R
A10L
2
74
A9R
A11L
3
73
A10R
A12L
4
72
A11R
A13L
5
71
A12R
A14L
6
70
A13R
A15L
7
69
A14R
LBL
8
68
A15R [7]
UBL
9
67
LBR
CE0L
10
66
UBR
CE1L
11
65
CE0R
SEML
12
64
CE1R
R/WL
13
63
SEMR
OEL
14
62
R/WR
VCC
15
61
GND
GND
16
60
OER
I/O17L
17
59
GND
I/O16L
18
58
I/O17R
GND
19
57
GND
I/O15L
20
56
I/O16R
I/O14L
21
55
I/O15R
I/O13L
22
54
I/O14R
I/O12L
23
53
I/O13R
I/O11L
24
52
I/O12R
I/O10L
25
51
I/O11R
CY7C038V (64K x 18)
CY7C037AV (32K x 18)
I/O10R
I/O9R
I/O8R
I/O7R
VCC
I/O6R
I/O5R
I/O4R
I/O3R
I/O2R
I/01R
I/O0R
GND
I/O0L
I/O1L
GND
I/O2L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
VCC
I/O8L
I/O9L
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note
7. This pin is NC for CY7C037AV.
Document Number: 38-06078 Rev. *J
Page 5 of 26
CY7C027V/027AV/028V/028AV
CY7C037AV/038V
Pin Definitions
Left Port
Right Port
Description
CE0L, CE1L
CE0R, CE1R
Chip Enable (CE is LOW when CE0 VIL and CE1 VIH)
R/WL
R/WR
Read/Write Enable
OEL
OER
Output Enable
A0L–A15L
A0R–A15R
Address (A0–A14 for 32K; A0–A15 for 64K devices)
I/O0L–I/O17L
I/O0R–I/O17R Data bus input/output (I/O0–I/O15 for × 16 devices; I/O0–I/O17 for × 18)
SEML
SEMR
Semaphore Enable
UBL
UBR
Upper byte select (I/O8–I/O15 for × 16 devices; I/O9–I/O17 for × 18 devices)
LBL
LBR
Lower byte select (I/O0–I/O7 for × 16 devices; I/O0–I/O8 for × 18 devices)
INTL
INTR
Interrupt flag
BUSYL
BUSYR
Busy flag
M/S
Master or Slave select
VCC
Power
GND
Ground
NC
No connect
Architecture
The CY7C027V/027AV/028V/028AV and CY7037AV/038V
consist of an array of 32K and 64K words of 16 and 18 bits each
of dual-port RAM cells, I/O and address lines, and control signals
(CE, OE, R/W). These control pins permit independent access for reads
or writes to any location in memory. To handle simultaneous
writes/reads to the same location, a BUSY pin is provided on each port.
Two interrupt (INT) pins can be utilized for port-to-port communication.
Two semaphore (SEM) control pins are used for allocating shared
resources. With the M/S pin, the devices can function as a master
(BUSY pins are outputs) or as a slave (BUSY pins are inputs). The
devices also have an automatic power down feature controlled by CE.
Each port is provided with its own output enable control (OE), which
allows data to be read from the device.
Functional Overview
Write Operation
the user wishes to access a semaphore flag, then the SEM pin must be
asserted instead of the CE pin, and OE must also be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (7FFF for the
CY7C027V/037AV/027AV, FFFF for the CY7C028V/028AV/38V)
is the mailbox for the right port and the second-highest memory
location (7FFE for the CY7C027V/027AV/037AV, FFFE for the
CY7C028V/028AV/38V) is the mailbox for the left port. When
one port writes to the other port’s mailbox, an interrupt is
generated to the owner. The interrupt is reset when the owner
reads the contents of the mailbox. The message is user defined.
Each port can read the other port’s mailbox without resetting the
interrupt. The active state of the busy signal (to a port) prevents
the port from setting the interrupt to the winning port. Also, an
active busy to a port prevents that port from reading its own
mailbox and, thus, resetting the interrupt to it.
Data must be set up for a duration of tSD before the rising edge of
R/W to guarantee a valid write. A write operation is controlled by either
the R/W pin (see Figure 7) or the CE pin (see Figure 8). Required inputs
for non-contention operations are summarized in Non-Contending
Read/Write on page 18.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin.
If a location is being written to by one port and the opposite port
attempts to read that location, a port-to-port flowthrough delay
must occur before the data is read on the output; otherwise the
data read is not deterministic. Data is valid on the port tDDD after
the data is presented on the other port.
Busy
Read Operation
When reading the device, the user must assert both the OE and
CE pins. Data is available tACE after CE or tDOE after OE is asserted. If
Document Number: 38-06078 Rev. *J
The operation of the interrupts and their interaction with Busy are
summarized in Interrupt Operation Example on page 18.
The CY7C027V/027AV/028V/028AV and CY7037AV/038V
provide on-chip arbitration to resolve simultaneous memory
location access (contention). If both ports’ CEs are asserted and
an address match occurs within tPS of each other, the busy logic determines which port has access. If tPS is violated, one port definitely gains
permission to the location, but it is not predictable which port gets that
permission. BUSY is asserted tBLA after an address match or tBLC after
CE is taken LOW.
Page 6 of 26
CY7C027V/027AV/028V/028AV
CY7C037AV/038V
Master/Slave
A M/S pin is provided to expand the word width by configuring the
device as either a master or a slave. The BUSY output of the master is
connected to the BUSY input of the slave. This allows the device to
interface to a master device with no external components. Writing to
slave devices must be delayed until after the BUSY input has settled
(tBLC or tBLA), otherwise, the slave chip may begin a write cycle during
a contention situation. When tied HIGH, the M/S pin allows the device
to be used as a master and, therefore, the BUSY line is an output. BUSY
can then be used to send the arbitration outcome to a slave.
Semaphore Operation
The CY7C027V/027AV/028V/028AV and CY7037AV/038V
provide eight semaphore latches, which are separate from the
dual-port memory locations. Semaphores are used to reserve
resources that are shared between the two ports.The state of the
semaphore indicates that a resource is in use. For example, if
the left port wants to request a given resource, it sets a latch by
writing a zero to a semaphore location. The left port then verifies
its success in setting the latch by reading it. After writing to the
semaphore, SEM or OE must be deasserted for tSOP before
attempting to read the semaphore. The semaphore value is available
tSWRD + tDOE after the rising edge of the semaphore write. If the left port
was successful (reads a zero), it assumes control of the shared
resource, otherwise (reads a one) it assumes the right port has control
and continues to poll the semaphore. When the right side has relinquished control of the semaphore (by writing a one), the left side
Document Number: 38-06078 Rev. *J
succeeds in gaining control of the semaphore. If the left side no longer
requires the semaphore, a one is written to cancel its request.
Semaphores are accessed by asserting SEM LOW. The SEM pin
functions as a chip select for the semaphore latches (CE must remain
HIGH during SEM LOW). A0–2 represents the semaphore address. OE
and R/W are used in the same manner as a normal memory access.
When writing or reading a semaphore, the other address pins have no
effect.
When writing to the semaphore, only I/O0 is used. If a zero is written
to the left port of an available semaphore, a one appears at the same
semaphore address on the right port. That semaphore can now only be
modified by the side showing zero (the left port in this case). If the left
port now relinquishes control by writing a one to the semaphore, the
semaphore is set to one for both sides. However, if the right port had
requested the semaphore (written a zero) while the left port had control,
the right port would immediately own the semaphore as soon as the left
port released it. Semaphore Operation Example on page 19 shows
sample semaphore operations.
When reading a semaphore, all sixteen/eighteen data lines
output the semaphore value. The read value is latched in an
output register to prevent the semaphore from changing state
during a write from the other port. If both ports attempt to access
the semaphore within tSPS of each other, the semaphore is definitely
obtained by one side or the other, but there is no guarantee which side
controls the semaphore.
Page 7 of 26
CY7C027V/027AV/028V/028AV
CY7C037AV/038V
DC input voltage [8] ............................. –0.5 V to VCC + 0.5 V
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage ......................................... > 1100 V
Storage temperature ................................ –65 °C to +150 °C
Latch-up current ................................................... > 200 mA
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Operating Range
Range
Supply voltage to ground potential ..............–0.5 V to +4.6 V
DC voltage applied to outputs
in High Z state .................................... –0.5 V to VCC + 0.5 V
Ambient Temperature
VCC
Commercial
0 °C to +70 °C
3.3 V 300 mV
Industrial [9]
–40 °C to +85 °C
3.3 V 300 mV
Electrical Characteristics
Over the Operating Range
CY7C027V/027AV/028V/028AV/CY7C037AV/CY7C038V
Parameter
Description
-15
Min
Typ
–
-20
Max
Min
Typ
2.4
–
-25
Max
Min
Typ
–
Unit
Max
VOH
Output HIGH voltage (VCC = Min., IOH = –4.0 mA)
2.4
–
2.4
–
V
VOL
Output LOW voltage (VCC = Min., IOH = +4.0 mA)
–
0.4
–
0.4
–
0.4
V
VIH
Input HIGH voltage
2.2
–
2.2
–
2.2
–
V
VIL
Input LOW voltage
–
0.8
–
0.8
–
0.8
V
IIX
Input leakage current
5
5
5
5
5
5
A
IOZ
Output leakage current
–10
10
–10
10
–10
10
A
ICC
Operating current
(VCC = Max., IOUT = 0 mA)
outputs disabled
Commercial
185
–
120
175
–
165
mA
140
195
Standby current
(Both ports TTL level)
CEL & CER VIH, f = fMAX
Commercial
35
45
45
55
Standby current
(One port TTL level)
CEL | CER VIH, f = fMAX
Commercial
Standby current
(Both ports CMOS level)
CEL & CER VCC 0.2 V, f = 0
Commercial
Standby current
(One port CMOS level)
CEL | CER VIH, f = fMAX[10]
Commercial
ISB1
ISB2
ISB3
ISB4
Industrial
Industrial
–
125
[9]
–
35
[9]
–
80
Industrial [9]
Industrial
Industrial
120
–
10
[9]
[9]
50
250
–
75
105
–
75
110
85
120
10
250
10
250
70
95
80
105
115
–
mA
30
40
–
mA
mA
65
95
–
mA
mA
10
250
A
A
–
60
80
–
mA
mA
Capacitance
Parameter [11]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = 3.3 V
Max
Unit
10
pF
10
pF
Notes
8. Pulse width < 20 ns.
9. Industrial parts are available in CY7C028V and CY7C038V, CY7C027V/027AV only.
10. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3.
11. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-06078 Rev. *J
Page 8 of 26
CY7C027V/027AV/028V/028AV
CY7C037AV/038V
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
3.3 V
3.3 V
R1 = 590
OUTPUT
OUTPUT
C = 30 pF
RTH = 250
R1 = 590
OUTPUT
C = 30 pF
R2 = 435
C = 5 pF
R2 = 435
VTH = 1.4 V
(a) Normal Load (Load 1)
(c) Three-State Delay (Load 2)
(Used for tLZ, tHZ, tHZWE, & tLZWE
including scope and jig)
(b) Thévenin Equivalent (Load 1)
ALL INPUT PULSES
3.0V
GND
10%
90%
10%
90%
3 ns
3 ns
Data Retention Mode
The CY7C027V/027AV/028V/028AV and CY7037AV/038V are
designed with battery backup in mind. Data retention voltage and
supply current are guaranteed over temperature. The following
rules ensure data retention:
1. Chip Enable (CE) must be held HIGH during data retention, within
VCC to VCC – 0.2 V
2. CE must be kept between VCC – 0.2 V and 70% of VCC during
the power up and power down transitions
3. The RAM can begin operation >tRC after VCC reaches the
minimum operating voltage (3.0 V)
Timing
Data Retention Mode
VCC
CE
Parameter
ICCDR1
3.0 V
VCC 2.0 V
3.0 V
tRC
VCC to VCC – 0.2 V
Test Conditions [12]
At VCCDR = 2 V
V
IH
Max
Unit
50
A
Note
12. CE = VCC, Vin = GND to VCC, TA = 25 C. This parameter is guaranteed but not tested.
Document Number: 38-06078 Rev. *J
Page 9 of 26
CY7C027V/027AV/028V/028AV
CY7C037AV/038V
Switching Characteristics
Over the Operating Range
Parameter [13]
CY7C027V/027AV/028V/028AV/
CY7C037AV/CY7C038V
Description
-15
-20
Unit
-25
Min
Max
Min
Max
Min
Max
Read Cycle
tRC
Read cycle time
15
–
20
–
25
–
ns
tAA
Address to data valid
–
15
–
20
–
25
ns
tOHA
Output hold from address change
3
–
3
–
3
–
ns
tACE[14]
CE LOW to data valid
–
15
–
20
–
25
ns
tDOE
OE LOW to data valid
–
10
–
12
–
13
ns
tLZOE[15, 16, 17] OE LOW to Low Z
3
–
3
–
3
–
ns
tHZOE[15, 16, 17]
tLZCE[15, 16, 17]
tHZCE[15, 16, 17]
tPU[17]
tPD[17]
tABE[14]
–
10
–
12
–
15
ns
OE HIGH to High Z
CE LOW to Low Z
3
–
3
–
3
–
ns
CE HIGH to High Z
–
10
–
12
–
15
ns
CE LOW to power-up
0
–
0
–
0
–
ns
CE HIGH to power-down
–
15
–
20
–
25
ns
Byte enable access time
–
15
–
20
–
25
ns
tWC
Write cycle time
15
–
20
–
25
–
ns
tSCE[14]
CE LOW to write end
12
–
16
–
20
–
ns
Write Cycle
tAW
Address valid to write end
12
–
16
–
20
–
ns
tHA
Address hold from write end
0
–
0
–
0
–
ns
tSA[14]
Address setup to write start
0
–
0
–
0
–
ns
tPWE
Write pulse width
12
–
17
–
22
–
ns
tSD
Data setup to write end
10
–
12
–
15
–
ns
tHD
Data hold from write end
0
–
0
–
0
–
ns
tHZWE[16, 17]
R/W LOW to High Z
–
10
–
12
–
15
ns
tLZWE[16, 17]
tWDD[18]
tDDD[18]
R/W HIGH to Low Z
3
–
3
–
3
–
ns
Write pulse to data delay
–
30
–
40
–
50
ns
Write data valid to read data valid
–
25
–
30
–
35
ns
Notes
13. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOI/IOH
and 30 pF load capacitance.
14. To access RAM, CE=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire tSCE time.
15. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
16. Test conditions used are Load 2.
17. This parameter is guaranteed by design, but it is not production tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer
to Figure 11 on page 15.
18. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).
Document Number: 38-06078 Rev. *J
Page 10 of 26
CY7C027V/027AV/028V/028AV
CY7C037AV/038V
Switching Characteristics(continued)
Over the Operating Range
CY7C027V/027AV/028V/028AV/
CY7C037AV/CY7C038V
Parameter [13]
Description
-15
-20
Unit
-25
Min
Max
Min
Max
Min
Max
Busy Timing[19]
tBLA
BUSY LOW from address match
–
15
–
20
–
20
ns
tBHA
BUSY HIGH from address
mismatch
–
15
–
20
–
20
ns
tBLC
BUSY LOW from CE LOW
–
15
–
20
–
20
ns
tBHC
BUSY HIGH from CE HIGH
–
15
–
16
–
17
ns
tPS
Port setup for priority
5
–
5
–
5
–
ns
tWB
R/W HIGH after BUSY (Slave)
0
–
0
–
0
–
ns
tWH
R/W HIGH after BUSY HIGH (Slave)
13
–
15
–
17
–
ns
tBDD[20]
BUSY HIGH to data valid
–
15
–
20
–
25
ns
Interrupt Timing
[19]
tINS
INT set time
–
15
–
20
–
20
ns
tINR
INT reset time
–
15
–
20
–
20
ns
Semaphore Timing
tSOP
SEM flag update pulse (OE or
SEM)
10
–
10
–
12
–
ns
tSWRD
SEM flag write to read time
5
–
5
–
5
–
ns
tSPS
SEM flag contention window
5
–
5
–
5
–
ns
tSAA
SEM address access time
–
15
–
20
–
25
ns
Notes
19. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Figure 11 on page 15.
20. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).
Document Number: 38-06078 Rev. *J
Page 11 of 26
CY7C027V/027AV/028V/028AV
CY7C037AV/038V
Switching Waveforms
Figure 4. Read Cycle No. 1 (Either Port Address Access) [21, 22, 23]
tRC
ADDRESS
tOHA
DATA OUT
tAA
tOHA
PREVIOUS DATA VALID
DATA VALID
Figure 5. Read Cycle No. 2 (Either Port CE/OE Access) [21, 24, 25]
tACE
CE and
LB or UB
tHZCE
tDOE
OE
tHZOE
tLZOE
DATA VALID
DATA OUT
tLZCE
tPU
tPD
ICC
CURRENT
ISB
Figure 6. Read Cycle No. 3 (Either Port) [21, 23, 24, 25]
tRC
ADDRESS
tAA
tOHA
UB or LB
tHZCE
tLZCE
tABE
CE
tHZCE
tACE
tLZCE
DATA OUT
Notes
21. R/W is HIGH for read cycles.
22. Device is continuously selected CE = VIL and UB or LB = VIL. This waveform cannot be used for semaphore reads.
23. OE = VIL.
24. Address valid prior to or coincident with CE transition LOW.
25. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.
Document Number: 38-06078 Rev. *J
Page 12 of 26
CY7C027V/027AV/028V/028AV
CY7C037AV/038V
Switching Waveforms(continued)
Figure 7. Write Cycle No. 1: R/W Controlled Timing [26, 27, 28, 29]
tWC
ADDRESS
tHZOE [32]
OE
tAW
CE
[30,31]
tPWE[29]
tSA
tHA
R/W
tHZWE[32]
DATA OUT
tLZWE
NOTE 33
NOTE 33
tSD
tHD
DATA IN
Figure 8. Write Cycle No. 2: CE Controlled Timing [26, 27, 28, 34]
tWC
ADDRESS
tAW
CE
[30,31]
tSA
tSCE
tHA
R/W
tSD
tHD
DATA IN
Notes
26. R/W must be HIGH during all address transitions.
27. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM and a LOW UB or LB.
28. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
29. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on the bus
for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tPWE.
30. To access RAM, CE = VIL, SEM = VIH.
31. To access upper byte, CE = VIL, UB = VIL, SEM = VIH.
To access lower byte, CE = VIL, LB = VIL, SEM = VIH.
32. Transition is measured 500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100% tested.
33. During this period, the I/O pins are in the output state, and input signals must not be applied.
34. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.
Document Number: 38-06078 Rev. *J
Page 13 of 26
CY7C027V/027AV/028V/028AV
CY7C037AV/038V
Switching Waveforms(continued)
Figure 9. Semaphore Read After Write Timing, Either Side [35]
tOHA
tSAA
A0–A 2
VALID ADRESS
VALID ADRESS
tAW
tACE
tHA
SEM
tSCE
tSOP
tSD
I/O 0
DATAIN VALID
tSA
tPWE
DATAOUT VALID
tHD
R/W
tSWRD
tDOE
tSOP
OE
WRITE CYCLE
READ CYCLE
Figure 10. Timing Diagram of Semaphore Contention [36, 37, 38]
A0L –A2L
MATCH
R/WL
SEM L
tSPS
A 0R –A 2R
MATCH
R/WR
SEM R
Notes
35. CE = HIGH for the duration of the above timing (both write and read cycle).
36. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH.
37. Semaphores are reset (available to both ports) at cycle start.
38. If tSPS is violated, the semaphore is definitely obtained by one side or the other, but which side gets the semaphore is unpredictable.
Document Number: 38-06078 Rev. *J
Page 14 of 26
CY7C027V/027AV/028V/028AV
CY7C037AV/038V
Switching Waveforms(continued)
Figure 11. Timing Diagram of Read with BUSY (M/S = HIGH) [39]
tWC
ADDRESSR
MATCH
tPWE
R/WR
tSD
DATA INR
tHD
VALID
tPS
ADDRESSL
MATCH
tBLA
tBHA
BUSYL
tBDD
tDDD
DATA OUTL
VALID
tWDD
Figure 12. Write Timing with Busy Input (M/S = LOW)
tPWE
R/W
BUSY
tWB
tWH
Note
39. CEL = CER = LOW.
Document Number: 38-06078 Rev. *J
Page 15 of 26
CY7C027V/027AV/028V/028AV
CY7C037AV/038V
Switching Waveforms(continued)
Figure 13. Busy Timing Diagram No. 1 (CE Arbitration) [40]
CELValid First:
ADDRESS L,R
ADDRESS MATCH
CEL
tPS
CER
tBLC
tBHC
BUSYR
CER Valid First:
ADDRESS L,R
ADDRESS MATCH
CER
tPS
CE L
tBLC
tBHC
BUSY L
Figure 14. Busy Timing Diagram No. 2 (Address Arbitration) [40]
Left Address Valid First:
tRC or tWC
ADDRESS L
ADDRESS MATCH
ADDRESS MISMATCH
tPS
ADDRESSR
tBLA
tBHA
BUSY R
Right Address Valid First:
tRC or tWC
ADDRESSR
ADDRESS MATCH
ADDRESS MISMATCH
tPS
ADDRESSL
tBLA
tBHA
BUSY L
Note
40. If tPS is violated, the busy signal is asserted on one side or the other, but there is no guarantee to which side BUSY is asserted.
Document Number: 38-06078 Rev. *J
Page 16 of 26
CY7C027V/027AV/028V/028AV
CY7C037AV/038V
Switching Waveforms(continued)
Figure 15. Interrupt Timing Diagrams
Left Side Sets INTR :
ADDRESSL
tWC
WRITE 7FFF (FFFF for CY7C028V/028AV/38V)
tHA[41]
CE L
R/W L
INT R
tINS [42]
Right Side Clears INT R :
tRC
READ 7FFF
(FFFF for CY7C028V/028AV/38V)
ADDRESSR
CE R
tINR [42]
R/WR
OE R
INTR
Right Side Sets INT L:
tWC
ADDRESSR
WRITE 7FFE (FFFE for CY7C028V/028AV/38V)
tHA[41]
CE R
R/W R
INT L
[42]
tINS
Left Side Clears INT L:
tRC
READ 7FFE
ADDRESSR
(FFFE for CY7C028V/028AV/38V)
CE L
tINR[42]
R/W L
OE L
INT L
Notes
41. tHA depends on which enable pin (CEL or R/WL) is deasserted first.
42. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
Document Number: 38-06078 Rev. *J
Page 17 of 26
CY7C027V/027AV/028V/028AV
CY7C037AV/038V
Non-Contending Read/Write
Inputs
Outputs
CE
R/W
OE
UB
LB
SEM
I/O9–I/O17
I/O0–I/O8
Operation
H
X
X
X
X
H
High Z
High Z
Deselected: Power-down
X
X
X
H
H
H
High Z
High Z
Deselected: Power-down
L
L
X
L
H
H
Data in
High Z
Write to upper byte only
L
L
X
H
L
H
High Z
Data in
Write to lower byte only
L
L
X
L
L
H
Data in
Data in
Write to both bytes
L
H
L
L
H
H
Data out
High Z
Read upper byte only
L
H
L
H
L
H
High Z
Data out
Read lower byte only
L
H
L
L
L
H
Data out
Data out
Read both bytes
X
X
H
X
X
X
High Z
High Z
Outputs disabled
H
H
L
X
X
L
Data out
Data out
Read data in semaphore flag
X
H
L
H
H
L
Data out
Data out
Read data in semaphore flag
H
X
X
X
L
Data in
Data in
Write DIN0 into semaphore flag
X
X
H
H
L
Data in
Data in
Write DIN0 into semaphore flag
L
X
X
L
X
L
Not allowed
L
X
X
X
L
L
Not allowed
Interrupt Operation Example
(Assumes BUSYL = BUSYR = HIGH) [43]
Left Port
Function
Right Port
R/WL
CEL
OEL
A0L–14L
INTL
R/WR
CER
OER
A0R–14R
INTR
Set right INTR flag
L
L
X
7FFF
X
X
X
X
X
L[44]
Reset right INTR flag
X
X
X
X
X
X
L
L
7FFF
H[45]
Set left INTL flag
X
X
X
X
L[45]
L
L
X
7FFE
X
[44]
X
X
X
X
X
Reset left INTL flag
X
L
L
7FFE
H
Notes
43. A0L–15L and A0R–15R,FFFF/FFFE for the CY7C028V/038V.
44. If BUSYL=L, then no change.
45. If BUSYR=L, then no change.
Document Number: 38-06078 Rev. *J
Page 18 of 26
CY7C027V/027AV/028V/028AV
CY7C037AV/038V
Semaphore Operation Example
Function
I/O0–I/O17 Left
I/O0–I/O17 Right
No action
1
1
Semaphore free
Left port writes 0 to semaphore
0
1
Left port has semaphore token
Right port writes 0 to semaphore
0
1
No change. Right side has no write access to semaphore
Left port writes 1 to semaphore
1
0
Right port obtains semaphore token
Left port writes 0 to semaphore
1
0
No change. Left port has no write access to semaphore
Right port writes 1 to semaphore
0
1
Left port obtains semaphore token
Left port writes 1 to semaphore
1
1
Semaphore free
Right port writes 0 to semaphore
1
0
Right port has semaphore token
Right port writes 1 to semaphore
1
1
Semaphore free
Left port writes 0 to semaphore
0
1
Left port has semaphore token
Left port writes 1 to semaphore
1
1
Semaphore free
Document Number: 38-06078 Rev. *J
Status
Page 19 of 26
CY7C027V/027AV/028V/028AV
CY7C037AV/038V
Ordering Information
32K × 16 3.3 V Asynchronous Dual-Port SRAM
Speed
(ns)
15
Ordering Code
Package
Name
Package Type
Operating
Range
CY7C027V-15AXC
A100
100-pin TQFP (Pb-free)
Commercial
CY7C027V-15AXI
A100
100-pin TQFP (Pb-free)
Industrial
20
CY7C027V-20AXC
A100
100-pin TQFP (Pb-free)
Commercial
25
CY7C027V-25AXC
A100
100-pin TQFP (Pb-free)
Commercial
64K × 16 3.3 V Asynchronous Dual-Port SRAM
Speed
(ns)
15
20
25
Ordering Code
Package
Name
Package Type
Operating
Range
CY7C028V-15AXC
A100
100-pin TQFP (Pb-free)
Commercial
CY7C028V-15AXI
A100
100-pin TQFP (Pb-free)
Industrial
CY7C028V-20AXC
A100
100-pin TQFP (Pb-free)
Commercial
CY7C028V-20AI
A100
100-pin TQFP
Industrial
CY7C028V-20AXI
A100
100-pin TQFP (Pb-free)
Industrial
CY7C028V-25AXC
A100
100-pin TQFP (Pb-free)
Commercial
CY7C028AV-25AXC
A100
100-pin TQFP (Pb-free)
Commercial
32K × 18 3.3 V Asynchronous Dual-Port SRAM
Speed
(ns)
20
Ordering Code
CY7C037AV-20AXI
Package
Name
A100
Package Type
100-pin TQFP (Pb-free)
Operating
Range
Industrial
64K × 18 3.3 V Asynchronous Dual-Port SRAM
Speed
(ns)
20
Ordering Code
CY7C038V-20AXI
Document Number: 38-06078 Rev. *J
Package
Name
A100
Package Type
100-pin TQFP (Pb-free)
Operating
Range
Industrial
Page 20 of 26
CY7C027V/027AV/028V/028AV
CY7C037AV/038V
Ordering Code Definitions
CY
7C
0X
X
X
XX
A
X
X
Operating Range
C = Com m ercial I = Industrial
X : Pb free (RoHS Com pliant)
Package: A=TQFP
Speed Grade : 15ns/20ns/25ns
X = V/AV : 3.3 V
Depth: 7=32K or 8=64K
W idth: 02=x16 or 03=x18
7C = Dual Port SRAM
Com pany ID: CY = Cypress
Document Number: 38-06078 Rev. *J
Page 21 of 26
CY7C027V/027AV/028V/028AV
CY7C037AV/038V
Package Diagram
Figure 16. 100-pin TQFP (14 × 14 × 1.4 mm) A100SA Package Outline, 51-85048
51-85048 *J
Document Number: 38-06078 Rev. *J
Page 22 of 26
CY7C027V/027AV/028V/028AV
CY7C037AV/038V
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CMOS
Complementary Metal Oxide Semiconductor
I/O
Input/Output
°C
degree Celsius
SRAM
Static Random Access Memory
MHz
megahertz
TQFP
Thin Quad Flat Pack
µA
microampere
mA
milliampere
mV
millivolt
ns
nanosecond
ohm
pF
picofarad
V
volt
W
watt
Document Number: 38-06078 Rev. *J
Symbol
Unit of Measure
Page 23 of 26
CY7C027V/027AV/028V/028AV
CY7C037AV/038V
Document History Page
Document Title: CY7C027V/027AV/028V/028AV/CY7C037AV/038V, 3.3 V, 32K/64K × 16/18 Dual-Port Static RAM
Document Number: 38-06078
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
**
237626
YDT
06/30/2004
Converted data sheet from old spec 38-00670 to conform with new data sheet.
Updated Features (Removed cross information).
*A
259110
JHX
09/01/2004
Added Pb-Free logo in top of first page.
Updated Ordering Information (Updated part numbers).
*B
2623540
VKN /
PYRS
12/17/2008
Updated Document Title to read as “CY7C027V/027VN/027AV/
CY7C028V/037V/037AV/038V 3.3V 32K/64K x 16/18 Dual Port Static RAM”.
Added CY7C027VN, CY7C027AV and CY7C037AV parts related information
in all instances across the document.
Updated Ordering Information (Updated part numbers).
Updated to new template.
*C
2897217
RAME
03/22/2010
Updated Ordering Information (Updated part numbers).
Updated Package Diagram:
spec 51-85048 – Changed revision from *C to *D.
*D
3093542
ADMU
11/25/2010
Updated Document Title to read as “CY7C027V/027AV/
CY7C028V/037AV/038V 3.3 V 32K/64K X 16/18 Dual Port Static RAM”.
Removed CY7C027VN and CY7C037V parts related information in all
instances across the document.
Updated Ordering Information:
No change in part numbers.
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Updated to new template.
Completing Sunset Review.
*E
3403652
ADMU
10/14/2011
Updated Ordering Information (Updated part numbers).
Updated Package Diagram:
spec 51-85048 – Changed revision from *D to *E.
Completing Sunset Review.
*F
3845411
ADMU
01/29/2013
Updated Ordering Information (Updated part numbers).
Updated Package Diagram:
spec 51-85048 – Changed revision from *E to *G.
*G
3896090
ADMU
02/05/2013
Updated Ordering Information (Updated part numbers).
*H
4103305
ADMU
08/23/2013
Updated Document Title to read as “CY7C027V/027AV/028V/028AV/
CY7C037AV/038V, 3.3 V 32 K / 64 K × 16 / 18 Dual-Port Static RAM”.
Included CY7C028AV related information in all instances across the document.
Updated Ordering Information (Updated part numbers).
Updated Package Diagram:
spec 51-85048 – Changed revision from *G to *H.
Updated to new template.
*I
4575241
ADMU
11/20/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Ordering Information:
Updated part numbers.
Updated Package Diagram:
spec 51-85048 – Changed revision from *H to *I.
Completing Sunset Review.
Document Number: 38-06078 Rev. *J
Page 24 of 26
CY7C027V/027AV/028V/028AV
CY7C037AV/038V
Document History Page(continued)
Document Title: CY7C027V/027AV/028V/028AV/CY7C037AV/038V, 3.3 V, 32K/64K × 16/18 Dual-Port Static RAM
Document Number: 38-06078
Rev.
ECN No.
Orig. of
Change
Submission
Date
*J
6043656
VINI
01/24/2018
Document Number: 38-06078 Rev. *J
Description of Change
Updated Ordering Information:
Updated part numbers.
Updated Package Diagram:
spec 51-85048 – Changed revision from *I to *J.
Updated to new template.
Completing Sunset Review.
Page 25 of 26
CY7C027V/027AV/028V/028AV
CY7C037AV/038V
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2004-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 38-06078 Rev. *J
Revised January 24, 2018
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