CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
FLEx18™ 3.3V 64K/128K x 36 and
128K/256K x 18 Synchronous Dual-Port RAM
Features
Functional Description
■
True Dual-Ported Memory Cells that Allow Simultaneous
Access of the Same Memory Location
■
Synchronous Pipelined Operation
■
Family of 512 Kbit, 1 Mbit, 2 Mbit, 4 Mbit, and 9 Mbit Devices
■
Pipelined Output Mode Allows Fast Operation
■
0.18 micron CMOS for Optimum Speed and Power
The FLEx18™ family includes 512 Kbit, 1 Mbit, 2 Mbit, 4 Mbit,
and 9 Mbit pipelined, synchronous, true dual port static RAMs
that are high speed, low power 3.3V CMOS. Two ports are
provided, permitting independent, simultaneous access to any
location in memory. The result of writing to the same location by
more than one port at the same time is undefined. Registers on
control, address, and data lines allow for minimal setup and hold
time.
■
High Speed Clock to Data Access
■
3.3V Low Power
❐ Active as Low as 225 mA (typ)
❐ Standby as Low as 55 mA (typ)
■
Mailbox Function for Message Passing
■
Global Master Reset
■
Separate Byte Enables on Both Ports
■
Commercial and Industrial Temperature Ranges
■
IEEE 1149.1 Compatible JTAG Boundary Scan
■
144-Ball FBGA (13 mm × 13 mm) (1.0 mm pitch)
■
120 TQFP (14 mm x 14 mm x 1.4 mm)
■
Pb-Free Packages Available
■
Counter Wrap Around Control
❐ Internal Mask Register Controls Counter Wrap Around
❐ Counter-Interrupt Flags to Indicate Wrap Around
❐ Memory Block Retransmit Operation
■
Counter Readback on Address Lines
■
Mask Register Readback on Address Lines
■
Dual Chip Enables on Both Ports for Easy Depth Expansion
During a Read operation, data is registered for decreased cycle
time. Each port contains a burst counter on the input address
register. After externally loading the counter with the initial
address, the counter increments the address internally (more
details to follow). The internal Write pulse width is independent
of the duration of the R/W input signal. The internal Write pulse
is self-timed to allow the shortest possible cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle powers down
the internal circuitry to reduce the static power consumption. One
cycle with chip enables asserted is required to reactivate the
outputs.
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
The CY7C0833AV device in this family has limited features. See
Address Counter and Mask Register Operations [16] on page 6
for details.
Table 1. Product Selection Guide
512 Kbit
(32K x 18)
1 Mbit
(64K x 18)
2 Mbit
(128K x 18)
CY7C0837AV
CY7C0830AV
CY7C0831AV
CY7C0832AV
CY7C0832BV [1]
CY7C0833AV
Maximum Speed (MHz)
167
167
167
167
133
133
Maximum Access Time Clock to Data (ns)
4.0
4.0
4.0
4.0
4.4
4.7
Typical Operating
Current (mA)
225
225
225
225
225
270
144 FBGA
120 TQFP
144 FBGA
120 TQFP
144 FBGA
120 TQFP
144 FBGA
120 TQFP
144 FBGA
Density
Part Number
Package
4 Mbit
(256K x 18)
9 Mbit
(512K x 18)
Note
1. CY7C0832AV and CY7C0832BV are functionally identical.
Cypress Semiconductor Corporation
Document #: 38-06059 Rev. *S
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 03, 2009
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Logic Block Diagram [2]
OEL
R/WL
OER
R/WR
B0L
B0R
B1L
B1R
CE0L
CE1L
DQ9L–DQ17L
DQ0L–DQ8L
CE0R
CE1R
I/O
Control
9
I/O
Control
9
9
9
Addr.
Read
Back
DQ9R–DQ17R
DQ0R–DQ8R
Addr.
Read
Back
True
Dual-Ported
RAM Array
A0L–A18L
19
19
Mask Register
Mask Register
A0R–A18R
CNT/MSKR
CNT/MSKL
ADSL
Counter/
Address
Register
CNTENL
CNTRSTL
CLKL
Address
Address
Decode
Decode
Mirror Reg
INTL
Logic
CNTEN
CNTRSTR
Mirror Reg
CNTINTL
Interrupt
ADS
Counter/
Address
Register
MRST
Reset
Logic
TMS
TDI
TCK
JTAG
TDO
CLKR
CNTINTR
Interrupt
Logic
INTR
Note
2. CY7C0837AV has 15 address bits, CY7C0830AV has 16 address bits, CY7C0831AV has 17 address bits, CY7C0832AV/CY7C0832BV has 18 address bits and
CY7C0833AV has 19 address bits.
Document #: 38-06059 Rev. *S
Page 2 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Pin Configurations
Figure 1. 144-Ball BGA (Top View)
CY7C0837AV / CY7C0830AV / CY7C0831AV / CY7C0832AV / CY7C0833AV
1
2
3
4
5
6
7
8
9
10
11
12
A
DQ17L
DQ16L
DQ14L
DQ12L
DQ10L
DQ9L
DQ9R
DQ10R
DQ12R
DQ14R
DQ16R
DQ17R
B
A0L
A1L
DQ15L
DQ13L
DQ11L
MRST
NC
DQ11R
DQ13R
DQ15R
A1R
A0R
C
A2L
A3L
CE1L
[7]
INTL
CNTINTL
[9]
ADSL
[8]
ADSR
[8]
CNTINTR
[9]
INTR
CE1R
[7]
A3R
A2R
D
A4L
A5L
CE0L
[8]
NC
VDD
VDD
VDD
VDD
NC
CE0R
[8]
A5R
A4R
E
A6L
A7L
B1L
NC
VDD
VSS
VSS
VDD
NC
B1R
A7R
A6R
F
A8L
A9L
CL
NC
VSS
VSS
VSS
VSS
NC
CR
A9R
A8R
G
A10L
A11L
B0L
NC
VSS
VSS
VSS
VSS
NC
B0R
A11R
A10R
H
A12L
A13L
OEL
NC
VDD
VSS
VSS
VDD
NC
OER
A13R
A12R
J
A14L
A15L
[3]
RWL
NC
VDD
VDD
VDD
VDD
NC
RWR
A15R
[3]
A14R
K
A16L
[4]
A17L
[5]
CNT/MSKL
[7]
TDO
CNTRSTL
[7]
TCK
TMS
CNTRSTR
[7]
TDI
CNT/MSKR
[7]
A17R
[5]
A16R
[4]
L
A18L
[6]
NC
DQ6L
DQ4L
DQ2L
CNTENL
[8]
CNTENR
[8]
DQ2R
DQ4R
DQ6R
NC
A18R
[6]
M
DQ8L
DQ7L
DQ5L
DQ3L
DQ1L
DQ0L
DQ0R
DQ1R
DQ3R
DQ5R
DQ7R
DQ8R
Notes
3. Leave this ball unconnected for CY7C0837AV.
4. Leave this ball unconnected for CY7C0837AV and CY7C0830AV.
5. Leave this ball unconnected for CY7C0837AV, CY7C0830AV and CY7C0831AV.
6. Leave this ball unconnected for CY7C0837AV, CY7C0830AV, CY7C0831AV, and CY7C0832AV.
7. These balls are not applicable for CY7C0833AV device. They must be tied to VDD.
8. These balls are not applicable for CY7C0833AV device. They must be tied to VSS.
9. These balls are not applicable for CY7C0833AV device. They must not be connected.
Document #: 38-06059 Rev. *S
Page 3 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Pin Configurations
Figure 2. 120-Pin Thin Quad Flat Pack (TQFP) (Top View)
A2L
A3L
VSS
VDD
A4L
A5L
A6L
A7L
CE1L
B0L
B1L
OEL
CE0L
VDD
VSS
R/WL
CLKL
VSS
ADSL
CNTENL
CNTRSTL
CNT/MSKL
A8L
A9L
A10L
A11L
A12L
VSS
VDD
INTR
DQ9R
DQ10R
DQ11R
DQ15L
DQ14L
DQ13L
VDD
VSS
DQ12L
DQ11L
DQ10L
DQ9L
INTL
CNTINTL
CNTINTR
DQ12R
VSS
VDD
DQ13R
DQ14R
DQ15R
DQ16R
DQ17R
A0R
A1R
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
A2R
A3R
VSS
VDD
A4R
A5R
A6R
A7R
CE1R
B0R
B1R
OER
CE0R
VDD
VSS
R/WR
CLKR
MRST
ADSR
CNTENR
CNTRSTR
CNT/MSKR
A8R
A9R
A10R
A11R
A12R
VSS
VDD
A13R
VDD
DQ4R
DQ5R
DQ6R
DQ7R
DQ8R
A17R[10]
A16R[9]
A15R
A14R
DQ1R
DQ2R
DQ3R
VSS
DQ8L
DQ7L
DQ6L
DQ5L
DQ4L
VDD
VSS
DQ3L
DQ2L
DQ1L
DQ0L
DQ0R
A14L
A15L
A16L[9]
A17L[10]
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
A13L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
A1L
A0L
DQ17L
DQ16L
CY7C0830AV / CY7C0831AV / CY7C0832AV / CY7C0832BV
Notes
10. Leave this pin unconnected for CY7C0830AV.
11. Leave this pin unconnected for CY7C0830AV and CY7C0831AV.
Document #: 38-06059 Rev. *S
Page 4 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Pin Definitions
Left Port
Right Port
Description
A0L–A18L[2]
A0R–A18R[2]
Address Inputs.
ADSL[8]
ADSR[8]
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW for
the part using the externally supplied address on the address pins and for loading this address
into the burst address counter.
CE0L[8]
CE0R[8]
Active LOW Chip Enable Input.
CE1L[7]
CE1R
[7]
Active HIGH Chip Enable Input.
CLKL
CLKR
Clock Signal. Maximum clock input rate is fMAX.
CNTENL[8]
CNTENR[8]
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. The increment is disabled if ADS or CNTRST are
asserted LOW.
CNTRSTL[7]
CNTRSTR[7]
Counter Reset Input. Asserting this signal LOW resets to zero the unmasked portion of the
burst address counter of its respective port. CNTRST is not disabled by asserting ADS or
CNTEN.
CNT/MSKL[7]
CNT/MSKR[7]
Address Counter Mask Register Enable Input. Asserting this signal LOW enables access to
the mask register. When tied HIGH, the mask register is not accessible and the address counter
operations are enabled based on the status of the counter control signals.
DQ0L–DQ17L
DQ0R–DQ17R
Data Bus Input/Output.
OEL
OER
Output Enable Input. This asynchronous signal must be asserted LOW to enable the DQ data
pins during Read operations.
INTL
INTR
Mailbox Interrupt Flag Output. The mailbox permits communications between ports. The
upper two memory locations are used for message passing. INTL is asserted LOW when the
right port writes to the mailbox location of the left port, and vice versa. An interrupt to a port is
deasserted HIGH when it reads the contents of its mailbox.
CNTINTL[9]
CNTINTR[9]
Counter Interrupt Output. This pin is asserted LOW when the unmasked portion of the counter
is incremented to all ‘1s.’
R/WL
R/WR
Read/Write Enable Input. Assert this pin LOW to write to, or HIGH to Read from the dual port
memory array.
B0L–B1L
B0R–B1R
Byte Select Inputs. Asserting these signals enables Read and Write operations to the corresponding bytes of the memory array.
Master Reset Input. MRST is an asynchronous input signal and affects both ports. Asserting
MRST LOW performs all of the reset functions as described in the text. A MRST operation is
required at power up.
MRST
TMS
JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State
machine transitions occur on the rising edge of TCK.
TDI
JTAG Test Data Input. Data on the TDI input is shifted serially into selected registers.
TCK
JTAG Test Clock Input.
TDO
JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally
three-stated except when captured data is shifted out of the JTAG TAP.
VSS
Ground Inputs.
VDD
Power Inputs.
Byte Select Operation
Control Pin
Document #: 38-06059 Rev. *S
Effect
B0
DQ0–8 Byte Control
B1
DQ9–17 Byte Control
Page 5 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Master Reset
The counter register contains the address used to access the
RAM array. It is changed only by the Counter Load, Increment,
Counter Reset, and by master reset (MRST) operations.
The FLEx18 family devices undergo a complete reset by taking
its MRST input LOW. The MRST input can switch asynchronously to the clocks. An MRST initializes the internal burst
counters to zero, and the counter mask registers to all ones
(completely unmasked). MRST also forces the Mailbox Interrupt
(INT) flags and the Counter Interrupt (CNTINT) flags HIGH.
MRST must be performed on the FLEx18 family devices after
power up.
The mask register value affects the Increment and Counter
Reset operations by preventing the corresponding bits of the
counter register from changing. It also affects the counter
interrupt output (CNTINT). The mask register is changed only by
the Mask Load and Mask Reset operations and by the MRST.
The mask register defines the counting range of the counter
register. It divides the counter register into two regions: zero or
more ‘0s’ in the most significant bits define the masked region,
one or more ‘1s’ in the least significant bits define the unmasked
region. Bit 0 may also be ‘0,’ masking the least significant counter
bit and causing the counter to increment by two instead of one.
Mailbox Interrupts
The upper two memory locations may be used for message
passing and permit communications between ports. Table 2
shows the interrupt operation for both ports of CY7C0833AV.
The highest memory location, 7FFFF is the mailbox for the right
port and 7FFFE is the mailbox for the left port. Table 2 shows that
to set the INTR flag, a Write operation by the left port to address
7FFFF asserts INTR LOW. At least one byte has to be active for
a Write to generate an interrupt. A valid Read of the 7FFFF
location by the right port resets INTR HIGH. At least one byte
must be active for a Read to reset the interrupt. When one port
Writes to the other port’s mailbox, the INT of the port that the
mailbox belongs to is asserted LOW. The INT is reset when the
owner (port) of the mailbox Reads the contents of the mailbox.
The interrupt flag is set in a flow-through mode (that is, it follows
the clock edge of the writing port). Also, the flag is reset in a
flow-through mode (that is, it follows the clock edge of the
reading port).
The mirror register is used to reload the counter register on
increment operations (see Retransmit on page 8). It always
contains the value last loaded into the counter register, and is
changed only by the Counter Load, and by the MRST instructions. Table 3 on page 7 summarizes the operation of these
registers and the required input control signals. The MRST
control signal is asynchronous. All the other control signals in
Table 3 on page 7 (CNT/MSK, CNTRST, ADS, CNTEN) are
synchronized to the port’s CLK. All these counter and mask
operations are independent of the port’s chip enable inputs (CE0
and CE1).
Counter enable (CNTEN) inputs are provided to stall the
operation of the address input and use the internal address
generated by the internal counter for fast, interleaved memory
applications. A port’s burst counter is loaded when the port’s
address strobe (ADS) and CNTEN signals are LOW. When the
port’s CNTEN is asserted and the ADS is deasserted, the
address counter increments on each LOW to HIGH transition of
that port’s clock signal. This reads and writes one word from and
to each successive address location until CNTEN s deasserted.
The counter can address the entire memory array, and loops
back to the start. Counter reset (CNTRST) is used to reset the
unmasked portion of the burst counter to I/0s. A counter-mask
register is used to control the counter wrap.
Each port can read the other port’s mailbox without resetting the
interrupt. And each port can write to its own mailbox without
setting the interrupt. If an application does not require message
passing, INT pins should be left open.
Address Counter and Mask Register Operations [16]
This section describes the features only apply to 512 Kbit,1 Mbit,
2 Mbit, and 4 Mbit devices. It does not apply to 9 Mbit device.
Each port of these devices has a programmable burst address
counter. The burst counter contains three registers: a counter
register, a mask register, and a mirror register.
Table 2. Interrupt Operation Example [2, 12, 13, 14, 15, 17]
FUNCTION
LEFT PORT
R/WL
CEL
A0L–A18L
RIGHT PORT
INTL
R/WR
CER
A0R–A18R
INTR
Set Right INTR Flag
L
L
3FFFF
X
X
X
X
L
Reset Right INTR Flag
X
X
X
X
H
L
3FFFF
H
Set Left INTL Flag
X
X
X
L
L
L
3FFFE
X
Reset Left INTL Flag
H
L
3FFFE
H
X
X
X
X
Set Right INTR Flag
L
L
3FFFF
X
X
X
X
L
Notes
12. CE is internal signal. CE = LOW if CE0 = LOW and CE1 = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK and
can be deasserted after that. Data is out after the following CLK edge and is three-stated after the next CLK edge.
13. OE is “Don’t Care” for mailbox operation.
14. At least one of BE0, BE1 must be LOW.
15. A18x is a NC for CY7C0832AV/CY7C0832BV, therefore the Interrupt Addresses are 3FFFF and 3FFFE. A18x and A17x are NC for CY7C0831AV, therefore the Interrupt
addresses are 1FFFF and 1FFFE; A18x, A17x and A16x are NC for CY7C0830AV, therefore the Interrupt Addresses are FFFF and FFFE;A18x, A17x, A16x and A15x
are NC for CY7C0837AV, therefore the Interrupt Addresses are 7FFF and 7FFE.
16. This section describes the CY7C0832AV/CY7C0832BV, CY7C0831AV, CY7C0830AV and CY7C0837AV having 18, 17, 16 and 15 address bits.
17. “X” = “Don’t Care,” “H” = HIGH, “L” = LOW.
Document #: 38-06059 Rev. *S
Page 6 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Counter Reset Operation
All unmasked bits of the counter are reset to ‘0.’ All masked bits
remain unchanged. The mirror register is loaded with the value
of the burst counter. A Mask Reset followed by a Counter Reset
resets the counter and mirror registers to 00000, as does master
reset (MRST).
Counter Load Operation
The address counter and mirror registers are both loaded with
the address value presented at the address lines.
Counter Increment Operation
When the address counter register is initially loaded with an
external address, the counter can internally increment the
address value, potentially addressing the entire memory array.
Only the unmasked bits of the counter register are incremented.
The corresponding bit in the mask register must be a ‘1’ for a
counter bit to change. The counter register is incremented by 1
if the least significant bit is unmasked, and by 2 if it is masked. If
all unmasked bits are ‘1,’ the next increment wraps the counter
back to the initially loaded value. If an Increment results in all the
unmasked bits of the counter being ‘1s,’ a counter interrupt flag
(CNTINT) is asserted. The next Increment returns the counter
register to its initial value, which was stored in the mirror register.
The counter address can instead be forced to loop to 00000 by
externally connecting CNTINT to CNTRST.[19] An increment that
results in one or more of the unmasked bits of the counter being
‘0’ deasserts the counter interrupt flag. The example in Figure 4
on page 10 shows the counter mask register loaded with a mask
value of 0003Fh unmasking the first 6 bits with bit ‘0’ as the LSB
and bit ‘16’ as the MSB. The maximum value the mask register
can be loaded with is 3FFFFh. Setting the mask register to this
value allows the counter to access the entire memory space. The
address counter is then loaded with an initial value of 8h. The
base address bits (in this case, the 6th address through the 16th
address) are loaded with an address value but do not increment
after the counter is configured for increment operation. The
counter address starts at address 8h. The counter increments its
internal address value until it reaches the mask register value of
3Fh. The counter wraps around the memory block to location 8h
at the next count. CNTINT is issued when the counter reaches
its maximum value
Counter Hold Operation
The value of all three registers can be constantly maintained
unchanged for an unlimited number of clock cycles. Such
operation is useful in applications where wait states are needed,
or when address is available a few cycles ahead of data in a
shared bus interface.
Counter Interrupt
The counter interrupt (CNTINT) is asserted LOW when an
increment operation results in the unmasked portion of the
counter register being all ‘1s.’ It is deasserted HIGH when an
Increment operation results in any other value. It is also
de-asserted by Counter Reset, Counter Load, Mask Reset and
Mask Load operations, and by MRST.
Counter Readback Operation
The internal value of the counter register can be read out on the
address lines. Readback is pipelined; the address is valid tCA2
after the next rising edge of the port’s clock. If address readback
occurs while the port is enabled (CE0 LOW and CE1 HIGH), the
data lines (DQs) are three-stated. Figure 3 on page 9 shows a
block diagram of the operation.
Table 3. Address Counter and Counter-Mask Register Control Operation (Any Port) [17, 18]
CLK
MRST
CNT/MSK
CNTRST
ADS
CNTEN
Operation
Description
X
L
X
X
X
X
Master Reset
Reset address counter to all 0s and mask
register to all 1s.
H
H
L
X
X
Counter Reset
Reset counter unmasked portion to all 0s.
H
H
H
L
L
Counter Load
Load counter with external address value
presented on address lines.
H
H
H
L
H
Counter Readback
Read out counter internal value on address
lines.
H
H
H
H
L
Counter Increment
Internally increment address counter value.
H
H
H
H
H
Counter Hold
Constantly hold the address value for multiple
clock cycles.
H
L
L
X
X
Mask Reset
Reset mask register to all 1s.
H
L
H
L
L
Mask Load
Load mask register with value presented on
the address lines.
H
L
H
L
H
Mask Readback
Read out mask register value on address
lines.
H
L
H
H
X
Reserved
Operation undefined
Notes
18. Counter operation and mask register operation is independent of chip enables.
19. CNTINT and CNTRST specs are guaranteed by design to operate properly at speed grade operating frequency when tied together.
Document #: 38-06059 Rev. *S
Page 7 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Retransmit
Mask Readback Operation
Retransmit is a feature that allows the Read of a block of memory
more than once without the need to reload the initial address.
This eliminates the need for external logic to store and route
data. It also reduces the complexity of the system design and
saves board space. An internal mirror register is used to store
the initially loaded address counter value. When the counter
unmasked portion reaches its maximum value set by the mask
register, it wraps back to the initial value stored in this mirror
register. If the counter is continuously configured in increment
mode, it increments again to its maximum value and wraps back
to the value initially stored into the mirror register. Thus, the
repeated access of the same data is allowed without the need
for any external logic.
The internal value of the mask register can be read out on the
address lines. Readback is pipelined; the address is valid tCM2
after the next rising edge of the port’s clock. If mask readback
occurs while the port is enabled (CE0 LOW and CE1 HIGH), the
data lines (DQs) is three-stated. Figure 3 on page 9 shows a
block diagram of the operation.
Mask Reset Operation
Counting by Two
When the least significant bit of the mask register is ‘0,’ the
counter increments by two. This may be used to connect the x18
devices as a 36-bit single port SRAM in which the counter of one
port counts even addresses and the counter of the other port
counts odd addresses. This even-odd address scheme stores
one half of the 36-bit data in even memory locations, and the
other half in odd memory locations.
The mask register is reset to all ‘1s,’ which unmasks every bit of
the counter. Master reset (MRST) also resets the mask register
to all ‘1s’.
Mask Load Operation
The mask register is loaded with the address value presented at
the address lines. Not all values permit correct increment operations. Permitted values are of the form 2n – 1 or 2n – 2. From the
most significant bit to the least significant bit, permitted values
have zero or more ‘0s,’ one or more ‘1s,’ or one ‘0.’ Thus 3FFFF,
003FE, and 00001 are permitted values, but 3F0FF, 003FC, and
00000 are not.
Document #: 38-06059 Rev. *S
Page 8 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Figure 3. Counter, Mask, and Mirror Logic Block Diagram [1]
CNT/MSK
CNTEN
Decode
Logic
ADS
CNTRST
MRST
Bidirectional
Address
Lines
Mask
Register
Counter/
Address
Register
Address
RAM
Decode
Array
CLK
From
Address
Lines
Load/Increment
17
Mirror
Counter
1
To Readback
and Address
Decode
1
0
From
Mask
Register
From
Mask
From
Counter
0
17
Increment
Logic
Wrap
17
17
17
Bit 0
17
+1
Wrap
Detect
1
+2
0
1
0
Document #: 38-06059 Rev. *S
Wrap
17
To
Counter
Page 9 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Figure 4. Programmable Counter-Mask Register Operation [2, 20]
Example:
Load
Counter-Mask
Register = 3F
CNTINT
H
0 0
0s
0 1 1
216 215
H
X X
Xs
216 215
Max
Address
Register
L
X X
H
X X
1
1
Unmasked Address
X 0 0
1
0
0
Xs
X 1 1
1
Mask
Register
bit-0
0
26 25 24 23 22 21 20
216 215
Max + 1
Address
Register
1
26 25 24 23 22 21 20
Masked Address
Load
Address
Counter = 8
1
1 1
Address
Counter
bit-0
1
26 25 24 23 22 21 20
Xs
216 215
IEEE 1149.1 Serial Boundary Scan (JTAG) [21]
The FLEx18 family devices incorporate an IEEE 1149.1 serial
boundary scan test access port (TAP). The TAP controller
functions in a manner that does not conflict with the operation of
other devices using 1149.1 compliant TAPs. The TAP operates
using JEDEC-standard 3.3V I/O logic levels. It is composed of
three input connections and one output connection required by
the test logic defined by the standard.
Performing a TAP Reset
A reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This reset does not affect the operation of the
devices, and may be performed while the device is operating. An
MRST must be performed on the devices after power up.
Performing a Pause/Restart
When a SHIFT-DR PAUSE-DR SHIFT-DR is performed the scan
chain outputs the next bit in the chain twice. For example, if the
value expected from the chain is 1010101, the device outputs a
11010101. This extra bit causes some testers to report an
erroneous failure for the devices in a scan test. Therefore the
tester should be configured to never enter the PAUSE-DR state.
X 0
0
1
0 0
0
26 25 24 23 22 21 20
Boundary Scan Hierarchy for 9-Mbit Device
Internally, the CY7C0833AV have two DIEs. Each DIE contain all
the circuitry required to support boundary scan testing. The
circuitry includes the TAP, TAP controller, instruction register,
and data registers. The circuity and operation of the DIE
boundary scan are described in detail below. The scan chain of
each DIE are connected serially to form the scan chain of the
CY7C0833AV as shown in Figure 5 on page 11. TMS and TCK
are connected in parallel to each DIE to drive all TAP controllers
in unison. In many cases, each DIE is supplied with the same
instruction. In other cases, it might be useful to supply different
instructions to each DIE. One example would be testing the
device ID of one DIE while bypassing the others.
Each pin of FLEx18 family is typically connected to multiple DIEs.
For connectivity testing with the EXTEST instruction, it is
desirable to check the internal connections between DIEs and
the external connections to the package. This is accomplished
by merging the netlist of the devices with the netlist of the user’s
circuit board. To facilitate boundary scan testing of the devices,
Cypress provides the BSDL file for each DIE, the internal netlist
of the device, and a description of the device scan chain. The
user can use these materials to easily integrate the devices into
the board’s boundary scan environment. Further information is
found in the Cypress application note Using JTAG Boundary
Scan For System in a Package (SIP) Dual-Port SRAMs.
Notes
20. The “X” in this diagram represents the counter upper bits
21. Boundary scan is IEEE 1149.1-compatible. See Performing a Pause/Restart on page 10 for deviation from strict 1149.1 compliance
Document #: 38-06059 Rev. *S
Page 10 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Figure 5. Scan Chain for 9 Mb Device
TDO
TDO
D2
TDI
TDO
D1
TDI
TDI
Table 4. Identification Register Definitions
Instruction Field
Value
Description
Revision Number (31:28)
0h
Cypress Device ID (27:12)
C090h
Reserved for version number.
Defines Cypress part number for CY7C0832AV/CY7C0832BV
C091h
Defines Cypress part number for CY7C0831AV
C093h
Defines Cypress part number for CY7C0830AV
C094h
Defines Cypress part number for CY7C0837AV.
Cypress JEDEC ID (11:1)
034h
Allows unique identification of the DP family device vendor.
ID Register Presence (0)
1
Indicates the presence of an ID register.
Table 5. Scan Registers Sizes
Register Name
Bit Size
Instruction
4
Bypass
1
Identification
32
Boundary Scan
n[22]
Table 6. Instruction Identification Codes
Instruction
Code
Description
EXTEST
0000
Captures the Input/Output ring contents. Places the BSR between the TDI and TDO.
BYPASS
1111
Places the BYR between TDI and TDO.
IDCODE
1011
Loads the IDR with the vendor ID code and places the register between TDI and TDO.
HIGHZ
0111
Places BYR between TDI and TDO. Forces all device output drivers to a High-Z state.
CLAMP
0100
Controls boundary to 1/0. Places BYR between TDI and TDO.
SAMPLE/PRELOAD
1000
Captures the input/output ring contents. Places BSR between TDI and TDO.
NBSRST
1100
Resets the non-boundary scan logic. Places BYR between TDI and TDO.
RESERVED
All other codes
Other combinations are reserved. Do not use other than the above.
Note
22. See details in the device BSDL file.
Document #: 38-06059 Rev. *S
Page 11 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
Exceeding maximum ratings[23] may impair the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage........................................... > 2000V
(JEDEC JESD22-A114-2000B)
Storage Temperature ................................. –65°C to +150°C
Latch Up Current .................................................... > 200 mA
Ambient Temperature with
Operating Range
Power Applied ............................................ –55°C to +125°C
Supply Voltage to Ground Potential................–0.5V to +4.6V
DC Voltage Applied to
Outputs in High-Z State ......................... –0.5V to VDD + 0.5V
Range
Ambient
Temperature
VDD
0°C to +70°C
3.3V±165 mV
–40°C to +85°C
3.3V±165 mV
Commercial
Industrial
DC Input Voltage .............................. –0.5V to VDD + 0.5V[24]
Electrical Characteristics
Over the Operating Range
Parameter
VOH
VOL
VIH
VIL
IOZ
IIX1
IIX2
ICC
ISB1[25]
ISB2[25]
ISB3[25]
ISB4[25]
ISB5
Description
Output HIGH Voltage (VDD = Min., IOH= –4.0 mA)
Output LOW Voltage (VDD = Min., IOL= +4.0 mA)
Input HIGH Voltage
Input LOW Voltage
Output Leakage Current
Input Leakage Current Except TDI, TMS, MRST
Input Leakage Current TDI, TMS, MRST
Operating Current for
CY7C0837AV
(VDD = Max., IOUT = 0 mA), Outputs CY7C0830AV
Disabled
CY7C0831AV
CY7C0832AV
CY7C0832BV
CY7C0833AV
Standby Current (Both Ports TTL Level)
CEL and CER ≥ VIH, f = fMAX
Standby Current (One Port TTL Level)
CEL | CER ≥ VIH, f = fMAX
Standby Current (Both Ports CMOS Level)
CEL and CER ≥ VDD – 0.2V, f = 0
Standby Current (One Port CMOS Level)
CEL | CER ≥ VIH, f = fMAX
Operating Current (VDD = Max, IOUT CY7C0833AV
= 0 mA, f = 0) Outputs Disabled
-167
-133
-100
Unit
Min Typ Max Min Typ Max Min Typ Max
2.4
2.4
2.4
V
0.4
0.4
0.4
V
2.0
2.0
2.0
V
0.8
0.8
0.8
V
–10
10 –10
10
–10
10
μA
–10
10 –10
10
–10
10
μA
–0.1
1.0 –0.1
1.0 –0.1
1.0 mA
225 300
225 300
mA
90
115
270
90
400
115
200
90
310
115
mA
mA
160
210
160
210
160
210
mA
55
75
55
75
55
75
mA
160
210
160
210
160
210
mA
70
100
70
100
mA
Capacitance
Part Number [26]
CY7C0837AV/CY7C0830AV/CY7C0831AV
CY7C0832AV/CY7C0832BV
CY7C0833AV
Parameter
Description
Input Capacitance
CIN
COUT
Output Capacitance
CIN
COUT
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C,
f = 1 MHz,
VDD = 3.3V
Max
13
Unit
pF
10
pF
22
20
pF
pF
Notes
23. The voltage on any input or I/O pin can not exceed the power pin during power up.
24. Pulse width < 20 ns.
25. ISB1, ISB2, ISB3 and ISB4 are not applicable for CY7C0833AV because it can not be powered down by using chip enable pins.
26. COUT also references CI/O.
Document #: 38-06059 Rev. *S
Page 12 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Figure 6. AC Test Load and Waveforms
3.3V
Z0 = 50Ω
R = 50Ω
R1 = 590 Ω
OUTPUT
OUTPUT
C = 10 pF
C = 5 pF
VTH = 1.5V
(a) Normal Load (Load 1)
R2 = 435 Ω
(b) Three-state Delay (Load 2)
3.0V
90%
ALL INPUT PULSES
10%
Vss
< 2 ns
90%
10%
< 2 ns
Switching Characteristics
Over the Operating Range
-167
Parameter
Description
CY7C0837AV
CY7C0830AV
CY7C0831AV
CY7C0832AV
Min
fMAX2
tCYC2
tCH2
tCL2
tR[27]
tF[27]
tSA
tHA
tSB
tHB
tSC
tHC
tSW
tHW
tSD
tHD
tSAD
tHAD
tSCN
tHCN
tSRST
tHRST
tSCM
Maximum Operating Frequency
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
Clock Rise Time
Clock Fall Time
Address Setup Time
Address Hold Time
Byte Select Setup Time
Byte Select Hold Time
Chip Enable Setup Time
Chip Enable Hold Time
R/W Setup Time
R/W Hold Time
Input Data Setup Time
Input Data Hold Time
ADS Setup Time
ADS Hold Time
CNTEN Setup Time
CNTEN Hold Time
CNTRST Setup Time
CNTRST Hold Time
CNT/MSK Setup Time
Max
167
6.0
2.7
2.7
2.0
2.0
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.3
-133
CY7C0837AV
CY7C0830AV
CY7C0831AV CY7C0833AV
CY7C0832AV
CY7C0832BV
Min
Max
Min
Max
133
133
7.5
7.5
3.0
3.0
3.0
3.0
2.0
2.0
2.0
2.0
2.5
2.5
0.6
0.6
2.5
2.5
0.6
0.6
2.5
NA
0.6
NA
2.5
2.5
0.6
0.6
2.5
2.5
0.6
0.6
2.5
NA
0.6
NA
2.5
NA
0.6
NA
2.5
NA
0.6
NA
2.5
NA
-100
CY7C0833AV
Min
Max
100
10
4.0
4.0
3.0
3.0
3.0
0.6
3.0
0.6
NA
NA
3.0
0.6
3.0
0.6
NA
NA
NA
NA
NA
NA
NA
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
27. Except JTAG signals (tr and tf < 10 ns [max.]).
Document #: 38-06059 Rev. *S
Page 13 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Switching Characteristics
(continued)
Over the Operating Range
-167
Parameter
Description
tHCM
CNT/MSK Hold Time
Output Enable to Data Valid
tOE
OE to Low Z
tOLZ[28,29]
tOHZ[28,29] OE to High Z
Clock to Data Valid
tCD2
Clock to Counter Address Valid
tCA2
tCM2
Clock to Mask Register Readback Valid
tDC
Data Output Hold After Clock HIGH
tCKHZ[28,29] Clock HIGH to Output High Z
tCKLZ[28, 29] Clock HIGH to Output Low Z
tSINT
Clock to INT Set Time
tRINT
Clock to INT Reset Time
tSCINT
Clock to CNTINT Set Time
tRCINT
Clock to CNTINT Reset time
Port to Port Delays
tCCS
Clock to Clock Skew
Master Reset Timing
tRS
Master Reset Pulse Width
tRS
Master Reset Setup Time
Master Reset Recovery Time
tRSR
tRSF
Master Reset to Outputs Inactive
tRSCNTINT
Master Reset to Counter Interrupt Flag
Reset Time
CY7C0837AV
CY7C0830AV
CY7C0831AV
CY7C0832AV
Min
0.6
Max
4.0
0
0
1.0
0
1.0
0.5
0.5
0.5
0.5
4.0
4.0
4.0
4.0
4.0
4.0
6.7
6.7
5.0
5.0
-133
CY7C0837AV
CY7C0830AV
CY7C0831AV CY7C0833AV
CY7C0832AV
CY7C0832BV
Min
Max
Min
Max
0.6
NA
4.4
4.7
0
0
4.4
4.7
4.4
4.7
4.4
NA
4.4
NA
1.0
1.0
0
4.4
4.7
1.0
4.4
1.0
4.7
0.5
7.5
0.5
7.5
0.5
7.5
0.5
7.5
0.5
5.7
NA
NA
0.5
5.7
NA
NA
-100
CY7C0833AV
Min
NA
Max
5.0
5.0
5.0
NA
NA
1.0
1.0
0.5
0.5
NA
NA
Unit
5.0
5.0
10
10
NA
NA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5.2
6.0
6.0
8.0
ns
7.0
6.0
6.0
7.5
6.0
7.5
7.5
6.0
7.5
10
8.5
10
ns
ns
ns
ns
ns
10.0
10.0
10.0
10.0
10.0
NA
10.0
NA
Notes
28. This parameter is guaranteed by design, but is not production tested.
29. Test conditions used are Load 2.
Document #: 38-06059 Rev. *S
Page 14 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
JTAG Timing and Switching Waveforms
Parameter
CY7C0837AV/CY7C0830AV
CY7C0831AV/CY7C0832AV
CY7C0832BV/CY7C0833AV
Description
Min
Unit
Max
fJTAG
Maximum JTAG TAP Controller Frequency
tTCYC
TCK Clock Cycle Time
100
tTH
TCK Clock HIGH Time
40
ns
tTL
TCK Clock LOW Time
40
ns
tTMSS
TMS Setup to TCK Clock Rise
10
ns
tTMSH
TMS Hold After TCK Clock Rise
10
ns
tTDIS
TDI Setup to TCK Clock Rise
10
ns
tTDIH
TDI Hold After TCK Clock Rise
10
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
10
ns
ns
30
0
MHz
ns
ns
Figure 7. JTAG Switching Waveform
tTH
Test Clock
TCK
tTMSS
tTL
tTCYC
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOX
tTDOV
Document #: 38-06059 Rev. *S
Page 15 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Switching Waveforms
Figure 8. Master Reset
tRS
MRST
ALL
ADDRESS/
DATA
LINES
tRSF
tRSS
ALL
OTHER
INPUTS
tRSR
INACTIVE
ACTIVE
TMS
CNTINT
INT
TDO
Figure 9. Read Cycle[12, 30, 31, 32, 33]
tCH2
tCYC2
tCL2
CLK
CE
tSC
tHC
tSB
tHB
tSW
tSA
tHW
tHA
tSC
tHC
BE0–BE1
R/W
ADDRESS
An
DATAOUT
An+1
1 Latency
An+2
tDC
tCD2
Qn
tCKLZ
An+3
Qn+1
tOHZ
Qn+2
tOLZ
OE
tOE
Notes
30. OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge.
31. ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH.
32. The output is disabled (high-impedance state) by CE = VIH following the next rising edge of the clock.
33. Addresses need not be accessed sequentially because ADS = CNTEN = VIL with CNT/MSK = VIH constantly loads the address on the rising edge of the CLK.
Numbers are for reference only.
Document #: 38-06059 Rev. *S
Page 16 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Switching Waveforms
(continued)
Figure 10. Bank Select Read[34, 35]
tCH2
tCYC2
tCL2
CLK
tHA
tSA
ADDRESS(B1)
A0
A1
A3
A2
A4
A5
tHC
tSC
CE(B1)
tCD2
tHC
tSC
tCD2
tHA
tSA
tDC
A0
ADDRESS(B2)
A1
tCKHZ
Q3
Q1
Q0
DATAOUT(B1)
tCD2
tCKHZ
tDC
tCKLZ
A3
A2
A4
A5
tHC
tSC
CE(B2)
tSC
tCD2
tHC
DATAOUT(B2)
tCKHZ
tCD2
Q4
Q2
tCKLZ
tCKLZ
Figure 11. Read-to-Write-to-Read (OE = LOW)[33, 36, 37, 38, 39]
tCH2
tCYC2
tCL2
CLK
CE
tSC
tHC
tSW
tHW
R/W
tSW
tHW
An
ADDRESS
tSA
DATAIN
An+1
An+2
An+2
An+3
An+4
tSD tHD
tHA
tCD2
tCKHZ
Dn+2
tCD2
Qn
DATAOUT
Qn+3
tCKLZ
READ
NO OPERATION
WRITE
READ
Notes
34. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress FLEx18 device from this data sheet. ADDRESS(B1)
= ADDRESS(B2).
35. ADS = CNTEN= BE0 – BE1 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.
36. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
37. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
38. CE0 = OE = BE0 – BE1 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
39. CE0 = BE0 – BE1 = R/W = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, because OE = LOW, the Write operation cannot be
completed (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.
Document #: 38-06059 Rev. *S
Page 17 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Switching Waveforms
(continued)
Figure 12. Read-to-Write-to-Read (OE Controlled)[33, 36, 38, 39]
tCH2
tCYC2
tCL2
CLK
CE
tSC
tHC
tSW tHW
R/W
tSW
tHW
An
An+1
An+2
An+3
An+4
An+5
ADDRESS
tSA
tHA
tSD tHD
Dn+2
DATAIN
Dn+3
tCD2
DATAOUT
tCD2
Qn
Qn+4
tOHZ
OE
READ
WRITE
READ
Figure 13. Read with Address Counter Advance[38]
tCH2
tCYC2
tCL2
CLK
tSA
ADDRESS
tHA
An
tSAD
tHAD
ADS
tSAD
tHAD
tSCN
tHCN
CNTEN
tSCN
DATAOUT
tHCN
Qx–1
READ
EXTERNAL
ADDRESS
Document #: 38-06059 Rev. *S
tCD2
Qx
Qn
tDC
READ WITH COUNTER
Qn+1
COUNTER HOLD
Qn+2
Qn+3
READ WITH COUNTER
Page 18 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Switching Waveforms
(continued)
Figure 14. Write with Address Counter Advance[39]
tCH2
tCYC2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL
ADDRESS
An
tSAD
tHAD
tSCN
tHCN
An+1
An+2
An+3
An+4
ADS
CNTEN
Dn
DATAIN
tSD
Dn+1
tHD
WRITE EXTERNAL
ADDRESS
Dn+1
WRITE WITH
COUNTER
Dn+2
Dn+3
WRITE COUNTER
HOLD
Figure 15. Counter
Dn+4
WRITE WITH COUNTER
Reset[40, 41]
tCYC2
tCH2
tCL2
CLK
tSA
INTERNAL
ADDRESS
Ax
tHW
tSD
tHD
An
1
0
tSW
Ap
Am
An
ADDRESS
tHA
Ap
Am
R/W
ADS
CNTEN
tSRST tHRST
CNTRST
DATAIN
D0
tCD2
tCD2
DATAOUT [42]
Q0
COUNTER
RESET
WRITE
ADDRESS 0
tCKLZ
READ
ADDRESS 0
READ
ADDRESS 1
Q1
READ
ADDRESS An
Qn
READ
ADDRESS Am
Notes
40. CE0 = BE0 – BE1 = LOW; CE1 = MRST = CNT/MSK = HIGH.
41. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset.
42. Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value.
Document #: 38-06059 Rev. *S
Page 19 of 28
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CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Switching Waveforms
(continued)
Figure 16. Readback State of Address Counter or Mask Register[43, 44, 45, 46]
tCYC2
tCH2 tCL2
CLK
tCA2 or tCM2
tSA tHA
EXTERNAL
ADDRESS
A0–A16
An*
An
INTERNAL
ADDRESS
An+1
An
An+2
An+4
An+3
tSAD tHAD
ADS
tSCN tHCN
CNTEN
tCD2
DATAOUT
Qx-2
LOAD
EXTERNAL
ADDRESS
tCKHZ
Qx-1
Qn
READBACK
COUNTER
INTERNAL
ADDRESS
INCREMENT
tCKLZ
Qn+1
Qn+2
Qn+3
Notes
43. CE0 = OE = BE0 – BE1 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
44. Address in output mode. Host must not be driving address bus after tCKLZ in next clock cycle.
45. Address in input mode. Host can drive address bus after tCKHZ.
46. An * is the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines.
Document #: 38-06059 Rev. *S
Page 20 of 28
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CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Switching Waveforms
(continued)
Figure 17. Left_Port (L_Port) Write to Right_Port (R_Port) Read[47, 48, 49]
tCH2
tCYC2
tCL2
CLKL
tHA
tSA
L_PORT
ADDRESS
An
tSW
tHW
R/WL
tCKHZ
tSD
L_PORT
DATAIN
CLKR
tHD
tCKLZ
Dn
tCYC2
tCL2
tCCS
tCH2
tSA
R_PORT
ADDRESS
tHA
An
R/WR
tCD2
R_PORT
Qn
DATAOUT
tDC
Notes
47. CE0 = OE = ADS = CNTEN = BE0 – BE1 = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH.
48. This timing is valid when one port is writing, and other port is reading the same location at the same time. If tCCS is violated, indeterminate data is Read out.
49. If tCCS < minimum specified value, then R_Port is Read the most recent data (written by L_Port) only (2 * tCYC2 + tCD2) after the rising edge of R_Port's clock. If tCCS
> minimum specified value, then R_Port is Read the most recent data (written by L_Port) (tCYC2 + tCD2) after the rising edge of R_Port's clock.
Document #: 38-06059 Rev. *S
Page 21 of 28
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CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Switching Waveforms
(continued)
Figure 18. Counter Interrupt and Retransmit [15, 42, 50, 51, 52, 53]
tCH2
tCYC2
tCL2
CLK
tSCM
tHCM
CNT/MSK
ADS
CNTEN
COUNTER
INTERNAL
ADDRESS
3FFFC
3FFFD
3FFFE
tSCINT
3FFFF
Last_Loaded
Last_Loaded +1
tRCINT
CNTINT
Notes
50. CE0 = OE = BE0 – BE1 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
51. CNTINT is always driven.
52. CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value.
53. The mask register assumed to have the value of 3FFFFh.
Document #: 38-06059 Rev. *S
Page 22 of 28
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CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Switching Waveforms
(continued)
Figure 19. MailBox Interrupt Timing [54, 55, 56, 57, 58]
tCH2
tCYC2
tCL2
CLKL
tSA
L_PORT
ADDRESS
tHA
7FFFF
An+1
An
An+2
An+3
tSINT
tRINT
INTR
tCH2
tCYC2
tCL2
CLKR
tSA
R_PORT
ADDRESS
tHA
Am+1
Am
7FFFF
Am+3
Am+4
Table 7. Read/Write and Enable Operation (Any Port) [2, 17, 59, 60, 61]
Inputs
OE
Operation
CE0
CE1
R/W
DQ0 – DQ17
X
H
X
X
High-Z
Deselected
X
X
L
X
High-Z
Deselected
X
L
H
L
DIN
Write
L
L
H
H
DOUT
Read
L
H
X
High-Z
Outputs Disabled
H
CLK
Outputs
X
Notes
54. CE0 = OE = ADS = CNTEN = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH.
55. Address “7FFFF” is the mailbox location for R_Port of the 9Mb device.
56. L_Port is configured for Write operation, and R_Port is configured for Read operation.
57. At least one byte enable (BE0 – BE1) is required to be active during interrupt operations.
58. Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock.
59. OE is an asynchronous input signal.
60. When CE changes state, deselection and Read happen after one cycle of latency.
61. CE0 = OE = LOW; CE1 = R/W = HIGH.
Document #: 38-06059 Rev. *S
Page 23 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Ordering Information
512K × 18 (9M) 3.3V Synchronous CY7C0833AV Dual-Port SRAM
Speed
(MHz)
133
100
Ordering Code
Package
Diagram
Package Type
Operating
Range
CY7C0833AV-133BBC
51-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
Commercial
CY7C0833AV-133BBI
51-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
Industrial
CY7C0833AV-100BBC
51-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
Commercial
CY7C0833AV-100BBI
51-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
Industrial
256K × 18 (4M) 3.3V Synchronous CY7C0832AV/CY7C0832BV Dual-Port SRAM
Speed
(MHz)
167
Ordering Code
Package
Diagram
CY7C0832AV-167BBC
51-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
CY7C0832AV-167AC
51-85100 120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm)
CY7C0832AV-167AXC
133
Package Type
Operating
Range
Commercial
120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm) (Pb-Free)
CY7C0832AV-133BBC
51-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
CY7C0832AV-133AC
51-85100 120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm)
CY7C0832AV-133AXC
Commercial
120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm) (Pb-Free)
CY7C0832AV-133BBI
51-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
CY7C0832BV-133AI
51-85100 120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm)
CY7C0832AV-133AXI
Industrial
120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm) (Pb-Free)
128K × 18 (2M) 3.3V Synchronous CY7C0831AV Dual-Port SRAM
Speed
(MHz)
167
Ordering Code
Package
Diagram
CY7C0831AV-167BBC
51-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
CY7C0831AV-167AC
51-85100 120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm)
CY7C0831AV-167AXC
133
Package Type
CY7C0831AV-133BBC
51-85100 120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm)
120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm) (Pb-Free)
51-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
CY7C0831AV-133BBXI
CY7C0831AV-133AI
Commercial
144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch (Pb-Free)
CY7C0831AV-133AXC
CY7C0831AV-133BBI
Commercial
120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm) (Pb-Free)
51-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
CY7C0831AV-133BBXC
CY7C0831AV-133AC
Operating
Range
Industrial
144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch (Pb-Free)
51-85100 120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm)
CY7C0831AV-133AXI
120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm) (Pb-Free)
64K × 18 (1M) 3.3V Synchronous CY7C0830AV Dual-Port SRAM
Speed
(MHz)
167
133
Ordering Code
Package
Diagram
Package Type
CY7C0830AV-167BBC
51-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
CY7C0830AV-167AC
51-85100 120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm)
CY7C0830AV-133BBC
51-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
CY7C0830AV-133AC
51-85100 120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm)
CY7C0830AV-133BBI
51-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
CY7C0830AV-133AI
51-85100 120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm)
Document #: 38-06059 Rev. *S
Operating
Range
Commercial
Commercial
Industrial
Page 24 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Ordering Information
32K × 18 (512K) 3.3V Synchronous CY7C0837AV Dual-Port SRAM
Speed
(MHz)
Ordering Code
Package
Diagram
Operating
Range
Package Type
167
CY7C0837AV-167BBC
51-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
Commercial
133
CY7C0837AV-133BBC
51-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
Commercial
CY7C0837AV-133BBI
51-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
Industrial
Package Diagrams
Figure 20. 144-Ball FBGA (13 x 13 x 1.6 mm) (51-85141)
TOP VIEW
BOTTOM VIEW
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
+0.10
Ø0.50 (144X)
-0.05
2 3 4 5 6 7 8 9 10 11 12
12 11 10 9 8 7 6 5 4 3
2 1
1.00
A
B
C
D
E
F
G
H
J
K
L
M
5.50
13.00±0.10
13.00±0.10
A
11.00
1
A
B
C
D
E
F
G
H
J
K
L
M
5.50
A
1.00
13.00±0.10
B
11.00
0.15 C
1.60MAX.
0.70±0.05
//
0.25 C
B
0.15(4X)
13.00±0.10
DIMENSIONS IN MILLIMETERS
REFERENCE JEDEC: PUBLICATION 95
DESIGN GUIDE 4.14D
PKG. WEIGHT: 0.53 gms
C
Document #: 38-06059 Rev. *S
0.40±0.05
0.36
SEATING PLANE
51-85141-*B
Page 25 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Package Diagrams
Figure 21. 120-Pin Thin Quad Flatpack (14 x 14 x 1.4 mm) (51-85100)
51-85100-**
Document #: 38-06059 Rev. *S
Page 26 of 28
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CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Document History Page
Document Title: CY7C0837AV/CY7C0830AV/CY7C0831AV/CY7C0832AV/CY7C0832BV/CY7C0833AV, FLEx18™ 3.3V
64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM
Document Number: 38-06059
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
**
111473
DSG
11/27/01
Change from Spec number: 38-01056 to 38-06059
*A
111942
JFU
12/21/01
Updated capacitance values
Updated switching parameters and ISB3
Updated “Read-to-Write-to-Read (OE Controlled)” waveform
Revised static discharge voltage
Revised footnote regarding ISB3
*B
113741
KRE
04/02/02
Updated Isb values
Updated ESD voltage
Corrected 0853 pins L3 and L12
*C
114704
KRE
04/24/02
Added discussion of Pause/Restart for JTAG boundary scan
*D
115336
KRE
07/01/02
Revised speed offerings for all densities
*E
122307
RBI
12/27/02
Power up requirements added to Maximum Ratings Information
*F
123636
KRE
1/27/03
Revise tcd2, tOE, tOHZ, tCKHZ, tCKLZ for the CY7C0853V to 4.7 ns
*G
126053
SPN
08/11/03
Separated out 4M and 9M data sheets
Updated Isb and ICC values
*H
129443
RAZ
11/03/03
Updated Isb and ICC values
*I
231993
YDT
See ECN
Removed “A particular port can write to a certain location while another port is
reading that location.” from Functional Description.
*J
231813
WWZ
See ECN
Removed x36 devices (CY7C0852/CY7C0851) from this datasheet. Added
0.5M, 1M and 9M x18 devices to it. Changed title to FLEx18 3.3V
32K/64K/128K/256K/512K x18 Synchronous Dual-Port RAM. Changed
datasheet to accommodate the removals and additions. Removed general
JTAG description. Updated JTAG ID codes for all devices. Added 144FBGA
package for all devices. Updated selection guide table and moved to the front
page. Updated block diagram to reflect x18 configuration. Added preliminary
status back due to the addition of the new devices.
*K
311054
RYQ
See ECN
Minor Change: Correct the revision indicated on the footer.
*L
329111
SPN
See ECN
Updated Marketing part numbers
Updated tRSF
*M
330561
RUY
See ECN
Added Byte Select Operation Table
*N
375198
YDT
See ECN
Removed Preliminary status
Added ISB5
Changed tRSCNTINT to 10ns
*O
391525
SPN
See ECN
Updated Counter reset section to reflect what is loaded into the mirror register
*P
414109
LIJ
See ECN
Corrected Ordering Codes for 0831 devices in the 133 Mhz speed bin.
Added CY7C0833AV-133BBI.
*Q
461113
YDT
SEE ECN
Changed VDDIO to VDD (typo)
Added lead(Pb)-free parts
Corrected typo in DC table
*R
2544945
VKN/AESA
07/29/08
Updated Template. Updated ordering information
*S
2668478
VKN/PYRS
02/04/09
Added CY7C0832BV part
Added footnote #1
Updated Ordering information table
Document #: 38-06059 Rev. *S
Page 27 of 28
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CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
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© Cypress Semiconductor Corporation, 2001-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-06059 Rev. *S
Revised March 03, 2009
Page 28 of 28
FLEx18 is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders.
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