CY7C093794V CY7C093894V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM
CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V
FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
Features
• True dual-ported memory cells that allow simultaneous access of the same memory location • Synchronous pipelined operation • Organization of 1-Mbit, 2-Mbit, 4-Mbit and 9-Mbit devices • Pipelined output mode allows fast operation • 0.18-micron CMOS for optimum speed and power • High-speed clock to data access • 3.3V low power — Active as low as 225 mA (typ) • • • • • • • • — Standby as low as 55 mA (typ) Mailbox function for message passing Global master reset Separate byte enables on both ports Commercial and industrial temperature ranges IEEE 1149.1-compatible JTAG boundary scan 172-ball FBGA (1 mm pitch) (15 mm × 15 mm) 176-pin TQFP (24 mm × 24 mm × 1.4 mm) Counter wrap around control — Internal mask register controls counter wrap-around — Counter-interrupt flags to indicate wrap-around — Memory block retransmit operation • Counter readback on address lines • Mask register readback on address lines • Dual Chip Enables on both ports for easy depth expansion
Functional Description
The FLEx36 family includes 1M, 2M, 4M and 9M pipelined, synchronous, true dual-port static RAMs that are high-speed, low-power 3.3V CMOS. Two ports are provided, permitting independent, simultaneous access to any location in memory. The result of writing to the same location by more than one port at the same time is undefined. Registers on control, address, and data lines allow for minimal set-up and hold time. During a Read operation, data is registered for decreased cycle time. Each port contains a burst counter on the input address register. After externally loading the counter with the initial address, the counter will increment the address internally (more details to follow). The internal Write pulse width is independent of the duration of the R/W input signal. The internal Write pulse is self-timed to allow the shortest possible cycle times. A HIGH on CE0 or LOW on CE1 for one clock cycle will power down the internal circuitry to reduce the static power consumption. One cycle with chip enables asserted is required to reactivate the outputs. Additional features include: readback of burst-counter internal address value on address lines, counter-mask registers to control the counter wrap-around, counter interrupt (CNTINT) flags, readback of mask register value on address lines, retransmit functionality, interrupt flags for message passing, JTAG for boundary scan, and asynchronous Master Reset (MRST). The CY7C0853 device in this family has limited features. Please see See “Address Counter and Mask Register Operations[10]” on page 8. for details.
Table 1. Product Selection Guide Density Part Number Max. Speed (MHz) Max. Access Time - clock to Data (ns) Typical operating current (mA) Package
1-Mbit (32K x 36) CY7C0850V 167 4.0 225 176TQFP 172FBGA 2-Mbit (64K x 36) CY7C0851V 167 4.0 225 176TQFP 172FBGA 4-Mbit (128K x 36) CY7C0852V 167 4.0 225 176TQFP 172FBGA 9-Mbit (256K x 36) CY7C0853V 133 4.7 270 172FBGA
Cypress Semiconductor Corporation Document #: 38-06070 Rev. *D
•
3901 North First Street
•
San Jose, CA 95134
• 408-943-2600 Revised June 24, 2004
CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V
Logic Block Diagram[1]
OEL R/WL B0L B1L B2L B3L CE0L CE1L OER R/WR B0R B1R B2R B3R CE0R CE1R
DQ27L–DQ35L DQ18L–DQ26L DQ9L–DQ17L DQ0L–DQ8L
9 9 9 9
9 9
DQ27R–DQ35R DQ18R–DQ26R DQ9R–DQ17R DQ0R–DQ8R
I/O Control
I/O Control
9 9
Addr. Read Back
True Dual-Ported RAM Array
Addr. Read Back
A0L–A17L CNT/MSKL ADSL CNTENL CNTRSTL CLKL CNTINTL
18
18
Mask Register Counter/ Address Register Mirror Reg TMS TDI TCK
Mask Register Counter/ Address Register Mirror Reg
A0R–A17R CNT/MSKR ADS CNTEN CNTRSTR CLKR CNTINTR
Address Decode
Address Decode
INTL
Interrupt Logic
MRST
Reset Logic
JTAG
TDO
Interrupt Logic
INTR
Note: 1. , 9M device has 18 address bits, 4M device has 17 address bits, 2M device has 16 address bits, and 1M device has 15 address bits.
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CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V
Pin Configurations
172-ball BGA Top View
1 A B C D E F G H J K L M N P
DQ32L
2
DQ30L
3
CNTINTL
4
VSS
5
DQ13L
6
VDD
7
DQ11L
8
DQ11R
9
VDD
10
DQ13R
11
VSS
12
CNTINTR
13
DQ30R
14
DQ32R
A0L
DQ33L
DQ29L
DQ17L
DQ14L
DQ12L
DQ9L
DQ9R
DQ12R
DQ14R
DQ17R
DQ29R
DQ33R
A0R
NC
A1L
DQ31L
DQ27L
INTL
DQ15L
DQ10L
DQ10R
DQ15R
INTR
DQ27R
DQ31R
A1R
NC
A2L
A3L
DQ35L
DQ34L
DQ28L
DQ16L
VSS
VSS
DQ16R
DQ28R
DQ34R
DQ35R
A3R
A2R
A4L
A5L
CE1L
B0L
VDD
VSS
VDD
VDD
B0R
CE1R
A5R
A4R
VDD
A6L
A7L
B1L
VDD
VSS
B1R
A7R
A6R
VDD
OEL
B2L
B3L
CE0L
VSS
R/WL
A8L
CLKL
CY7C0850V CY7C0851V CY7C0852V
VSS VDD
CE0R
B3R
B2R
OER
CLKR
A8R
R/WR
VSS
A9L
A10L
VSS
ADSL
ADSR
MRST
A10R
A9R
A11L
A12L
A15L[2]
CNTRSTL
VDD
VDD
VSS
VDD
CNTRSTR
A15R[2]
A12R
A11R
CNT/MSKL
A13L
CNTENL
DQ26L
DQ25L
DQ19L
VSS
VSS
DQ19R
DQ25R
DQ26R
CNTENR
A13R
CNT/MSKR
A16L[2]
A14L
DQ22L
DQ18L
TDI
DQ7L
DQ2L
DQ2R
DQ7R
TCK
DQ18R
DQ22R
A14R
A16R[2]
DQ24L
DQ20L
DQ8L
DQ6L
DQ5L
DQ3L
DQ0L
DQ0R
DQ3R
DQ5R
DQ6R
DQ8R
DQ20R
DQ24R
DQ23L
DQ21L
TDO
VSS
DQ4L
VDD
DQ1L
DQ1R
VDD
DQ4R
VSS
TMS
DQ21R
DQ23R
Note: 2. For CY7C0851V, pins M1 and M14 are NC. For CY7C0850V, pins K3, K12 M1, and M14 are NC
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CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V
Pin Configurations (continued)
172-ball BGA Top View
1 A B C D E F G H J K L M N P
DQ32L
2
DQ30L
3
NC
4
VSS
5
DQ13L
6
VDD
7
DQ11L
8
DQ11R
9
VDD
10
DQ13R
11
VSS
12
NC
13
DQ30R
14
DQ32R
A0L
DQ33L
DQ29L
DQ17L
DQ14L
DQ12L
DQ9L
DQ9R
DQ12R
DQ14R
DQ17R
DQ29R
DQ33R
A0R
A17L
A1L
DQ31L
DQ27L
INTL
DQ15L
DQ10L
DQ10R
DQ15R
INTR
DQ27R
DQ31R
A1R
A17R
A2L
A3L
DQ35L
DQ34L
DQ28L
DQ16L
VSS
VSS
DQ16R
DQ28R
DQ34R
DQ35R
A3R
A2R
A4L
A5L
VDD
B0L
VDD
VSS
VDD
VDD
B0R
VDD
A5R
A4R
VDD
A6L
A7L
B1L
VDD
VSS
B1R
A7R
A6R
VDD
OEL
B2L
B3L
VSS
CY7C0853V
VSS
B3R
B2R
OER
VSS
R/WL
A8L
CLKL
CLKR
A8R
R/WR
VSS
A9L
A10L
VSS
VSS
VSS
VDD
VSS
MRST
A10R
A9R
A11L
A12L
A15L
VDD
VDD
VDD
VSS
VDD
VDD
A15R
A12R
A11R
VDD
A13L
VSS
DQ26L
DQ25L
DQ19L
VSS
VSS
DQ19R
DQ25R
DQ26R
VSS
A13R
VDD
A16L
A14L
DQ22L
DQ18L
TDI
DQ7L
DQ2L
DQ2R
DQ7R
TCK
DQ18R
DQ22R
A14R
A16R
DQ24L
DQ20L
DQ8L
DQ6L
DQ5L
DQ3L
DQ0L
DQ0R
DQ3R
DQ5R
DQ6R
DQ8R
DQ20R
DQ24R
DQ23L
DQ21L
TDO
VSS
DQ4L
VDD
DQ1L
DQ1R
VDD
DQ4R
VSS
TMS
DQ21R
DQ23R
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CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V
Pin Configurations (continued)
176-pin Thin Quad Flat Pack (TQFP) Top View
DQ11R DQ12R DQ17R DQ15R DQ10R VSS DQ13R DQ14R DQ16R DQ15L DQ17L DQ13L VSS DQ16L DQ14L DQ12L DQ11L DQ10L DQ9L DQ9R VDD VDD
CNTINTR INTR
INTL CNTINTL
DQ29R DQ28R
DQ27R
DQ30R
174 173
171 170
168 167
165 164
162 161
159 158
156 155
153 152
150 149
145 144
142 141
139 138
136 135 134
DQ31R
DQ31L
DQ30L
DQ27L
148 147
176 175
146
143
140
172
169
166
163
160
157
154
151
137
133
DQ32R DQ33R
DQ33L DQ32L
DQ28L DQ29L
VDD VSS
VSS VDD
DQ34L DQ35L NC A0L A1L A2L A3L VSS VDD A4L A5L A6L A7L B0L B1L CE1L B2L B3L OEL CE0L VDD VDD VSS VSS R/WL CLKL VSS ADSL CNTENL CNTRSTL CNT/MSKL A8L A9L A10L A11L A12L VSS VDD A13L A15L[2] A16L[2] DQ24L DQ20L A14L
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115
DQ34R DQ35R NC A0R A1R A2R A3R VSS VDD A4R A5R A6R A7R B0R B1R CE1R B2R B3R OER CE0R VDD VDD VSS VSS R/WR CLKR MRST ADSR CNTENR CNTRSTR CNT/MSKR A8R A9R A10R A11R A12R VSS VDD A13R A15R[2] A16R[2] DQ24R DQ20R A14R
CY7C0850V CY7C0851V CY7C0852V
114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 85 86 87 DQ22R 76 77
65 66
53 54
47 48
50 51
56 57
59 60
62 63
71 72
68 69
45 46
73 74
79 80
82 83
61
49
52
55
58
64
67
70
75
78
DQ19R DQ25R
84
81
DQ18R
DQ21R
DQ22L
DQ21L
DQ18L
DQ1R
DQ5R
DQ8R
DQ8L
DQ5L
DQ1L
TMS TCK
VDD
Document #: 38-06070 Rev. *D
VDD
DQ23R DQ26R
DQ26L DQ23L
DQ25L DQ19L
DQ2R DQ3R
DQ6R DQ7R
DQ0L DQ0R
VSS DQ4R
DQ7L DQ6L
DQ4L VSS
DQ3L DQ2L
TDI TDO
VDD VSS
VSS VDD
88
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CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V
Pin Definitions
Left Port A0L–A17L ADSL[3] CE0L[3] CE1L[3] CLKL CNTENL[3] CNTRSTL[3] CNT/MSKL[3] DQ0L–DQ35L OEL INTL CNTINTL[3] R/WL B0L–B3L MRST TMS TDI TCK TDO VSS VDD
[1]
Right Port A0R–A17R ADSR[3] CE0R[3] CE1R[3] CLKR CNTENR[3] CNTRSTR[3] CNT/MSKR[3] DQ0R–DQ35R OER INTR CNTINTR[3] R/WR B0R–B3R
[1]
Description Address Inputs. Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW for the part using the externally supplied address on the address pins and for loading this address into the burst address counter. Active LOW Chip Enable Input. Active HIGH Chip Enable Input. Clock Signal. Maximum clock input rate is fMAX. Counter Enable Input. Asserting this signal LOW increments the burst address counter of its respective port on each rising edge of CLK. The increment is disabled if ADS or CNTRST are asserted LOW. Counter Reset Input. Asserting this signal LOW resets to zero the unmasked portion of the burst address counter of its respective port. CNTRST is not disabled by asserting ADS or CNTEN. Address Counter Mask Register Enable Input. Asserting this signal LOW enables access to the mask register. When tied HIGH, the mask register is not accessible and the address counter operations are enabled based on the status of the counter control signals. Data Bus Input/Output. Output Enable Input. This asynchronous signal must be asserted LOW to enable the DQ data pins during Read operations. Mailbox Interrupt Flag Output. The mailbox permits communications between ports. The upper two memory locations can be used for message passing. INTL is asserted LOW when the right port writes to the mailbox location of the left port, and vice versa. An interrupt to a port is deasserted HIGH when it reads the contents of its mailbox. Counter Interrupt Output. This pin is asserted LOW when the unmasked portion of the counter is incremented to all “1s.” Read/Write Enable Input. Assert this pin LOW to write to, or HIGH to Read from the dual port memory array. Byte Select Inputs. Asserting these signals enables Read and Write operations to the corresponding bytes of the memory array. Master Reset Input. MRST is an asynchronous input signal and affects both ports. Asserting MRST LOW performs all of the reset functions as described in the text. A MRST operation is required at power-up. JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State machine transitions occur on the rising edge of TCK. JTAG Test Data Input. Data on the TDI input will be shifted serially into selected registers. JTAG Test Clock Input. JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally three-stated except when captured data is shifted out of the JTAG TAP. Ground Inputs. Power Inputs.
Note: 3. These pins are not available for CY7C0853V device.
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CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V
Master Reset
The FLEx36 family devices undergo a complete reset by taking its MRST input LOW. The MRST input can switch asynchronously to the clocks. The MRST initializes the internal burst counters to zero, and the counter mask registers to all ones (completely unmasked). The MRST also forces the Mailbox Interrupt (INT) flags and the Counter Interrupt (CNTINT) flags HIGH. The MRST must be performed on the FLEx36 family devices after power-up. shows that in order to set the INTR flag, a Write operation by the left port to address 3FFFF will assert INTR LOW. At least one byte has to be active for a Write to generate an interrupt. A valid Read of the 3FFFF location by the right port will reset INTR HIGH. At least one byte has to be active in order for a Read to reset the interrupt. When one port Writes to the other port’s mailbox, the INT of the port that the mailbox belongs to is asserted LOW. The INT is reset when the owner (port) of the mailbox Reads the contents of the mailbox. The interrupt flag is set in a flow-thru mode (i.e., it follows the clock edge of the writing port). Also, the flag is reset in a flow-thru mode (i.e., it follows the clock edge of the reading port). Each port can read the other port’s mailbox without resetting the interrupt. And each port can write to its own mailbox without setting the interrupt. If an application does not require message passing, INT pins should be left open.
Mailbox Interrupts
The upper two memory locations may be used for message passing and permit communications between ports. Table 2 shows the interrupt operation for both ports of CY7C0853V. The highest memory location, 3FFFF is the mailbox for the right port and 3FFFE is the mailbox for the left port. Table 2 Table 2. Interrupt Operation Example [1, 4, 5, 6, 7] Left Port Function Set Right INTR Flag Reset Right INTR Flag Set Left INTL Flag Reset Left INTL Flag R/WL L X X H CEL L X X L A0L–17L 3FFFF X X 3FFFE
Right Port INTL X X L H R/WR X H L X CER X L L X A0R–17R X 3FFFF 3FFFE X INTR L H X X
Table 3. Address Counter and Counter-Mask Register Control Operation (Any Port) [8, 9] CLK X MRST L H H H H H H H H H CNT/MSK X H H H H H L L L L CNTRST X L H H H H L H H H ADS X X L L H H X L L H CNTEN X X L H L H X L H X Operation Master Reset Counter Reset Counter Load Description Reset address counter to all 0s and mask register to all 1s. Reset counter unmasked portion to all 0s. Load counter with external address value presented on address lines.
Counter Readback Read out counter internal value on address lines. Counter Increment Internally increment address counter value. Counter Hold Mask Reset Mask Load Mask Readback Reserved Constantly hold the address value for multiple clock cycles. Reset mask register to all 1s. Load mask register with value presented on the address lines. Read out mask register value on address lines. Operation undefined
Notes: 4. CE is internal signal. CE = LOW if CE0 = LOW and CE1 = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK and can be deasserted after that. Data will be out after the following CLK edge and will be three-stated after the next CLK edge. 5. OE is “Don’t Care” for mailbox operation. 6. At least one of B0, B1, B2, or B3 must be LOW. 7. A16x is a NC for CY7C0851V, therefore the Interrupt Addresses are FFFF and EFFF; A16x and A15x are NC for CY7C0850V, therefore the Interrupt Addresses are 7FFF and 6FFF. 8. “X” = “Don’t Care,” “H” = HIGH, “L” = LOW. 9. Counter operation and mask register operation is independent of chip enables.
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CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V
Address Counter and Mask Register Operations[10]
This section describes the features only apply to CY7C0850V/CY7C0851V/CY7C0852V devices, but not to CY7C0853 device. Each port of these devices has a programmable burst address counter. The burst counter contains three registers: a counter register, a mask register, and a mirror register. The counter register contains the address used to access the RAM array. It is changed only by the Counter Load, Increment, Counter Reset, and by master reset (MRST) operations. The mask register value affects the Increment and Counter Reset operations by preventing the corresponding bits of the counter register from changing. It also affects the counter interrupt output (CNTINT). The mask register is changed only by the Mask Load and Mask Reset operations, and by the MRST. The mask register defines the counting range of the counter register. It divides the counter register into two regions: zero or more “0s” in the most significant bits define the masked region, one or more “1s” in the least significant bits define the unmasked region. Bit 0 may also be “0,” masking the least significant counter bit and causing the counter to increment by two instead of one. The mirror register is used to reload the counter register on increment operations (see “retransmit,” below). It always contains the value last loaded into the counter register, and is changed only by the Counter Load, and Counter Reset operations, and by the MRST. Table 3 summarizes the operation of these registers and the required input control signals. The MRST control signal is asynchronous. All the other control signals in Table 3 (CNT/MSK, CNTRST, ADS, CNTEN) are synchronized to the port’s CLK. All these counter and mask operations are independent of the port’s chip enable inputs (CE0 and CE1). Counter enable (CNTEN) inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast, interleaved memory applications. A port’s burst counter is loaded when the port’s address strobe (ADS) and CNTEN signals are LOW. When the port’s CNTEN is asserted and the ADS is deasserted, the address counter will increment on each LOW to HIGH transition of that port’s clock signal. This will Read/Write one word from/into each successive address location until CNTEN is deasserted. The counter can address the entire memory array, and will loop back to the start. Counter reset (CNTRST) is used to reset the unmasked portion of the burst counter to 0s. A counter-mask register is used to control the counter wrap. Counter Reset Operation All unmasked bits of the counter and mirror registers are reset to “0.” All masked bits remain unchanged. A Mask Reset followed by a Counter Reset will reset the counter and mirror registers to 00000, as will master reset (MRST).
Notes: 10. This section describes the CY7C0852V, which have 17 address bits and a maximum address value of 1FFFF. The CY7C0851V has 16 address bits, register lengths of 16 bits, and a maximum address value of FFFF. The CY7C0850V has 15 address bits, register lengths of 15 bits, and a maximum address value of 7FFF 11. CNTINT and CNTRST specs are guaranteed by design to operate properly at speed grade operating frequency when tied together.
Counter Load Operation The address counter and mirror registers are both loaded with the address value presented at the address lines. Counter Readback Operation The internal value of the counter register can be read out on the address lines. Readback is pipelined; the address will be valid tCA2 after the next rising edge of the port’s clock. If address readback occurs while the port is enabled (CE0 LOW and CE1 HIGH), the data lines (DQs) will be three-stated. Figure 1 shows a block diagram of the operation. Counter Increment Operation Once the address counter register is initially loaded with an external address, the counter can internally increment the address value, potentially addressing the entire memory array. Only the unmasked bits of the counter register are incremented. The corresponding bit in the mask register must be a “1” for a counter bit to change. The counter register is incremented by 1 if the least significant bit is unmasked, and by 2 if it is masked. If all unmasked bits are “1,” the next increment will wrap the counter back to the initially loaded value. If an Increment results in all the unmasked bits of the counter being “1s,” a counter interrupt flag (CNTINT) is asserted. The next Increment will return the counter register to its initial value, which was stored in the mirror register. The counter address can instead be forced to loop to 00000 by externally connecting CNTINT to CNTRST.[11] An increment that results in one or more of the unmasked bits of the counter being “0” will de-assert the counter interrupt flag. The example in Figure 2 shows the counter mask register loaded with a mask value of 0003Fh unmasking the first 6 bits with bit “0” as the LSB and bit “16” as the MSB. The maximum value the mask register can be loaded with is 1FFFFh. Setting the mask register to this value allows the counter to access the entire memory space. The address counter is then loaded with an initial value of 8h. The base address bits (in this case, the 6th address through the 16th address) are loaded with an address value but do not increment once the counter is configured for increment operation. The counter address will start at address 8h. The counter will increment its internal address value till it reaches the mask register value of 3Fh. The counter wraps around the memory block to location 8h at the next count. CNTINT is issued when the counter reaches its maximum value. Counter Hold Operation The value of all three registers can be constantly maintained unchanged for an unlimited number of clock cycles. Such operation is useful in applications where wait states are needed, or when address is available a few cycles ahead of data in a shared bus interface.
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CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V
Counter Interrupt The counter interrupt (CNTINT) is asserted LOW when an increment operation results in the unmasked portion of the counter register being all “1s.” It is deasserted HIGH when an Increment operation results in any other value. It is also de-asserted by Counter Reset, Counter Load, Mask Reset and Mask Load operations, and by MRST. Retransmit Retransmit is a feature that allows the Read of a block of memory more than once without the need to reload the initial address. This eliminates the need for external logic to store and route data. It also reduces the complexity of the system design and saves board space. An internal “mirror register” is used to store the initially loaded address counter value. When the counter unmasked portion reaches its maximum value set by the mask register, it wraps back to the initial value stored in this “mirror register.” If the counter is continuously configured in increment mode, it increments again to its maximum value and wraps back to the value initially stored into the “mirror register.” Thus, the repeated access of the same data is allowed without the need for any external logic. Mask Reset Operation The mask register is reset to all “1s,” which unmasks every bit of the counter. Master reset (MRST) also resets the mask register to all “1s.” Mask Load Operation The mask register is loaded with the address value presented at the address lines. Not all values permit correct increment operations. Permitted values are of the form 2n – 1 or 2n – 2. From the most significant bit to the least significant bit, permitted values have zero or more “0s,” one or more “1s,” or one “0.” Thus 1FFFF, 003FE, and 00001 are permitted values, but 1F0FF, 003FC, and 00000 are not. Mask Readback Operation The internal value of the mask register can be read out on the address lines. Readback is pipelined; the address will be valid tCM2 after the next rising edge of the port’s clock. If mask readback occurs while the port is enabled (CE0 LOW and CE1 HIGH), the data lines (DQs) will be three-stated. Figure 1 shows a block diagram of the operation. Counting by Two When the least significant bit of the mask register is “0,” the counter increments by two. This may be used to connect the CY7C0850V/CY7C0851V/CY7C0852V as a 72-bit single port SRAM in which the counter of one port counts even addresses and the counter of the other port counts odd addresses. This even-odd address scheme stores one half of the 72-bit data in even memory locations, and the other half in odd memory locations.
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CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V
CNT/MSK CNTEN ADS CNTRST MRST Decode Logic
Bidirectional Address Lines
Mask Register Counter/ Address Register
Address Decode
RAM Array
CLK
From Address Lines
17 Mirror
Load/Increment Counter To Readback and Address Decode
1 From Mask Register 17 Increment Logic Wrap 0
1 0
17
From Mask From Counter
17 17
17 Bit 0 +1 1 +2 0 1 0 17 To Counter Wrap Detect Wrap
Figure 1. Counter, Mask, and Mirror Logic Block Diagram[1]
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CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V
Example: Load Counter-Mask Register = 3F CNTINT H 00 216 215 Masked Address Load Address Counter = 8 H XX 216 215 Max Address Register Max + 1 Address Register L XX 216 215 H XX 216 215 Xs Xs Xs 0s 011 1 1 1 1 Mask Register bit-0
26 25 24 23 22 21 20 Unmasked Address X00 1 0 0 0
26 25 24 23 22 21 20 X11 1 11 1
Address Counter bit-0
26 25 24 23 22 21 20 X0 0 1 00 0
26 25 24 23 22 21 20
Figure 2. Programmable Counter-Mask Register Operation[1, 12]
IEEE 1149.1 Serial Boundary Scan (JTAG)[13]
The CY7C0850V/CY7C0851V/CY7C0852V/CY7C0853V incorporates an IEEE 1149.1 serial boundary scan test access port (TAP). The TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1-compliant TAPs. The TAP operates using JEDEC-standard 3.3V I/O logic levels. It is composed of three input connections and one output connection required by the test logic defined by the standard. Performing a TAP Reset A reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This reset does not affect the operation of the devices, and may be performed while the devices are Table 4. Identification Register Definitions Instruction Field Revision Number (31:28) Cypress Device ID (27:12) 0h C001h C002h C092h Cypress JEDEC ID (11:1) ID Register Presence (0) 034h 1 Value
operating. An MRST must be performed on the devices after power-up. Performing a Pause/Restart When a SHIFT-DR PAUSE-DR SHIFT-DR is performed the scan chain will output the next bit in the chain twice. For example, if the value expected from the chain is 1010101, the device will output a 11010101. This extra bit will cause some testers to report an erroneous failure for the devices in a scan test. Therefore the tester should be configured to never enter the PAUSE-DR state.
.
Description Reserved for version number. Defines Cypress part number for the CY7C0851V Defines Cypress part number for the CY7C0852V and CY7C0853V Defines Cypress part number for the CY7C0850V Allows unique identification of the DP family device vendor. Indicates the presence of an ID register.
Notes: 12. The “X” in this diagram represents the counter upper bits. 13. Boundary scan is IEEE 1149.1-compatible. See “Performing a Pause/Restart” for deviation from strict 1149.1 compliance
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Table 5. Scan Registers Sizes Register Name Instruction Bypass Identification Boundary Scan Table 6. Instruction Identification Codes Instruction EXTEST BYPASS IDCODE HIGHZ CLAMP SAMPLE/PRELOAD NBSRST RESERVED 1111 1011 0111 0100 1000 1100 All other codes Code 0000 Description Captures the Input/Output ring contents. Places the BSR between the TDI and TDO. Places the BYR between TDI and TDO. Loads the IDR with the vendor ID code and places the register between TDI and TDO. Places BYR between TDI and TDO. Forces all CY7C0851V/CY7C0852V/ CY7C0853V output drivers to a High-Z state. Controls boundary to 1/0. Places BYR between TDI and TDO. Captures the input/output ring contents. Places BSR between TDI and TDO. Resets the non-boundary scan logic. Places BYR between TDI and TDO. Other combinations are reserved. Do not use other than the above. Bit Size 4 1 32 n[14]
Note: 14. See details in the device BSDL files.
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Maximum Ratings [15]
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................ –65°C to + 150°C Ambient Temperature with Power Applied............................................–55°C to + 125°C Supply Voltage to Ground Potential .............. –0.5V to + 4.6V DC Voltage Applied to Outputs in High-Z State..........................–0.5V to VDD + 0.5V DC Input Voltage .............................. –0.5V to VDD + 0.5V[16] Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... > 2000V (JEDEC JESD22-A114-2000B) Latch-up Current..................................................... > 200 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VDD 3.3V ± 165 mV 3.3V ± 165 mV
Electrical Characteristics Over the Operating Range
Parameter
VOH VOL VIH VIL IOZ IIX1 IIX2 ICC
Description
Output HIGH Voltage (VDD = Min., IOH= –4.0 mA) Output LOW Voltage (VDD = Min., IOL= +4.0 mA) Input HIGH Voltage Input LOW Voltage Output Leakage Current Input Leakage Current Except TDI, TMS, MRST Input Leakage Current TDI, TMS, MRST Operating Current for CY7C0850V (VDD = Max.,IOUT = 0 mA), Outputs Disabled CY7C0851V CY7C0852V CY7C0853V Standby Current (Both Ports TTL Level) CEL and CER ≥ VIH, f = fMAX Standby Current (One Port TTL Level) CEL | CER ≥ VIH, f = fMAX Standby Current (Both Ports CMOS Level) CEL and CER ≥ VDD – 0.2V, f = 0 Standby Current (One Port CMOS Level) CEL | CER ≥ VIH, f = fMAX –10 –10 –0.1 2.0 2.4
-167
2.4 0.4 2.0 0.8 10 10 1.0 225 300 –10 –10 –0.1
-133
2.4 0.4 2.0 0.8 10 10 1.0 225 300 –10 –10 –0.1
-100
V 0.4 V V 0.8 10 10 1.0 V µA µA mA mA
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
270 90 115 90
400 115
200 90
310 115 mA
ISB1[18] ISB2[18] ISB3[18] ISB4[18]
160
210
160
210
160
210
mA
55
75
55
75
55
75
mA
160
210
160
210
160
210
mA
Capacitance [17]
Part Number CY7C0850V/7C0851V/ CY7C0852V CY7C0853V Parameter CIN COUT CIN COUT Description Input Capacitance Output Capacitance Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VDD = 3.3V Max. 13 10 22 20 Unit pF pF pF pF
Note: 15. The voltage on any input or I/O pin can not exceed the power pin during power-up. 16. Pulse width < 20 ns. 17. COUT also references CI/O 18. ISB1, ISB2, ISB3 and ISB4 are not applicable for CY7C0853V because it can not be powered down by using chip enable pins.
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AC Test Load and Waveforms
3.3V Z 0 = 5 0Ω OUTPUT C = 10 pF VTH = 1.5V OUTPUT C = 5 pF R2 = 435 Ω R = 50Ω R1 = 590 Ω
(a) Normal Load (Load 1)
3.0V ALL INPUT PULSES Vss < 2 ns
(b) Three-state Delay (Load 2)
90% 10%
90% 10% < 2 ns
Switching Characteristics Over the Operating Range
-167 Parameter Description CY7C0850V CY7C0851V CY7C0852V Min. fMAX2 tCYC2 tCH2 tCL2 tR[19] tF[19] tSA tHA tSB tHB tSC tHC tSW tHW tSD tHD tSAD tHAD tSCN tHCN tSRST tHRST tSCM tHCM Maximum Operating Frequency Clock Cycle Time Clock HIGH Time Clock LOW Time Clock Rise Time Clock Fall Time Address Set-up Time Address Hold Time Byte Select Set-up Time Byte Select Hold Time Chip Enable Set-up Time Chip Enable Hold Time R/W Set-up Time R/W Hold Time Input Data Set-up Time Input Data Hold Time ADS Set-up Time ADS Hold Time CNTEN Set-up Time CNTEN Hold Time CNTRST Set-up Time CNTRST Hold Time CNT/MSK Set-up Time CNT/MSK Hold Time 2.3 0.6 2.3 0.6 2.3 0.6 2.3 0.6 2.3 0.6 2.3 0.6 2.3 0.6 2.3 0.6 2.3 0.6 6.0 2.7 2.7 2.0 2.0 2.5 0.6 2.5 0.6 2.5 0.6 2.5 0.6 2.5 0.6 2.5 0.6 2.5 0.6 2.5 0.6 2.5 0.6 Max. 167 7.5 3.0 3.0 2.0 2.0 2.5 0.6 2.5 0.6 NA NA 2.5 0.6 2.5 0.6 NA NA NA NA NA NA NA NA -133 CY7C0850V CY7C0851V CY7C0852V Min. Max. 133 7.5 3.0 3.0 2.0 2.0 3.0 0.6 3.0 0.6 NA NA 3.0 0.6 3.0 0.6 NA NA NA NA NA NA NA NA CY7C0853V Min. Max. 133 10.0 4.0 4.0 3.0 3.0 -100 CY7C0853V Min. Max. 100 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Notes: 19. Except JTAG signals (tr and tf < 10 ns [max.]). 20. This parameter is guaranteed by design, but it is not production tested. 21. Test conditions used are Load 2.
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Switching Characteristics Over the Operating Range (continued)
-167 Parameter Description CY7C0850V CY7C0851V CY7C0852V Min. tOE tOLZ[20, 21] tOHZ[20, 21] tCD2 tCA2 tCM2 tDC tCKHZ tSINT tRINT tSCINT tRCINT tCCS tRS tRSS tRSR tRSF tRSCNTINT
[20, 21]
-133 CY7C0850V CY7C0851V CY7C0852V Min. 0 4.0 4.0 4.0 4.0 0 4.4 4.4 4.4 4.4 1.0 4.0 4.0 6.7 6.7 5.0 5.0 0 1.0 0.5 0.5 0.5 0.5 6.0 7.5 6.0 7.5 6.0 5.8 6.5 7.0 4.4 4.4 7.5 7.5 5.7 5.7 1.0 0 1.0 0.5 0.5 NA NA 6.0 7.5 6.0 7.5 6.5 NA 4.7 4.7 7.5 7.5 NA NA Max. 4.4 0 0 4.7 4.7 NA NA 1.0 0 1.0 0.5 0.5 NA NA 8.0 CY7C0853V Min. Max. 4.7 0 0
-100 CY7C0853V Min. Max. 5.0 5.0 5.0 NA NA ns ns ns ns ns ns ns 5.0 5.0 10 10 NA NA ns ns ns ns ns ns ns ns ns ns 8.0 NA ns ns Unit
Max. 4.0
Output Enable to Data Valid OE to Low Z OE to High Z Clock to Data Valid Clock to Counter Address Valid Clock to Mask Register Readback Valid Data Output Hold After Clock HIGH Clock HIGH to Output High Z Clock HIGH to Output Low Z Clock to INT Set Time Clock to INT Reset Time Clock to CNTINT Set Time Clock to CNTINT Reset time Clock to Clock Skew Master Reset Pulse Width Master Reset Set-up Time Master Reset Recovery Time Master Reset to Outputs Inactive Master Reset to Counter Interrupt Flag Reset Time 1.0 0 1.0 0.5 0.5 0.5 0.5 5.2 7.0 6.0 6.0 0 0
tCKLZ[20, 21]
Port to Port Delays Master Reset Timing 10.0 8.5 10.0
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JTAG Timing
167/133/100 Parameter fJTAG tTCYC tTH tTL tTMSS tTMSH tTDIS tTDIH tTDOV tTDOX TCK Clock Cycle Time TCK Clock HIGH Time TCK Clock LOW Time TMS Set-up to TCK Clock Rise TMS Hold After TCK Clock Rise TDI Set-up to TCK Clock Rise TDI Hold After TCK Clock Rise TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid 0 Description Maximum JTAG TAP Controller Frequency 100 40 40 10 10 10 10 30 Min. Max. 10 Unit MHz ns ns ns ns ns ns ns ns ns
JTAG Switching Waveform
tTH Test Clock TCK Test Mode Select TMS tTDIS Test Data-In TDI Test Data-Out TDO tTDIH tTL
tTMSS
tTCYC tTMSH
tTDOX
tTDOV
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Switching Waveforms
Master Reset
MRST ALL ADDRESS/ DATA LINES ALL OTHER INPUTS TMS CNTINT INT TDO tRSF tRSS tRSR ACTIVE tRS
INACTIVE
Read Cycle[ 4, 22, 23, 24, 25]
tCH2 CLK tCYC2 tCL2
CE tSC tSB B0–B3 tHC tHB tSC tHC
R/W tSW tSA ADDRESS DATAOUT An 1 Latency tHW tHA An+1 tCD2 Qn tCKLZ OE
tOE Notes: 22. OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge. 23. ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH. 24. The output is disabled (high-impedance state) by CE = VIH following the next rising edge of the clock. 25. Addresses do not have to be accessed sequentially since ADS = CNTEN = VIL with CNT/MSK = VIH constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
An+2 tDC Qn+1 tOHZ
An+3
Qn+2 tOLZ
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Switching Waveforms (continued)
Bank Select Read[26, 27]
tCH2 CLK tSA ADDRESS(B1) tSC CE(B1) tCD2 DATAOUT(B1) tSA ADDRESS(B2) A0 tHA A1 tSC CE(B2) tSC DATAOUT(B2) tCKLZ tHC tCD2 Q2 tCKLZ tCKHZ tCD2 Q4 tSC Q0 tDC A2 tHC tHC tCD2 Q1 tDC A3 A4 tCKLZ A5 tCKHZ tCD2 Q3 tCKHZ A0 tHC tHA A1 A2 A3 A4 A5 tCYC2 tCL2
Read-to-Write-to-Read (OE = LOW)[25, 28, 29, 30, 31]
tCH2 CLK tCYC2 tCL2
CE tSC tHC
tSW R/W tSW ADDRESS tSA DATAIN An tHA tCD2 Qn tHW An+1 An+2
tHW
An+2 tSD tHD
An+3
An+4
tCKHZ
Dn+2
tCD2 Qn+3 tCKLZ
DATAOUT READ
NO OPERATION
WRITE
READ
Notes: 26. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress CY7C0851V/CY7C0852V device from this data sheet. ADDRESS(B1) = ADDRESS(B2). 27. ADS = CNTEN= B0 – B3 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH. 28. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals. 29. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. 30. CE0 = OE = B0 – B3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH. 31. CE0 = B0 – B3 = R/W = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be completed (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.
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Switching Waveforms (continued)
Read-to-Write-to-Read (OE Controlled)[25, 28, 30, 31]
tCH2 CLK tCYC2 tCL2
CE tSC tHC tSW tHW
R/W
tSW An tSA
tHW An+1 tHA tCD2 An+2 tSD tHD Dn+2 Dn+3 tCD2 Qn tOHZ Qn+4 An+3 An+4 An+5
ADDRESS DATAIN
DATAOUT
OE READ WRITE READ
Read with Address Counter
tCH2 CLK tSA ADDRESS tSAD ADS An
Advance[30]
tCYC2 tCL2
tHA
tHAD tSAD tHAD
CNTEN tSCN DATAOUT Qx–1 READ EXTERNAL ADDRESS tHCN Qx tDC tCD2 Qn READ WITH COUNTER tSCN Qn+1 COUNTER HOLD tHCN Qn+2 READ WITH COUNTER Qn+3
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Switching Waveforms (continued)
Write with Address Counter Advance [31]
tCH2 CLK tSA ADDRESS An tHA tCYC2 tCL2
INTERNAL ADDRESS tSAD ADS tHAD
An
An+1
An+2
An+3
An+4
CNTEN tSCN DATAIN tSD Dn tHD WRITE EXTERNAL ADDRESS tHCN Dn+1 WRITE WITH COUNTER Dn+1 Dn+2 Dn+3 Dn+4
WRITE COUNTER HOLD
WRITE WITH COUNTER
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Switching Waveforms (continued)
Counter Reset [32, 33]
tCYC2 tCH2 tCL2 CLK tSA ADDRESS INTERNAL ADDRESS An Ax tSW R/W tHW 0 1 An tHA Am Am Ap Ap
ADS
CNTEN tSRST tHRST CNTRST tSD DATAIN tHD
D0
tCD2 Q0 tCKLZ READ ADDRESS 0
tCD2 Q1 Qn
[45] DATAOUT
COUNTER RESET
WRITE ADDRESS 0
READ ADDRESS 1
READ ADDRESS An
READ ADDRESS Am
Notes: 32. CE0 = B0 – B3 = LOW; CE1 = MRST = CNT/MSK = HIGH. 33. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset.
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Switching Waveforms (continued)
Readback State of Address Counter or Mask Register[34, 35, 36, 37]
tCYC2 tCH2 tCL2 CLK tSA tHA EXTERNAL ADDRESS A0–A16 INTERNAL ADDRESS tSAD tHAD ADS tSCN tHCN CNTEN tCD2 DATAOUT Qx-2 Qx-1 tCKHZ Qn tCKLZ Qn+1 Qn+2 Qn+3 An tCA2 or tCM2 An*
An
An+1
An+2
An+3
An+4
LOAD EXTERNAL ADDRESS
READBACK COUNTER INTERNAL ADDRESS
INCREMENT
Notes: 34. CE0 = OE = B0 – B3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH. 35. Address in output mode. Host must not be driving address bus after tCKLZ in next clock cycle. 36. Address in input mode. Host can drive address bus after tCKHZ. 37. An * is the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines.
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Switching Waveforms (continued)
Left_Port (L_Port) Write to Right_Port (R_Port) Read[38, 39, 40]
tCH2 CLKL tSA L_PORT ADDRESS tSW R/WL tCKHZ tSD Dn tCYC2 tCL2 tCH2 tSA An tHA tCCS tHD An tHW tHA tCYC2 tCL2
L_PORT
DATAIN
tCKLZ
CLKR R_PORT ADDRESS
R/WR tCD2
R_PORT
DATAOUT tDC
Qn
Notes: 38. CE0 = OE = ADS = CNTEN = B0 – B3 = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. 39. This timing is valid when one port is writing, and other port is reading the same location at the same time. If tCCS is violated, indeterminate data will be Read out. 40. If tCCS < minimum specified value, then R_Port will Read the most recent data (written by L_Port) only (2 * tCYC2 + tCD2) after the rising edge of R_Port's clock. If tCCS > minimum specified value, then R_Port will Read the most recent data (written by L_Port) (tCYC2 + tCD2) after the rising edge of R_Port's clock.
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Switching Waveforms (continued)
Counter Interrupt and Retransmit[41, 42, 43, 44, 45]
tCH2 CLK tSCM CNT/MSK tHCM tCYC2 tCL2
ADS
CNTEN
COUNTER INTERNAL ADDRESS CNTINT
1FFFC
1FFFD
1FFFE tSCINT
1FFFF tRCINT
Last_Loaded
Last_Loaded +1
Notes: 41. CE0 = OE = B0 – B3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH. 42. CNTINT is always driven. 43. CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value. 44. The mask register assumed to have the value of 1FFFFh. 45. Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value.
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Switching Waveforms (continued)
MailBox Interrupt Timing[46, 47, 48, 49, 50]
tCH2 CLKL tSA L_PORT ADDRESS INTR tCYC2 tCL2 tHA An tSINT tRINT An+1 An+2 An+3 tCYC2 tCL2
3FFFF
tCH2 CLKR
tSA R_PORT ADDRESS Am
tHA Am+1 3FFFF Am+3 Am+4
Table 7. Read/Write and Enable Operation (Any Port)[1, 8, 51, 52] Inputs OE X X X L H X CLK CE0 H X L L L CE1 X L H H H R/W X X L H X Outputs DQ0 – DQ35 High-Z High-Z DIN DOUT High-Z Deselected Deselected Write Read Outputs Disabled Operation
Notes: 46. CE0 = OE = ADS = CNTEN = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. 47. Address “3FFFF” is the mailbox location for R_Port of a 9M device. 48. L_Port is configured for Write operation, and R_Port is configured for Read operation. 49. At least one byte enable (B0 – B3) is required to be active during interrupt operations. 50. Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock. 51. OE is an asynchronous input signal. 52. When CE changes state, deselection and Read happen after one cycle of latency.
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Ordering Information
256K × 36 (9M) 3.3V Synchronous CY7C0853V Dual-Port SRAM Speed (MHz) 133 100 Ordering Code CY7C0853V-133BBC CY7C0853V-133BBI CY7C0853V-100BBC CY7C0853V-100BBI Speed (MHz) 167 133 Package Name BB172 BB172 BB172 BB172 Package Name BB172 A176 BB172 BB172 A176 A176 Package Name BB172 A176 BB172 BB172 A176 A176 Package Name BB172 A176 BB172 BB172 A176 A176 Package Type Operating Range
172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Commercial 172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Industrial 172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Commercial 172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Industrial Operating Range Commercial
128K × 36 (4M) 3.3V Synchronous CY7C0852V Dual-Port SRAM Ordering Code CY7C0852V-167BBC CY7C0852V-167AC CY7C0852V-133BBC CY7C0852V-133BBI CY7C0852V-133AC CY7C0852V-133AI Speed (MHz) 167 133 Package Type 176-pin Flat Pack 24 mm × 24 mm (TQFP)
172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Commercial 172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Commercial 172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Industrial 176-pin Flat Pack 24 mm × 24 mm (TQFP) 176-pin Flat Pack 24 mm × 24 mm (TQFP) Commercial Industrial Operating Range Commercial
64K × 36 (2M) 3.3V Synchronous CY7C0851V Dual-Port SRAM Ordering Code CY7C0851V-167BBC CY7C0851V-167AC CY7C0851V-133BBC CY7C0851V-133BBI CY7C0851V-133AC CY7C0851V-133AI Speed (MHz) 167 133 Package Type 176-pin Flat Pack 24 mm × 24 mm (TQFP)
172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Commercial 172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Commercial 172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Industrial 176-pin Flat Pack 24 mm × 24 mm (TQFP) 176-pin Flat Pack 24 mm × 24 mm (TQFP) Commercial Industrial Operating Range Commercial
32K × 36 (1M) 3.3V Synchronous CY7C0850V Dual-Port SRAM Ordering Code CY7C0850V-167BBC CY7C0850V-167AC CY7C0850V-133BBC CY7C0850V-133BBI CY7C0850V-133AC CY7C0850V-133AI Package Type 176-pin Flat Pack 24 mm × 24 mm (TQFP)
172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Commercial 172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Commercial 172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Industrial 176-pin Flat Pack 24 mm × 24 mm (TQFP) 176-pin Flat Pack 24 mm × 24 mm (TQFP) Commercial Industrial
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Package Diagrams 176-lead Thin Quad Flat Pack (24 × 24 × 1.4 mm) A176
51-85132-**
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Package Diagrams (continued) 172-Ball FBGA (15 x 15 x 1.25 mm) BB172
51-85114-*B
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© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V
Document History Page
Document Title: CY7C0850V/CY7C0851V/CY7C0852V/CY7C0853V FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM Document Number: 38-06070 REV. ** ECN NO. 127809 Issue Date 08/04/03 Orig. of Change SPN Description of Change This data sheet has been extracted from another data sheet: the 2M/4M/9M data sheet. The following changes have been made from the original as pertains to this device: Updated capacitance values Updated “Read-to-Write-to-Read (OE Controlled)” waveform Revised static discharge voltage Corrected 0853 pins L3 and L12 Added discussion of Pause/Restart for JTAG boundary scan Power up requirements added to Maximum Ratings information Revise tcd2, tOE, tOHZ, tCKHZ, tCKLZ for the CY7C0853V to 4.7 ns Updated Icc numbers Updated tHA, tHB, tHD for -100 speed Separated out from the 4M data sheet Added 133-MHz Industrial device to Ordering Information table Changed mailbox addresses from 1FFFE and 1FFFF to 3FFFE and 3FFFF. Removed “A particular port can write to a certain location while another port is reading that location.” from Functional Description. Merged 0853 (9Mx36) with 0852 (4Mx36) and 0851(2Mx36), add 0850 (1M x36), to the datasheet. Added product selection table. Added JTAG ID code for 1M device. Added note 14. Updated boundry scan section section. Updated function description for the merge and addition.
*A *B *C *D
210948 216190 231996 238938
See ECN See ECN See ECN See ECN
YDT YDT WWZ
YDT/Dcon Corrected Revision of Document. CMS does not reflect this rev change
Document #: 38-06070 Rev. *D
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