CY7C0851V-133AXC

CY7C093794V CY7C093894V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM Features Functional Description • True dual-ported memory cells that allow simultaneous access of the same memory location • Synchronous pipelined operation • Organization of 1-Mbit, 2-Mbit, 4-Mbit and 9-Mbit devices • Pipelined output mode allows fast operation • 0.18-micron CMOS for optimum speed and power • High-speed clock to data access • 3.3V low power — Active as low as 225 mA (typ) • • • • • • • • The FLEx36 family includes 1M, 2M, 4M and 9M pipelined, synchronous, true dual-port static RAMs that are high-speed, low-power 3.3V CMOS. Two ports are provided, permitting independent, simultaneous access to any location in memory. The result of writing to the same location by more than one port at the same time is undefined. Registers on control, address, and data lines allow for minimal set-up and hold time. — Standby as low as 55 mA (typ) Mailbox function for message passing Global master reset Separate byte enables on both ports Commercial and industrial temperature ranges IEEE 1149.1-compatible JTAG boundary scan 172-ball FBGA (1 mm pitch) (15 mm × 15 mm) 176-pin TQFP (24 mm × 24 mm × 1.4 mm) Counter wrap around control — Internal mask register controls counter wrap-around — Counter-interrupt flags to indicate wrap-around — Memory block retransmit operation • Counter readback on address lines • Mask register readback on address lines • Dual Chip Enables on both ports for easy depth expansion During a Read operation, data is registered for decreased cycle time. Each port contains a burst counter on the input address register. After externally loading the counter with the initial address, the counter will increment the address internally (more details to follow). The internal Write pulse width is independent of the duration of the R/W input signal. The internal Write pulse is self-timed to allow the shortest possible cycle times. A HIGH on CE0 or LOW on CE1 for one clock cycle will power down the internal circuitry to reduce the static power consumption. One cycle with chip enables asserted is required to reactivate the outputs. Additional features include: readback of burst-counter internal address value on address lines, counter-mask registers to control the counter wrap-around, counter interrupt (CNTINT) flags, readback of mask register value on address lines, retransmit functionality, interrupt flags for message passing, JTAG for boundary scan, and asynchronous Master Reset (MRST). The CY7C0853 device in this family has limited features. Please see See “Address Counter and Mask Register Operations[10]” on page 8. for details. Table 1. Product Selection Guide Density 1-Mbit (32K x 36) 2-Mbit (64K x 36) 4-Mbit (128K x 36) 9-Mbit (256K x 36) CY7C0850V CY7C0851V CY7C0852V CY7C0853V Max. Speed (MHz) 167 167 167 133 Max. Access Time - clock to Data (ns) 4.0 4.0 4.0 4.7 Part Number Typical operating current (mA) Package Cypress Semiconductor Corporation Document #: 38-06070 Rev. *D • 225 225 225 270 176TQFP 172FBGA 176TQFP 172FBGA 176TQFP 172FBGA 172FBGA 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised June 24, 2004 CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V Logic Block Diagram[1] OEL R/WL OER R/WR B0L B0R B1L B1R B2L B2R B3L B3R CE0L CE1L DQ27L–DQ35L DQ18L–DQ26L DQ9L–DQ17L DQ0L–DQ8L CE0R CE1R 9 9 9 9 I/O Control 9 I/O Control 9 9 9 Addr. Read Back DQ27R–DQ35R DQ18R–DQ26R DQ9R–DQ17R DQ0R–DQ8R Addr. Read Back True Dual-Ported RAM Array A0L–A17L 18 CNT/MSKL 18 Mask Register Mask Register Counter/ Address Register Counter/ Address Register ADSL CNTENL CNTRSTL CLKL Address Address Decode Decode Mirror Reg INTL Interrupt Logic CNT/MSKR ADS CNTEN CNTRSTR Mirror Reg CNTINTL MRST Reset Logic TMS TDI TCK JTAG TDO Interrupt Logic A0R–A17R CLKR CNTINTR INTR Note: 1. , 9M device has 18 address bits, 4M device has 17 address bits, 2M device has 16 address bits, and 1M device has 15 address bits. Document #: 38-06070 Rev. *D Page 2 of 29 CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V Pin Configurations 172-ball BGA Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A DQ32L DQ30L CNTINTL VSS DQ13L VDD DQ11L DQ11R VDD DQ13R VSS CNTINTR DQ30R DQ32R B A0L DQ33L DQ29L DQ17L DQ14L DQ12L DQ9L DQ9R DQ12R DQ14R DQ17R DQ29R DQ33R A0R C NC A1L DQ31L DQ27L INTL DQ15L DQ10L DQ10R DQ15R INTR DQ27R DQ31R A1R NC D A2L A3L DQ35L DQ34L DQ28L DQ16L VSS VSS DQ16R DQ28R DQ34R DQ35R A3R A2R E A4L A5L CE1L B0L VDD VSS VDD VDD B0R CE1R A5R A4R F VDD A6L A7L B1L VDD VSS B1R A7R A6R VDD G OEL B2L B3L CE0L CE0R B3R B2R OER H VSS R/WL A8L CLKL CLKR A8R R/WR VSS J A9L A10L VSS ADSL VSS VDD ADSR MRST A10R A9R K A11L A12L A15L[2] CNTRSTL VDD VDD VSS VDD CNTRSTR A15R[2] A12R A11R L CNT/MSKL A13L CNTENL DQ26L DQ25L DQ19L VSS VSS DQ19R DQ25R DQ26R CNTENR A13R CNT/MSKR M A16L[2] A14L DQ22L DQ18L TDI DQ7L DQ2L DQ2R DQ7R TCK DQ18R DQ22R A14R A16R[2] N DQ24L DQ20L DQ8L DQ6L DQ5L DQ3L DQ0L DQ0R DQ3R DQ5R DQ6R DQ8R DQ20R DQ24R P DQ23L DQ21L TDO VSS DQ4L VDD DQ1L DQ1R VDD DQ4R VSS TMS DQ21R DQ23R CY7C0850V CY7C0851V CY7C0852V Note: 2. For CY7C0851V, pins M1 and M14 are NC. For CY7C0850V, pins K3, K12 M1, and M14 are NC Document #: 38-06070 Rev. *D Page 3 of 29 CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V Pin Configurations (continued) 172-ball BGA Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A DQ32L DQ30L NC VSS DQ13L VDD DQ11L DQ11R VDD DQ13R VSS NC DQ30R DQ32R B A0L DQ33L DQ29L DQ17L DQ14L DQ12L DQ9L DQ9R DQ12R DQ14R DQ17R DQ29R DQ33R A0R C A17L A1L DQ31L DQ27L INTL DQ15L DQ10L DQ10R DQ15R INTR DQ27R DQ31R A1R A17R D A2L A3L DQ35L DQ34L DQ28L DQ16L VSS VSS DQ16R DQ28R DQ34R DQ35R A3R A2R E A4L A5L VDD B0L VDD VSS VDD VDD B0R VDD A5R A4R F VDD A6L A7L B1L VDD VSS B1R A7R A6R VDD G OEL B2L B3L VSS VSS B3R B2R OER H VSS R/WL A8L CLKL CLKR A8R R/WR VSS J A9L A10L VSS VSS VSS VDD VSS MRST A10R A9R K A11L A12L A15L VDD VDD VDD VSS VDD VDD A15R A12R A11R L VDD A13L VSS DQ26L DQ25L DQ19L VSS VSS DQ19R DQ25R DQ26R VSS A13R VDD M A16L A14L DQ22L DQ18L TDI DQ7L DQ2L DQ2R DQ7R TCK DQ18R DQ22R A14R A16R N DQ24L DQ20L DQ8L DQ6L DQ5L DQ3L DQ0L DQ0R DQ3R DQ5R DQ6R DQ8R DQ20R DQ24R P DQ23L DQ21L TDO VSS DQ4L VDD DQ1L DQ1R VDD DQ4R VSS TMS DQ21R DQ23R Document #: 38-06070 Rev. *D CY7C0853V Page 4 of 29 CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V A6L 10 11 12 A7L B0L 13 14 B1L 15 16 17 18 VDD VSS 20 21 22 23 VSS R/WL 24 25 CLKL 26 27 28 29 30 A10L 33 34 A11L A12L 35 36 VSS 37 VDD A13L 38 DQ32R DQ33R DQ31R DQ30R VSS VDD 136 135 134 137 DQ27R DQ29R DQ28R 139 138 140 DQ16R CNTINTR INTR 142 141 143 DQ14R DQ17R DQ15R 145 144 146 VSS DQ13R 148 147 VDD 150 149 DQ11R DQ12R 151 DQ10R 153 152 DQ9L DQ9R 154 DQ10L 156 155 DQ12L DQ11L 157 VDD 159 158 DQ13L VSS 160 DQ14L 162 161 DQ15L DQ17L 163 DQ16L 165 164 INTL CNTINTL 166 DQ27L 168 167 DQ28L DQ29L 169 DQ30L 171 170 172 VDD VSS DQ31L 133 123 122 A4R A5R 121 120 119 118 117 A6R A7R B0R B1R CE1R B2R B3R OER CE0R 111 110 109 108 107 VDD VSS 106 105 104 103 MRST ADSR VDD VSS R/WR CLKR CNTENR CNTRSTR CNT/MSKR A8R A9R A10R A11R A12R VSS VDD A13R A14R A15R[2] A16R[2] DQ24R 88 DQ20R DQ23R DQ26R DQ22R 85 86 87 84 VSS VDD DQ21R 82 83 81 DQ19R DQ25R DQ18R 79 80 78 TMS TCK DQ8R 76 77 75 DQ6R DQ7R DQ5R 73 74 71 72 VSS DQ4R VDD 70 68 69 DQ2R DQ3R DQ1R 67 65 66 DQ0L DQ0R DQ1L 64 62 63 DQ3L DQ2L VDD 61 59 60 DQ4L VSS DQ5L 58 56 57 A2R 114 113 112 93 92 91 90 89 Document #: 38-06070 Rev. *D A1R A3R VSS VDD 39 40 41 42 43 44 DQ7L DQ6L DQ24L DQ20L A0R 128 127 126 125 124 95 94 DQ8L A15L[2] A16L[2] 129 97 96 55 A14L DQ35R NC 102 101 100 99 98 31 32 53 54 A8L A9L TDI TDO CNTENL CNTRSTL CNT/MSKL DQ18L VSS ADSL CY7C0850V CY7C0851V CY7C0852V 52 VDD 174 173 19 50 51 OEL CE0L DQ25L DQ19L B3L DQ34R 132 131 130 116 115 DQ21L CE1L B2L 49 A4L A5L DQ33L DQ32L 8 9 47 48 A3L VSS VDD 4 5 6 7 VDD VSS A2L 176-pin Thin Quad Flat Pack (TQFP) Top View 3 DQ22L A1L 1 2 45 46 DQ35L NC A0L DQ26L DQ23L DQ34L 176 175 Pin Configurations (continued) Page 5 of 29 CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V Pin Definitions Left Port A0L–A17L [1] Right Port A0R–A17R [1] Description Address Inputs. ADSL[3] ADSR[3] Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW for the part using the externally supplied address on the address pins and for loading this address into the burst address counter. CE0L[3] CE0R[3] Active LOW Chip Enable Input. CE1L[3] CE1R[3] Active HIGH Chip Enable Input. CLKL CLKR Clock Signal. Maximum clock input rate is fMAX. CNTENL[3] CNTENR[3] Counter Enable Input. Asserting this signal LOW increments the burst address counter of its respective port on each rising edge of CLK. The increment is disabled if ADS or CNTRST are asserted LOW. CNTRSTL[3] CNTRSTR[3] Counter Reset Input. Asserting this signal LOW resets to zero the unmasked portion of the burst address counter of its respective port. CNTRST is not disabled by asserting ADS or CNTEN. CNT/MSKL[3] CNT/MSKR[3] Address Counter Mask Register Enable Input. Asserting this signal LOW enables access to the mask register. When tied HIGH, the mask register is not accessible and the address counter operations are enabled based on the status of the counter control signals. DQ0L–DQ35L DQ0R–DQ35R Data Bus Input/Output. OEL OER Output Enable Input. This asynchronous signal must be asserted LOW to enable the DQ data pins during Read operations. INTL INTR Mailbox Interrupt Flag Output. The mailbox permits communications between ports. The upper two memory locations can be used for message passing. INTL is asserted LOW when the right port writes to the mailbox location of the left port, and vice versa. An interrupt to a port is deasserted HIGH when it reads the contents of its mailbox. CNTINTL[3] CNTINTR[3] Counter Interrupt Output. This pin is asserted LOW when the unmasked portion of the counter is incremented to all “1s.” R/WL R/WR Read/Write Enable Input. Assert this pin LOW to write to, or HIGH to Read from the dual port memory array. B0L–B3L B0R–B3R Byte Select Inputs. Asserting these signals enables Read and Write operations to the corresponding bytes of the memory array. MRST Master Reset Input. MRST is an asynchronous input signal and affects both ports. Asserting MRST LOW performs all of the reset functions as described in the text. A MRST operation is required at power-up. TMS JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State machine transitions occur on the rising edge of TCK. TDI JTAG Test Data Input. Data on the TDI input will be shifted serially into selected registers. TCK JTAG Test Clock Input. TDO JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally three-stated except when captured data is shifted out of the JTAG TAP. VSS Ground Inputs. VDD Power Inputs. Note: 3. These pins are not available for CY7C0853V device. Document #: 38-06070 Rev. *D Page 6 of 29 CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V Master Reset The FLEx36 family devices undergo a complete reset by taking its MRST input LOW. The MRST input can switch asynchronously to the clocks. The MRST initializes the internal burst counters to zero, and the counter mask registers to all ones (completely unmasked). The MRST also forces the Mailbox Interrupt (INT) flags and the Counter Interrupt (CNTINT) flags HIGH. The MRST must be performed on the FLEx36 family devices after power-up. Mailbox Interrupts The upper two memory locations may be used for message passing and permit communications between ports. Table 2 shows the interrupt operation for both ports of CY7C0853V. The highest memory location, 3FFFF is the mailbox for the right port and 3FFFE is the mailbox for the left port. Table 2 shows that in order to set the INTR flag, a Write operation by the left port to address 3FFFF will assert INTR LOW. At least one byte has to be active for a Write to generate an interrupt. A valid Read of the 3FFFF location by the right port will reset INTR HIGH. At least one byte has to be active in order for a Read to reset the interrupt. When one port Writes to the other port’s mailbox, the INT of the port that the mailbox belongs to is asserted LOW. The INT is reset when the owner (port) of the mailbox Reads the contents of the mailbox. The interrupt flag is set in a flow-thru mode (i.e., it follows the clock edge of the writing port). Also, the flag is reset in a flow-thru mode (i.e., it follows the clock edge of the reading port). Each port can read the other port’s mailbox without resetting the interrupt. And each port can write to its own mailbox without setting the interrupt. If an application does not require message passing, INT pins should be left open. Table 2. Interrupt Operation Example [1, 4, 5, 6, 7] Left Port Function R/WL CEL A0L–17L Right Port INTL R/WR CER A0R–17R INTR Set Right INTR Flag L L 3FFFF X X X X L Reset Right INTR Flag X X X X H L 3FFFF H Set Left INTL Flag X X X L L L 3FFFE X Reset Left INTL Flag H L 3FFFE H X X X X Table 3. Address Counter and Counter-Mask Register Control Operation (Any Port) [8, 9] CLK MRST CNT/MSK CNTRST ADS CNTEN Operation Description X L X X X X Master Reset Reset address counter to all 0s and mask register to all 1s. H H L X X Counter Reset Reset counter unmasked portion to all 0s. H H H L L Counter Load Load counter with external address value presented on address lines. H H H L H Counter Readback Read out counter internal value on address lines. H H H H L Counter Increment Internally increment address counter value. H H H H H Counter Hold Constantly hold the address value for multiple clock cycles. H L L X X Mask Reset Reset mask register to all 1s. H L H L L Mask Load Load mask register with value presented on the address lines. H L H L H Mask Readback Read out mask register value on address lines. H L H H X Reserved Operation undefined Notes: 4. CE is internal signal. CE = LOW if CE0 = LOW and CE1 = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK and can be deasserted after that. Data will be out after the following CLK edge and will be three-stated after the next CLK edge. 5. OE is “Don’t Care” for mailbox operation. 6. At least one of B0, B1, B2, or B3 must be LOW. 7. A16x is a NC for CY7C0851V, therefore the Interrupt Addresses are FFFF and EFFF; A16x and A15x are NC for CY7C0850V, therefore the Interrupt Addresses are 7FFF and 6FFF. 8. “X” = “Don’t Care,” “H” = HIGH, “L” = LOW. 9. Counter operation and mask register operation is independent of chip enables. Document #: 38-06070 Rev. *D Page 7 of 29 CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V Address Counter and Mask Register Operations[10] This section describes the features only apply to CY7C0850V/CY7C0851V/CY7C0852V devices, but not to CY7C0853 device. Each port of these devices has a programmable burst address counter. The burst counter contains three registers: a counter register, a mask register, and a mirror register. The counter register contains the address used to access the RAM array. It is changed only by the Counter Load, Increment, Counter Reset, and by master reset (MRST) operations. The mask register value affects the Increment and Counter Reset operations by preventing the corresponding bits of the counter register from changing. It also affects the counter interrupt output (CNTINT). The mask register is changed only by the Mask Load and Mask Reset operations, and by the MRST. The mask register defines the counting range of the counter register. It divides the counter register into two regions: zero or more “0s” in the most significant bits define the masked region, one or more “1s” in the least significant bits define the unmasked region. Bit 0 may also be “0,” masking the least significant counter bit and causing the counter to increment by two instead of one. The mirror register is used to reload the counter register on increment operations (see “retransmit,” below). It always contains the value last loaded into the counter register, and is changed only by the Counter Load, and Counter Reset operations, and by the MRST. Table 3 summarizes the operation of these registers and the required input control signals. The MRST control signal is asynchronous. All the other control signals in Table 3 (CNT/MSK, CNTRST, ADS, CNTEN) are synchronized to the port’s CLK. All these counter and mask operations are independent of the port’s chip enable inputs (CE0 and CE1). Counter enable (CNTEN) inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast, interleaved memory applications. A port’s burst counter is loaded when the port’s address strobe (ADS) and CNTEN signals are LOW. When the port’s CNTEN is asserted and the ADS is deasserted, the address counter will increment on each LOW to HIGH transition of that port’s clock signal. This will Read/Write one word from/into each successive address location until CNTEN is deasserted. The counter can address the entire memory array, and will loop back to the start. Counter reset (CNTRST) is used to reset the unmasked portion of the burst counter to 0s. A counter-mask register is used to control the counter wrap. Counter Reset Operation Counter Load Operation The address counter and mirror registers are both loaded with the address value presented at the address lines. Counter Readback Operation The internal value of the counter register can be read out on the address lines. Readback is pipelined; the address will be valid tCA2 after the next rising edge of the port’s clock. If address readback occurs while the port is enabled (CE0 LOW and CE1 HIGH), the data lines (DQs) will be three-stated. Figure 1 shows a block diagram of the operation. Counter Increment Operation Once the address counter register is initially loaded with an external address, the counter can internally increment the address value, potentially addressing the entire memory array. Only the unmasked bits of the counter register are incremented. The corresponding bit in the mask register must be a “1” for a counter bit to change. The counter register is incremented by 1 if the least significant bit is unmasked, and by 2 if it is masked. If all unmasked bits are “1,” the next increment will wrap the counter back to the initially loaded value. If an Increment results in all the unmasked bits of the counter being “1s,” a counter interrupt flag (CNTINT) is asserted. The next Increment will return the counter register to its initial value, which was stored in the mirror register. The counter address can instead be forced to loop to 00000 by externally connecting CNTINT to CNTRST.[11] An increment that results in one or more of the unmasked bits of the counter being “0” will de-assert the counter interrupt flag. The example in Figure 2 shows the counter mask register loaded with a mask value of 0003Fh unmasking the first 6 bits with bit “0” as the LSB and bit “16” as the MSB. The maximum value the mask register can be loaded with is 1FFFFh. Setting the mask register to this value allows the counter to access the entire memory space. The address counter is then loaded with an initial value of 8h. The base address bits (in this case, the 6th address through the 16th address) are loaded with an address value but do not increment once the counter is configured for increment operation. The counter address will start at address 8h. The counter will increment its internal address value till it reaches the mask register value of 3Fh. The counter wraps around the memory block to location 8h at the next count. CNTINT is issued when the counter reaches its maximum value. Counter Hold Operation The value of all three registers can be constantly maintained unchanged for an unlimited number of clock cycles. Such operation is useful in applications where wait states are needed, or when address is available a few cycles ahead of data in a shared bus interface. All unmasked bits of the counter and mirror registers are reset to “0.” All masked bits remain unchanged. A Mask Reset followed by a Counter Reset will reset the counter and mirror registers to 00000, as will master reset (MRST). Notes: 10. This section describes the CY7C0852V, which have 17 address bits and a maximum address value of 1FFFF. The CY7C0851V has 16 address bits, register lengths of 16 bits, and a maximum address value of FFFF. The CY7C0850V has 15 address bits, register lengths of 15 bits, and a maximum address value of 7FFF 11. CNTINT and CNTRST specs are guaranteed by design to operate properly at speed grade operating frequency when tied together. Document #: 38-06070 Rev. *D Page 8 of 29 CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V Counter Interrupt Mask Load Operation The counter interrupt (CNTINT) is asserted LOW when an increment operation results in the unmasked portion of the counter register being all “1s.” It is deasserted HIGH when an Increment operation results in any other value. It is also de-asserted by Counter Reset, Counter Load, Mask Reset and Mask Load operations, and by MRST. The mask register is loaded with the address value presented at the address lines. Not all values permit correct increment operations. Permitted values are of the form 2n – 1 or 2n – 2. From the most significant bit to the least significant bit, permitted values have zero or more “0s,” one or more “1s,” or one “0.” Thus 1FFFF, 003FE, and 00001 are permitted values, but 1F0FF, 003FC, and 00000 are not. Retransmit Retransmit is a feature that allows the Read of a block of memory more than once without the need to reload the initial address. This eliminates the need for external logic to store and route data. It also reduces the complexity of the system design and saves board space. An internal “mirror register” is used to store the initially loaded address counter value. When the counter unmasked portion reaches its maximum value set by the mask register, it wraps back to the initial value stored in this “mirror register.” If the counter is continuously configured in increment mode, it increments again to its maximum value and wraps back to the value initially stored into the “mirror register.” Thus, the repeated access of the same data is allowed without the need for any external logic. Mask Reset Operation The mask register is reset to all “1s,” which unmasks every bit of the counter. Master reset (MRST) also resets the mask register to all “1s.” Document #: 38-06070 Rev. *D Mask Readback Operation The internal value of the mask register can be read out on the address lines. Readback is pipelined; the address will be valid tCM2 after the next rising edge of the port’s clock. If mask readback occurs while the port is enabled (CE0 LOW and CE1 HIGH), the data lines (DQs) will be three-stated. Figure 1 shows a block diagram of the operation. Counting by Two When the least significant bit of the mask register is “0,” the counter increments by two. This may be used to connect the CY7C0850V/CY7C0851V/CY7C0852V as a 72-bit single port SRAM in which the counter of one port counts even addresses and the counter of the other port counts odd addresses. This even-odd address scheme stores one half of the 72-bit data in even memory locations, and the other half in odd memory locations. Page 9 of 29 CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V CNT/MSK CNTEN Decode Logic ADS CNTRST MRST Bidirectional Address Lines Mask Register Counter/ Address Register Address RAM Decode Array CLK From Address Lines Load/Increment 17 Mirror 1 From Mask Register Increment Logic Wrap 17 From Mask From Counter 17 To Readback and Address Decode 0 0 17 Counter 1 17 17 Bit 0 +1 Wrap Detect 1 +2 Wrap 0 1 0 17 To Counter Figure 1. Counter, Mask, and Mirror Logic Block Diagram[1] Document #: 38-06070 Rev. *D Page 10 of 29 CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V CNTINT Example: Load Counter-Mask Register = 3F H 0 0 0s 216 215 0 1 1 H X X Xs 216 215 Max Address Register L H 1 1 X X X X Unmasked Address X 0 0 1 0 0 Xs X 1 1 1 Mask Register bit-0 0 26 25 24 23 22 21 20 216 215 Max + 1 Address Register 1 26 25 24 23 22 21 20 Masked Address Load Address Counter = 8 1 1 1 1 Address Counter bit-0 26 25 24 23 22 21 20 Xs 216 215 X 0 0 1 0 0 0 26 25 24 23 22 21 20 Figure 2. Programmable Counter-Mask Register Operation[1, 12] IEEE 1149.1 Serial Boundary Scan (JTAG)[13] The CY7C0850V/CY7C0851V/CY7C0852V/CY7C0853V incorporates an IEEE 1149.1 serial boundary scan test access port (TAP). The TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1-compliant TAPs. The TAP operates using JEDEC-standard 3.3V I/O logic levels. It is composed of three input connections and one output connection required by the test logic defined by the standard. Performing a TAP Reset A reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This reset does not affect the operation of the devices, and may be performed while the devices are operating. An MRST must be performed on the devices after power-up. Performing a Pause/Restart When a SHIFT-DR PAUSE-DR SHIFT-DR is performed the scan chain will output the next bit in the chain twice. For example, if the value expected from the chain is 1010101, the device will output a 11010101. This extra bit will cause some testers to report an erroneous failure for the devices in a scan test. Therefore the tester should be configured to never enter the PAUSE-DR state. . Table 4. Identification Register Definitions Instruction Field Value Description Revision Number (31:28) 0h Reserved for version number. Cypress Device ID (27:12) C001h Defines Cypress part number for the CY7C0851V C002h Defines Cypress part number for the CY7C0852V and CY7C0853V C092h Defines Cypress part number for the CY7C0850V Cypress JEDEC ID (11:1) 034h Allows unique identification of the DP family device vendor. ID Register Presence (0) 1 Indicates the presence of an ID register. Notes: 12. The “X” in this diagram represents the counter upper bits. 13. Boundary scan is IEEE 1149.1-compatible. See “Performing a Pause/Restart” for deviation from strict 1149.1 compliance Document #: 38-06070 Rev. *D Page 11 of 29 CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V Table 5. Scan Registers Sizes Register Name Bit Size Instruction 4 Bypass 1 Identification 32 Boundary Scan n[14] Table 6. Instruction Identification Codes Instruction Code Description EXTEST 0000 Captures the Input/Output ring contents. Places the BSR between the TDI and TDO. BYPASS 1111 Places the BYR between TDI and TDO. IDCODE 1011 Loads the IDR with the vendor ID code and places the register between TDI and TDO. HIGHZ 0111 Places BYR between TDI and TDO. Forces all CY7C0851V/CY7C0852V/ CY7C0853V output drivers to a High-Z state. CLAMP 0100 Controls boundary to 1/0. Places BYR between TDI and TDO. SAMPLE/PRELOAD 1000 Captures the input/output ring contents. Places BSR between TDI and TDO. NBSRST 1100 Resets the non-boundary scan logic. Places BYR between TDI and TDO. RESERVED All other codes Other combinations are reserved. Do not use other than the above. Note: 14. See details in the device BSDL files. Document #: 38-06070 Rev. *D Page 12 of 29 CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V DC Input Voltage .............................. –0.5V to VDD + 0.5V[16] Maximum Ratings [15] Output Current into Outputs (LOW)............................. 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage........................................... > 2000V Storage Temperature ................................ –65°C to + 150°C (JEDEC JESD22-A114-2000B) Ambient Temperature with Power Applied............................................–55°C to + 125°C Latch-up Current..................................................... > 200 mA Operating Range Supply Voltage to Ground Potential .............. –0.5V to + 4.6V Range DC Voltage Applied to Outputs in High-Z State..........................–0.5V to VDD + 0.5V Ambient Temperature 0°C to +70°C 3.3V ± 165 mV –40°C to +85°C 3.3V ± 165 mV Commercial Industrial VDD Electrical Characteristics Over the Operating Range Parameter Description -167 -133 -100 Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit VOH Output HIGH Voltage (VDD = Min., IOH= –4.0 mA) VOL Output LOW Voltage (VDD = Min., IOL= +4.0 mA) VIH Input HIGH Voltage VIL Input LOW Voltage 2.4 2.4 2.4 0.4 2.0 V 0.4 2.0 0.4 V 0.8 V µA 2.0 0.8 V 0.8 IOZ Output Leakage Current –10 10 –10 10 –10 10 IIX1 Input Leakage Current Except TDI, TMS, MRST –10 10 –10 10 –10 10 µA IIX2 Input Leakage Current TDI, TMS, MRST –0.1 1.0 –0.1 1.0 –0.1 1.0 mA ICC Operating Current for CY7C0850V (VDD = Max.,IOUT = 0 mA), Outputs Disabled CY7C0851V CY7C0852V ISB1[18] 225 300 225 300 Standby Current (Both Ports TTL Level) CEL and CER ≥ VIH, f = fMAX 90 115 270 400 200 310 90 115 90 115 mA ISB2[18] Standby Current (One Port TTL Level) CEL | CER ≥ VIH, f = fMAX 160 210 160 210 160 210 mA ISB3[18] Standby Current (Both Ports CMOS Level) CEL and CER ≥ VDD – 0.2V, f = 0 55 75 55 75 55 75 mA ISB4[18] Standby Current (One Port CMOS Level) CEL | CER ≥ VIH, f = fMAX 160 210 160 210 160 210 mA CY7C0853V mA Capacitance [17] Part Number CY7C0850V/7C0851V/ CY7C0852V CY7C0853V Parameter Description Test Conditions TA = 25°C, f = 1 MHz, VDD = 3.3V Max. Unit 13 pF 10 pF CIN Input Capacitance COUT Output Capacitance CIN Input Capacitance 22 pF COUT Output Capacitance 20 pF Note: 15. The voltage on any input or I/O pin can not exceed the power pin during power-up. 16. Pulse width < 20 ns. 17. COUT also references CI/O 18. ISB1, ISB2, ISB3 and ISB4 are not applicable for CY7C0853V because it can not be powered down by using chip enable pins. Document #: 38-06070 Rev. *D Page 13 of 29 CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V AC Test Load and Waveforms 3.3V Z0 = 50Ω R = 50Ω R1 = 590 Ω OUTPUT OUTPUT C = 10 pF C = 5 pF VTH = 1.5V (a) Normal Load (Load 1) 3.0V ALL INPUT PULSES (b) Three-state Delay (Load 2) 90% 90% 10% 10% Vss R2 = 435 Ω < 2 ns < 2 ns Switching Characteristics Over the Operating Range -167 Parameter Description -133 -100 CY7C0850V CY7C0851V CY7C0852V CY7C0850V CY7C0851V CY7C0852V CY7C0853V CY7C0853V Min. Min. Min. Min. Max. Max. Max. Unit Max. fMAX2 Maximum Operating Frequency tCYC2 Clock Cycle Time tCH2 tCL2 tR[19] tF[19] Clock Rise Time 2.0 2.0 2.0 3.0 ns Clock Fall Time 2.0 2.0 2.0 3.0 ns tSA Address Set-up Time 2.3 2.5 2.5 3.0 ns tHA Address Hold Time 0.6 0.6 0.6 0.6 ns tSB Byte Select Set-up Time 2.3 2.5 2.5 3.0 ns tHB Byte Select Hold Time 0.6 0.6 0.6 0.6 ns tSC Chip Enable Set-up Time 2.3 2.5 NA NA ns tHC Chip Enable Hold Time 0.6 0.6 NA NA ns 167 133 133 100 MHz 6.0 7.5 7.5 10.0 ns Clock HIGH Time 2.7 3.0 3.0 4.0 ns Clock LOW Time 2.7 3.0 3.0 4.0 ns tSW R/W Set-up Time 2.3 2.5 2.5 3.0 ns tHW R/W Hold Time 0.6 0.6 0.6 0.6 ns tSD Input Data Set-up Time 2.3 2.5 2.5 3.0 ns tHD Input Data Hold Time 0.6 0.6 0.6 0.6 ns tSAD ADS Set-up Time 2.3 2.5 NA NA ns tHAD ADS Hold Time 0.6 0.6 NA NA ns tSCN CNTEN Set-up Time 2.3 2.5 NA NA ns tHCN CNTEN Hold Time 0.6 0.6 NA NA ns tSRST CNTRST Set-up Time 2.3 2.5 NA NA ns tHRST CNTRST Hold Time 0.6 0.6 NA NA ns tSCM CNT/MSK Set-up Time 2.3 2.5 NA NA ns tHCM CNT/MSK Hold Time 0.6 0.6 NA NA ns Notes: 19. Except JTAG signals (tr and tf < 10 ns [max.]). 20. This parameter is guaranteed by design, but it is not production tested. 21. Test conditions used are Load 2. Document #: 38-06070 Rev. *D Page 14 of 29 CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V Switching Characteristics Over the Operating Range (continued) -167 Parameter Description -133 -100 CY7C0850V CY7C0851V CY7C0852V CY7C0850V CY7C0851V CY7C0852V CY7C0853V CY7C0853V Min. Min. Min. Min. Max. Output Enable to Data Valid OE to Low Z 0 tOHZ[20, 21] OE to High Z 0 tCD2 Clock to Data Valid tCA2 Clock to Counter Address Valid 4.0 4.4 NA NA ns tCM2 Clock to Mask Register Readback Valid 4.0 4.4 NA NA ns 0 4.0 0 4.0 1.0 4.7 Max. tOLZ[20, 21] Data Output Hold After Clock HIGH 4.4 Max. tOE tDC 4.0 Max. Unit 0 4.4 0 4.4 1.0 5.0 0 4.7 0 4.7 1.0 ns ns 5.0 ns 5.0 ns 1.0 ns [20, 21] Clock HIGH to Output High Z 0 4.0 0 4.4 0 4.7 0 5.0 ns tCKLZ[20, 21] Clock HIGH to Output Low Z 1.0 4.0 1.0 4.4 1.0 4.7 1.0 5.0 ns tSINT Clock to INT Set Time 0.5 6.7 0.5 7.5 0.5 7.5 0.5 10 ns tRINT Clock to INT Reset Time 0.5 6.7 0.5 7.5 0.5 7.5 0.5 10 ns tSCINT Clock to CNTINT Set Time 0.5 5.0 0.5 5.7 NA NA NA NA ns tRCINT Clock to CNTINT Reset time 0.5 5.0 0.5 5.7 NA NA NA NA ns tCKHZ Port to Port Delays tCCS Clock to Clock Skew 5.2 6.0 6.0 8.0 ns 7.0 7.5 7.5 10.0 ns Master Reset Timing tRS Master Reset Pulse Width tRSS Master Reset Set-up Time 6.0 6.0 6.0 8.5 ns tRSR Master Reset Recovery Time 6.0 7.5 7.5 10.0 ns tRSF Master Reset to Outputs Inactive 6.0 6.5 6.5 8.0 ns tRSCNTINT Master Reset to Counter Interrupt Flag Reset Time 5.8 7.0 NA NA ns Document #: 38-06070 Rev. *D Page 15 of 29 CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V JTAG Timing 167/133/100 Parameter Description Min. Max. Unit 10 MHz fJTAG Maximum JTAG TAP Controller Frequency tTCYC TCK Clock Cycle Time tTH TCK Clock HIGH Time 40 ns tTL TCK Clock LOW Time 40 ns tTMSS TMS Set-up to TCK Clock Rise 10 ns tTMSH TMS Hold After TCK Clock Rise 10 ns tTDIS TDI Set-up to TCK Clock Rise 10 ns tTDIH TDI Hold After TCK Clock Rise 10 ns tTDOV TCK Clock LOW to TDO Valid tTDOX TCK Clock LOW to TDO Invalid 100 ns 30 0 ns ns JTAG Switching Waveform tTH Test Clock TCK tTMSS tTL tTCYC tTMSH Test Mode Select TMS tTDIS tTDIH Test Data-In TDI Test Data-Out TDO Document #: 38-06070 Rev. *D tTDOX tTDOV Page 16 of 29 CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V Switching Waveforms Master Reset tRS MRST tRSF ALL ADDRESS/ DATA LINES tRSS ALL OTHER INPUTS tRSR INACTIVE ACTIVE TMS CNTINT INT TDO Read Cycle[ 4, 22, 23, 24, 25] tCH2 tCYC2 tCL2 CLK CE tSC tHC tSB tHB tSW tSA tHW tHA tSC tHC B0–B3 R/W ADDRESS An DATAOUT An+1 1 Latency An+2 tDC tCD2 Qn tCKLZ An+3 Qn+1 tOHZ Qn+2 tOLZ OE tOE Notes: 22. OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge. 23. ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH. 24. The output is disabled (high-impedance state) by CE = VIH following the next rising edge of the clock. 25. Addresses do not have to be accessed sequentially since ADS = CNTEN = VIL with CNT/MSK = VIH constantly loads the address on the rising edge of the CLK. Numbers are for reference only. Document #: 38-06070 Rev. *D Page 17 of 29 CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V Switching Waveforms (continued) Bank Select Read[26, 27] tCH2 tCYC2 tCL2 CLK tHA tSA ADDRESS(B1) A0 A1 A3 A2 A4 A5 tHC tSC CE(B1) tCD2 tHC tSC tCD2 tHA tSA A0 ADDRESS(B2) tDC A1 tCKHZ Q3 Q1 Q0 DATAOUT(B1) tCD2 tCKHZ tDC tCKLZ A3 A2 A4 A5 tHC tSC CE(B2) tSC tCD2 tHC DATAOUT(B2) tCKHZ tCD2 Q4 Q2 tCKLZ tCKLZ Read-to-Write-to-Read (OE = LOW)[25, 28, 29, 30, 31] tCH2 tCYC2 tCL2 CLK CE tSC tHC tSW tHW R/W tSW tHW An ADDRESS tSA An+1 An+2 An+3 An+4 tSD tHD tHA DATAIN An+2 tCD2 tCKHZ Dn+2 tCD2 Qn DATAOUT Qn+3 tCKLZ READ NO OPERATION WRITE READ Notes: 26. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress CY7C0851V/CY7C0852V device from this data sheet. ADDRESS(B1) = ADDRESS(B2). 27. ADS = CNTEN= B0 – B3 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH. 28. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals. 29. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. 30. CE0 = OE = B0 – B3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH. 31. CE0 = B0 – B3 = R/W = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be completed (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK. Document #: 38-06070 Rev. *D Page 18 of 29 CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V Switching Waveforms (continued) Read-to-Write-to-Read (OE Controlled)[25, 28, 30, 31] tCH2 tCYC2 tCL2 CLK CE tSC tHC tSW tHW R/W ADDRESS tSW tHW An tSA An+1 An+2 tHA An+3 An+4 An+5 tSD tHD Dn+2 DATAIN Dn+3 tCD2 DATAOUT tCD2 Qn Qn+4 tOHZ OE READ Read with Address Counter tCH2 WRITE READ Advance[30] tCYC2 tCL2 CLK tSA ADDRESS tHA An tSAD tHAD ADS tSAD tHAD tSCN tHCN CNTEN tSCN DATAOUT tHCN Qx–1 READ EXTERNAL ADDRESS Document #: 38-06070 Rev. *D tCD2 Qx tDC Qn READ WITH COUNTER Qn+1 COUNTER HOLD Qn+2 Qn+3 READ WITH COUNTER Page 19 of 29 CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V Switching Waveforms (continued) Write with Address Counter Advance [31] tCH2 tCYC2 tCL2 CLK tSA tHA An ADDRESS INTERNAL ADDRESS An tSAD tHAD tSCN tHCN An+1 An+2 An+3 An+4 ADS CNTEN Dn DATAIN tSD tHD WRITE EXTERNAL ADDRESS Document #: 38-06070 Rev. *D Dn+1 Dn+1 WRITE WITH COUNTER Dn+2 WRITE COUNTER HOLD Dn+3 Dn+4 WRITE WITH COUNTER Page 20 of 29 CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V Switching Waveforms (continued) Counter Reset [32, 33] tCYC2 tCH2 tCL2 CLK tSA INTERNAL ADDRESS Ax tSW tHW tSD tHD An 1 0 Ap Am An ADDRESS tHA Ap Am R/W ADS CNTEN tSRST tHRST CNTRST DATAIN D0 tCD2 tCD2 [45] DATAOUT Q0 COUNTER RESET WRITE ADDRESS 0 tCKLZ READ ADDRESS 0 READ ADDRESS 1 Qn Q1 READ ADDRESS An READ ADDRESS Am Notes: 32. CE0 = B0 – B3 = LOW; CE1 = MRST = CNT/MSK = HIGH. 33. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset. Document #: 38-06070 Rev. *D Page 21 of 29 CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V Switching Waveforms (continued) Readback State of Address Counter or Mask Register[34, 35, 36, 37] tCYC2 tCH2 tCL2 CLK tCA2 or tCM2 tSA tHA EXTERNAL ADDRESS A0–A16 An* An INTERNAL ADDRESS An+1 An An+2 An+3 An+4 tSAD tHAD ADS tSCN tHCN CNTEN tCD2 DATAOUT Qx-1 Qn READBACK COUNTER INTERNAL ADDRESS INCREMENT Qx-2 LOAD EXTERNAL ADDRESS tCKHZ tCKLZ Qn+1 Qn+2 Qn+3 Notes: 34. CE0 = OE = B0 – B3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH. 35. Address in output mode. Host must not be driving address bus after tCKLZ in next clock cycle. 36. Address in input mode. Host can drive address bus after tCKHZ. 37. An * is the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines. Document #: 38-06070 Rev. *D Page 22 of 29 CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V Switching Waveforms (continued) Left_Port (L_Port) Write to Right_Port (R_Port) Read[38, 39, 40] tCH2 tCYC2 tCL2 CLKL tHA tSA L_PORT ADDRESS An tSW tHW R/WL tCKHZ tSD L_PORT tCKLZ Dn DATAIN CLKR tHD tCYC2 tCL2 tCCS tCH2 R_PORT ADDRESS tSA tHA An R/WR tCD2 R_PORT Qn DATAOUT tDC Notes: 38. CE0 = OE = ADS = CNTEN = B0 – B3 = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. 39. This timing is valid when one port is writing, and other port is reading the same location at the same time. If tCCS is violated, indeterminate data will be Read out. 40. If tCCS < minimum specified value, then R_Port will Read the most recent data (written by L_Port) only (2 * tCYC2 + tCD2) after the rising edge of R_Port's clock. If tCCS > minimum specified value, then R_Port will Read the most recent data (written by L_Port) (tCYC2 + tCD2) after the rising edge of R_Port's clock. Document #: 38-06070 Rev. *D Page 23 of 29 CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V Switching Waveforms (continued) Counter Interrupt and Retransmit[41, 42, 43, 44, 45] tCH2 tCYC2 tCL2 CLK tSCM tHCM CNT/MSK ADS CNTEN COUNTER INTERNAL ADDRESS 1FFFC 1FFFD 1FFFE tSCINT 1FFFF Last_Loaded Last_Loaded +1 tRCINT CNTINT Notes: 41. CE0 = OE = B0 – B3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH. 42. CNTINT is always driven. 43. CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value. 44. The mask register assumed to have the value of 1FFFFh. 45. Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value. Document #: 38-06070 Rev. *D Page 24 of 29 CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V Switching Waveforms (continued) MailBox Interrupt Timing[46, 47, 48, 49, 50] tCH2 tCYC2 tCL2 CLKL tSA L_PORT ADDRESS tHA 3FFFF An+1 An An+2 An+3 tSINT tRINT INTR tCH2 tCYC2 tCL2 CLKR tSA R_PORT ADDRESS tHA Am+1 Am 3FFFF Am+3 Am+4 Table 7. Read/Write and Enable Operation (Any Port)[1, 8, 51, 52] Inputs OE Outputs CE0 CE1 R/W DQ0 – DQ35 X H X X High-Z Deselected X X L X High-Z Deselected X L H L DIN Write L L H H DOUT Read L H X High-Z Outputs Disabled H CLK X Operation Notes: 46. CE0 = OE = ADS = CNTEN = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. 47. Address “3FFFF” is the mailbox location for R_Port of a 9M device. 48. L_Port is configured for Write operation, and R_Port is configured for Read operation. 49. At least one byte enable (B0 – B3) is required to be active during interrupt operations. 50. Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock. 51. OE is an asynchronous input signal. 52. When CE changes state, deselection and Read happen after one cycle of latency. Document #: 38-06070 Rev. *D Page 25 of 29 CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V Ordering Information 256K × 36 (9M) 3.3V Synchronous CY7C0853V Dual-Port SRAM Speed (MHz) Ordering Code Package Name 133 CY7C0853V-133BBC BB172 172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Commercial CY7C0853V-133BBI BB172 172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Industrial 100 CY7C0853V-100BBC BB172 172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Commercial CY7C0853V-100BBI BB172 172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Industrial Package Type Operating Range 128K × 36 (4M) 3.3V Synchronous CY7C0852V Dual-Port SRAM Speed (MHz) Ordering Code Package Name 167 CY7C0852V-167BBC BB172 CY7C0852V-167AC 133 A176 Package Type Operating Range 172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Commercial 176-pin Flat Pack 24 mm × 24 mm (TQFP) Commercial CY7C0852V-133BBC BB172 172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Commercial CY7C0852V-133BBI BB172 172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Industrial CY7C0852V-133AC A176 176-pin Flat Pack 24 mm × 24 mm (TQFP) Commercial CY7C0852V-133AI A176 176-pin Flat Pack 24 mm × 24 mm (TQFP) Industrial 64K × 36 (2M) 3.3V Synchronous CY7C0851V Dual-Port SRAM Speed (MHz) Ordering Code Package Name 167 CY7C0851V-167BBC BB172 CY7C0851V-167AC 133 A176 Package Type Operating Range 172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Commercial 176-pin Flat Pack 24 mm × 24 mm (TQFP) Commercial CY7C0851V-133BBC BB172 172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Commercial CY7C0851V-133BBI BB172 172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Industrial CY7C0851V-133AC A176 176-pin Flat Pack 24 mm × 24 mm (TQFP) Commercial CY7C0851V-133AI A176 176-pin Flat Pack 24 mm × 24 mm (TQFP) Industrial 32K × 36 (1M) 3.3V Synchronous CY7C0850V Dual-Port SRAM Speed (MHz) Ordering Code Package Name 167 CY7C0850V-167BBC BB172 133 CY7C0850V-133BBC BB172 172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Commercial CY7C0850V-133BBI BB172 172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Industrial CY7C0850V-133AC A176 176-pin Flat Pack 24 mm × 24 mm (TQFP) Commercial CY7C0850V-133AI A176 176-pin Flat Pack 24 mm × 24 mm (TQFP) Industrial CY7C0850V-167AC Document #: 38-06070 Rev. *D A176 Package Type Operating Range 172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Commercial 176-pin Flat Pack 24 mm × 24 mm (TQFP) Commercial Page 26 of 29 CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V Package Diagrams 176-lead Thin Quad Flat Pack (24 × 24 × 1.4 mm) A176 51-85132-** Document #: 38-06070 Rev. *D Page 27 of 29 CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V Package Diagrams (continued) 172-Ball FBGA (15 x 15 x 1.25 mm) BB172 51-85114-*B Document #: 38-06070 Rev. *D Page 28 of 29 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V Document History Page Document Title: CY7C0850V/CY7C0851V/CY7C0852V/CY7C0853V FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM Document Number: 38-06070 REV. ECN NO. Issue Date Orig. of Change ** 127809 08/04/03 SPN This data sheet has been extracted from another data sheet: the 2M/4M/9M data sheet. The following changes have been made from the original as pertains to this device: Updated capacitance values Updated “Read-to-Write-to-Read (OE Controlled)” waveform Revised static discharge voltage Corrected 0853 pins L3 and L12 Added discussion of Pause/Restart for JTAG boundary scan Power up requirements added to Maximum Ratings information Revise tcd2, tOE, tOHZ, tCKHZ, tCKLZ for the CY7C0853V to 4.7 ns Updated Icc numbers Updated tHA, tHB, tHD for -100 speed Separated out from the 4M data sheet Added 133-MHz Industrial device to Ordering Information table YDT Changed mailbox addresses from 1FFFE and 1FFFF to 3FFFE and 3FFFF. Description of Change *A 210948 See ECN *B 216190 See ECN *C 231996 See ECN YDT Removed “A particular port can write to a certain location while another port is reading that location.” from Functional Description. *D 238938 See ECN WWZ Merged 0853 (9Mx36) with 0852 (4Mx36) and 0851(2Mx36), add 0850 (1M x36), to the datasheet. Added product selection table. Added JTAG ID code for 1M device. Added note 14. Updated boundry scan section section. Updated function description for the merge and addition. Document #: 38-06070 Rev. *D YDT/Dcon Corrected Revision of Document. CMS does not reflect this rev change Page 29 of 29