CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
3.3V 64K/128K/256K x 36 and 128K/256K x 18
Synchronous Dual-Port RAM
Features (all)
Functional Description (all)
— 64K × 36 (CY7C0851V)
The CY7C085XV/CY7C083XV are 2M, 4.5M, and 9M
pipelined, synchronous, true dual-port static RAMs that are
high-speed, low-power 3.3V CMOS. Two ports are provided,
permitting independent, simultaneous access for Reads from
any location in memory. A particular port can write to a certain
location while another port is reading that location. The result
of writing to the same location by more than one port at the
same time is undefined. Registers on control, address, and
data lines allow for minimal set-up and hold time.
— 256K × 18 (CY7C0832V)
Functional Description (all except CY7C0853V)
•
•
•
•
— 128K × 18 (CY7C0831V)
Pipelined output mode allows fast 150-MHz operation
0.18-micron CMOS for optimum speed and power
High-speed clock to data access: 4.0 ns (max.)
3.3V low operating power
— Active = 300 mA (typical)
•
•
•
•
•
•
•
•
•
— Standby = 10 mA (typical)
Interrupt flags for message passing
Global master reset
Separate byte enables on both ports
Commercial and industrial temperature ranges
IEEE 1149.1-compatible JTAG boundary scan
172-ball BGA (1 mm pitch) (15 mm × 15 mm)
120-pin TQFP (14 mm × 14 mm × 1.4 mm)
176-pin TQFP (24 mm × 24 mm × 1.4 mm)
FLEx36 devices are pin footprint upgradeable from
2M to 4M to 9M
During a Read operation, data is registered for decreased
cycle time. Clock to data valid tCD2 = 4.0 ns at 150 MHz. Each
port contains a burst counter on the input address register.
After externally loading the counter with the initial address, the
counter will increment the address internally (more details to
follow). The internal Write pulse width is independent of the
duration of the R/W input signal. The internal Write pulse is
self-timed to allow the shortest possible cycle times.
• True dual-ported memory cells that allow simultaneous
access of the same memory location
• Synchronous pipelined
• Organization of 2M, 4.5M, and 9M devices
— 256K × 36 (CY7C0853V)
— 128K × 36 (CY7C0852V)
Features (all except CY7C0853V)
• Counter wrap around control
— Internal mask register controls counter wrap-around
— Counter-interrupt flags to indicate wrap-around
— Memory block retransmit operation
• Counter readback on address lines
• Mask register readback on address lines
• Dual Chip Enables on both ports for easy depth
expansion
Cypress Semiconductor Corporation
Document #: 38-06059 Rev. *C
•
A HIGH on CE0 or LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce the static power
consumption. One cycle with chip enables asserted is required
to reactivate the outputs.
Counter enable (CNTEN) inputs are provided to stall the
operation of the address input and utilize the internal address
generated by the internal counter for fast, interleaved memory
applications. A port’s burst counter is loaded when the port’s
address strobe (ADS) and CNTEN signals are LOW. When the
port’s CNTEN is asserted and the ADS is deasserted, the
address counter will increment on each LOW to HIGH
transition of that port’s clock signal. This will Read/Write one
word from/into each successive address location until CNTEN
is deasserted. The counter can address the entire memory
array, and will loop back to the start. Counter reset (CNTRST)
is used to reset the unmasked portion of the burst counter to
0s. A counter-mask register is used to control the counter
wrap. The counter and mask register operations are described
in more detail in the following sections.
New features added to the CY7C08X1V/CY7C08X2V devices
include: readback of burst-counter internal address value on
address lines, counter-mask registers to control the counter
wrap-around, counter interrupt (CNTINT) flags, readback of
mask register value on address lines, retransmit functionality,
interrupt flags for message passing, JTAG for boundary scan,
and asynchronous Master Reset (MRST).
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised April 22, 2002
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Logic Block Diagram[1]
OEL
R/WL
OER
R/W R
B0L
B0R
B1L
B1R
B2L
B2R
B3L
B3R
[2]
[2]
CE0L
[2]
CE1L
DQ27L–DQ35L
DQ18L–DQ26L
DQ9L–DQ17L
DQ0L–DQ8L
CE0R
[2]
CE1R
9
9
9
9
I/O
Control
9
I/O
Control
9
9
9
Addr.
Read
Back
DQ27R–DQ35R
DQ18R–DQ26R
DQ9R–DQ17R
DQ0R–DQ8R
Addr.
Read
Back
True
Dual-Ported
RAM Array
A0L–A16L
17
CNT/MSKL[2]
17
Mask Register
Mask Register
Counter/
Address
Register
Counter/
Address
Register
ADSL[2]
CNTENL[2]
CNTRSTL[2]
CLKL[2]
Address
Address
Decode
Decode
Mirror Reg
Interrupt
INTL
Logic
ADSR[2]
CNTENR[2]
CNTRSTR[2]
Mirror Reg
CNTINTL[2]
MRST
Reset
Logic
TMS
TDI
TCK
JTAG
TDO
A0R–A16R
CNT/MSKR[2]
CLKR[2]
CNTINTR[2]
Interrupt
Logic
INTR
Notes:
1. CY7C0851V has 16 address bits instead of 17. CY7C0832V and CY7C0853V have 18 address bits instead of 17. CY7C083XV does not have B2 and B3
inputs. CY7C083XV does not have DQ18–DQ35 data bits. JTAG not implemented on CY7C083XV.
2. This feature is not available on the CY7C0853V.
Document #: 38-06059 Rev. *C
Page 2 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Pin Configurations
172-ball BGA
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DQ32L
DQ30L
CNTINTL
VSSQ
DQ13L
VDDQ
DQ11L
DQ11R
VDDQ
DQ13R
VSSQ
CNTINTR
DQ30R
DQ32R
A0L
DQ33L
DQ29L
DQ17L
DQ14L
DQ12L
DQ9L
DQ9R
DQ12R
DQ14R
DQ17R
DQ29R
DQ33R
A0R
NC
A1L
DQ31L
DQ27L
INTL
DQ15L
DQ10L
DQ10R
DQ15R
INTR
DQ27R
DQ31R
A1R
NC
A2L
A3L
DQ35L
DQ34L
DQ28L
DQ16L
VSSQ
VSSQ
DQ16R
DQ28R
DQ34R
DQ35R
A3R
A2R
A4L
A5L
CE1L
B0L
VDDQ
VSSA
VDDA
VDDQ
B0R
CE1R
A5R
A4R
VDD
A6L
A7L
B1L
VDDA
VSSA
B1R
A7R
A6R
VDD
OEL
B2L
B3L
CE0L
CE0R
B3R
B2R
OER
VSS
R/WL
A8L
CLKL
CLKR
A8R
R/WR
VSS
A9L
A10L
VSS
ADSL
VSSA
VDDA
ADSR
MRST
A10R
A9R
A11L
A12L
A15L
CNTRSTL
VDDQ
VDDA
VSSA
VDDQ
CNTRSTR
A15R
A12R
A11R
CNT/MSKL
A13L
CNTENL
DQ26L
DQ25L
DQ19L
VSSQ
VSSQ
DQ19R
DQ25R
DQ26R
CNTENR
A13R
CNT/MSKR
A16L[3]
A14L
DQ22L
DQ18L
TDI
DQ7L
DQ2L
DQ2R
DQ7R
TCK
DQ18R
DQ22R
A14R
A16R[3]
DQ24L
DQ20L
DQ8L
DQ6L
DQ5L
DQ3L
DQ0L
DQ0R
DQ3R
DQ5R
DQ6R
DQ8R
DQ20R
DQ24R
DQ23L
DQ21L
TDO
VSSQ
DQ4L
VDDQ
DQ1L
DQ1R
VDDQ
DQ4R
VSSQ
TMS
DQ21R
DQ23R
A
B
C
D
E
F
CY7C0851V
CY7C0852V
G
H
J
K
L
M
N
P
Note:
3. For CY7C0851V, pins M1 and M14 are NC.
Document #: 38-06059 Rev. *C
Page 3 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Pin Configurations (continued)
172-ball BGA
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DQ32L
DQ30L
NC
VSSQ
DQ13L
VDDQ
DQ11L
DQ11R
VDDQ
DQ13R
VSSQ
NC
DQ30R
DQ32R
A0L
DQ33L
DQ29L
DQ17L
DQ14L
DQ12L
DQ9L
DQ9R
DQ12R
DQ14R
DQ17R
DQ29R
DQ33R
A0R
A17L
A1L
DQ31L
DQ27L
INTL
DQ15L
DQ10L
DQ10R
DQ15R
INTR
DQ27R
DQ31R
A1R
A17R
A2L
A3L
DQ35L
DQ34L
DQ28L
DQ16L
VSSQ
VSSQ
DQ16R
DQ28R
DQ34R
DQ35R
A3R
A2R
A4L
A5L
VDD
B0L
VDDQ
VSSA
VDDA
VDDQ
B0R
VDD
A5R
A4R
VDD
A6L
A7L
B1L
VDDA
VSSA
B1R
A7R
A6R
VDD
OEL
B2L
B3L
VSS
VSS
B3R
B2R
OER
VSS
R/WL
A8L
CLKL
CLKR
A8R
R/WR
VSS
A9L
A10L
VSS
VSS
VSSA
VDDA
VSS
MRST
A10R
A9R
A11L
A12L
A15L
VDD
VDDQ
VDDA
VSSA
VDDQ
VDD
A15R
A12R
A11R
VDD
A13L
VSS
DQ26L
DQ25L
DQ19L
VSSQ
VSSQ
DQ19R
DQ25R
DQ26R
VSS
A13R
VDD
A16L
A14L
DQ22L
DQ18L
TDI
DQ7L
DQ2L
DQ2R
DQ7R
TCK
DQ18R
DQ22R
A14R
A16R
DQ24L
DQ20L
DQ8L
DQ6L
DQ5L
DQ3L
DQ0L
DQ0R
DQ3R
DQ5R
DQ6R
DQ8R
DQ20R
DQ24R
DQ23L
DQ21L
TDO
VSSQ
DQ4L
VDDQ
DQ1L
DQ1R
VDDQ
DQ4R
VSSQ
TMS
DQ21R
DQ23R
A
B
C
D
E
F
CY7C0853V
G
H
J
K
L
M
N
P
Document #: 38-06059 Rev. *C
Page 4 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
A3L
VSS
VDD
7
8
9
A4L
A5L
10
11
A6L
CE1L
B2L
12
13
14
15
16
17
B3L
18
OE L
CE0L
19
20
21
22
DQ32R
DQ33R
133
DQ31R
DQ30R
VSS
VDD
136
135
134
137
DQ27R
DQ29R
DQ28R
139
138
140
DQ16R
CNTINTR
INTR
142
141
143
DQ14R
DQ17R
DQ15R
145
144
146
VSS
DQ13R
148
147
VDD
150
149
DQ11R
DQ12R
151
DQ10R
153
152
DQ9L
DQ9R
154
DQ10L
156
155
DQ12L
DQ11L
157
VDD
159
158
DQ13L
VSS
160
DQ14L
162
161
DQ15L
DQ17L
163
DQ16L
165
164
INTL
CNTINTL
166
DQ27L
168
167
DQ28L
DQ29L
169
DQ30L
171
170
VDD
VSS
172
Document #: 38-06059 Rev. *C
DQ35R
NC
A0R
A1R
A2R
A3R
VSS
VDD
A4R
A5R
120
119
118
117
116
115
A7R
B0R
A6R
B1R
CE1R
B2R
B3R
114
113
112
111
110
OER
CE0R
109
108
107
106
105
104
103
VSS
R/WR
VDD
VDD
VSS
CLKR
MRST
ADSR
CNTENR
CNTRSTR
CNT/MSKR
A8R
A9R
A10R
A11R
A12R
96
VSS
95
94
93
VDD
A13R
92
91
90
89
A15R
A16R
A14R
DQ24R
DQ20R
DQ23R
DQ26R
DQ22R
85
86
87
84
VSS
VDD
DQ21R
82
83
81
DQ19R
DQ25R
DQ18R
79
80
78
TMS
TCK
DQ8R
76
77
75
DQ6R
DQ7R
DQ5R
73
74
71
72
VSS
DQ4R
VDD
70
68
69
DQ2R
DQ3R
DQ1R
67
65
66
DQ0L
DQ0R
DQ1L
64
62
63
DQ3L
DQ2L
VDD
61
59
60
DQ4L
VSS
DQ5L
58
56
57
DQ7L
DQ6L
DQ24L
DQ20L
DQ8L
40
41
42
43
44
55
A14L
A15L
A16L
53
54
38
39
TDI
TDO
VDD
A13L
DQ18L
36
37
52
VSS
50
51
A10L
A11L
A12L
DQ34R
123
122
121
102
101
100
99
98
97
31
32
33
34
35
DQ25L
DQ19L
A8L
A9L
DQ21L
CNTRSTL
CNT/MSKL
28
29
30
49
CNTENL
CY7C0852V
23
24
25
26
27
47
48
CLK L
VSS
ADSL
CY7C0851V
VDD
VSS
VSS
R/WL
125
124
DQ22L
VDD
VDD
VSS
129
128
127
126
45
46
B1L
132
131
130
DQ26L
DQ23L
A7L
B0L
176-pin Thin Quad Flat Pack (TQFP)
Top View
88
A2L
4
5
6
A1L
DQ31L
2
3
174
173
1
DQ35L
NC
A0L
DQ33L
DQ32L
DQ34L
176
175
Pin Configurations (continued)
Page 5 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Pin Configurations (continued)
A2L
A3L
VSS
VDD
A4L
A5L
A6L
A7L
CE1L
B0L
B1L
OEL
CE0L
VDD
VSS
R/WL
CLKL
VSS
ADSL
CNTENL
CNTRSTL
CNT/MSKL
A8L
A9L
A10L
A11L
A12L
VSS
VDD
DQ12R
VSS
VDD
DQ13R
DQ14R
DQ15R
DQ16R
DQ17R
A0R
A1R
INTR
DQ9R
DQ10R
DQ11R
DQ15L
DQ14L
DQ13L
VDD
VSS
DQ12L
DQ11L
DQ10L
DQ9L
INTL
CNTINTL
CNTINTR
CY7C0831V
CY7C0832V
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
A2R
A3R
VSS
VDD
A4R
A5R
A6R
A7R
CE1R
B0R
B1R
OER
CE0R
VDD
VSS
R/WR
CLKR
MRST
ADSR
CNTENR
CNTRSTR
CNT/MSKR
A8R
A9R
A10R
A11R
A12R
VSS
VDD
A13R
VDD
DQ4R
DQ5R
DQ6R
DQ7R
DQ8R
A17R[3]
A16R
A15R
A14R
DQ1R
DQ2R
DQ3R
VSS
DQ8L
DQ7L
DQ6L
DQ5L
DQ4L
VDD
VSS
DQ3L
DQ2L
DQ1L
DQ0L
DQ0R
A14L
A15L
A16L
A17L[3]
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
A13L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
A1L
A0L
DQ17L
DQ16L
120-pin Thin Quad Flat Pack (TQFP)[4]
Top View
Selection Guide
CY7C0853V
CY7C0851V
CY7C0852V
CY7C0853V[6]
-150
CY7C0853V
CY7C0851V
CY7C0852V
CY7C0853V
-133
CY7C0853V
CY7C0851V
CY7C0852V
CY7C0853V
-100
Unit
fMAX
150
133
100
MHz
Max. Access Time (Clock to Data)
4.0
4.4
5
ns
Typical Operating Current ICC
300
270
200
mA
Typical Standby Current for ISB3
(Both Ports CMOS Level)[5]
10
10
10
mA
Notes:
4. NC for CY7C0831V.
5. Not applicable for CY7C0853V.
6. For CY7C0853V all 150 MHz values are advance information.
Document #: 38-06059 Rev. *C
Page 6 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Pin Definitions
Left Port
Right Port
Description
A0L–A16L[1]
A0R–A16R[1]
Address Inputs.
ADSL
ADSR
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW
for the part using the externally supplied address on the address pins and for loading this
address into the burst address counter.
CE0L
CE0R
Active LOW Chip Enable Input.[2]
CE1L
CE1R
Active HIGH Chip Enable Input.[2]
CLKL
CLKR
Clock Signal. Maximum clock input rate is fMAX.
CNTENL
CNTENR
Counter Enable Input.[2] Asserting this signal LOW increments the burst address counter
of its respective port on each rising edge of CLK. The increment is disabled if ADS or
CNTRST are asserted LOW.
CNTRSTL
CNTRSTR
Counter Reset Input.[2] Asserting this signal LOW resets to zero the unmasked portion of
the burst address counter of its respective port. CNTRST is not disabled by asserting ADS
or CNTEN.
CNT/MSKL
CNT/MSKR
Address Counter Mask Register Enable Input.[2] Asserting this signal LOW enables
access to the mask register. When tied HIGH, the mask register is not accessible and the
address counter operations are enabled based on the status of the counter control signals.
DQ0L–DQ35L[1]
DQ0R–DQ35R[1] Data Bus Input/Output.
OEL
OER
Output Enable Input. This asynchronous signal must be asserted LOW to enable the DQ
data pins during Read operations.
INTL
INTR
Mailbox Interrupt Flag Output. The mailbox permits communications between ports. The
upper two memory locations can be used for message passing. INTL is asserted LOW when
the right port writes to the mailbox location of the left port, and vice versa. An interrupt to a
port is deasserted HIGH when it reads the contents of its mailbox.
CNTINTL
CNTINTR
Counter Interrupt Output.[2] This pin is asserted LOW when the unmasked portion of the
counter is incremented to all “1s.”
R/WL
R/WR
Read/Write Enable Input. Assert this pin LOW to write to, or HIGH to Read from the dual
port memory array.
B0L–B3L
B0R–B3R
Byte Select Inputs. Asserting these signals enables Read and Write operations to the
corresponding bytes of the memory array.
MRST
Master Reset Input. MRST is an asynchronous input signal and affects both ports.
Asserting MRST LOW performs all of the reset functions as described in the text. A MRST
operation is required at power-up.
TMS
JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State
machine transitions occur on the rising edge of TCK.
TDI
JTAG Test Data Input. Data on the TDI input will be shifted serially into selected registers.
TCK
JTAG Test Clock Input.
TDO
JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally
three-stated except when captured data is shifted out of the JTAG TAP.
VSS
Ground Inputs.
VDD
Power Inputs.
Document #: 38-06059 Rev. *C
Page 7 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
Master Reset
The CY7C0831V undergoes a complete reset by taking its
MRST input LOW. The MRST input can switch asynchronously to the clocks. An MRST initializes the internal burst
counters to zero, and the counter mask registers to all ones
(completely unmasked). MRST also forces the Mailbox
Interrupt (INT) flags and the Counter Interrupt (CNTINT) flags
HIGH. MRST must be performed on the CY7C0831V after
power-up.
Mailbox Interrupts
The upper two memory locations may be used for message
passing and permit communications between ports. Table 2
shows the interrupt operation for both ports. The highest
memory location, 1FFFF is the mailbox for the right port and
1FFFE is the mailbox for the left port. Table 2 shows that in
CY7C0831V/CY7C0832V
order to set the INTR flag, a Write operation by the left port to
address 1FFFF will assert INTR LOW. At least one byte has to
be active for a Write to generate an interrupt. A valid Read of
the 1FFFF location by the right port will reset INTR HIGH. At
least one byte has to be active in order for a Read to reset the
interrupt. When one port Writes to the other port’s mailbox, the
INT of the port that the mailbox belongs to is asserted LOW.
The INT is reset when the owner (port) of the mailbox Reads
the contents of the mailbox. The interrupt flag is set in
a flow-thru mode (i.e., it follows the clock edge of the writing
port). Also, the flag is reset in a flow-thru mode (i.e., it follows
the clock edge of the reading port).
Each port can read the other port’s mailbox without resetting
the interrupt. And each port can write to its own mailbox
without setting the interrupt. If an application does not require
message passing, INT pins should be left open.
Table 1. Address Counter and Counter-Mask Register Control Operation (Any Port)[2, 7, 8]
CLK
MRST
CNT/MSK
CNTRST
ADS
CNTEN
X
L
X
X
X
X
Master Reset
Operation
Reset address counter to all 0s and mask
register to all 1s.
Description
H
H
L
X
X
Counter Reset
Reset counter unmasked portion to all 0s.
H
H
H
L
L
Counter Load
Load counter with external address value
presented on address lines.
H
H
H
L
H
Counter
Readback
Read out counter internal value on
address lines.
H
H
H
H
L
Counter Increment Internally increment address counter
value.
H
H
H
H
H
Counter Hold
Constantly hold the address value for
multiple clock cycles.
H
L
L
X
X
Mask Reset
Reset mask register to all 1s.
H
L
H
L
L
Mask Load
Load mask register with value presented
on the address lines.
H
L
H
L
H
Mask Readback
Read out mask register value on address
lines.
H
L
H
H
X
Reserved
Operation undefined
Table 2. Interrupt Operation Example [1, 9, 10, 11]
Left Port
Function
Right Port
R/WL
CEL
A0L–16L
INTL
R/WR
CER
A0R–16R
INTR
Set Right INTR Flag
L
L
1FFFF
X
X
X
X
L
Reset Right INTR Flag
X
X
X
X
H
L
1FFFF
H
Set Left INTL Flag
X
X
X
L
L
L
1FFFE
X
Reset Left INTL Flag
H
L
1FFFE
H
X
X
X
X
Notes:
7. “X” = “Don’t Care,” “H” = HIGH, “L” = LOW.
8. Counter operation and mask register operation is independent of chip enables.
9. CE is internal signal. CE = LOW if CE0 = LOW and CE1 = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the
CLK and can be deasserted after that. Data will be out after the following CLK edge and will be three-stated after the next CLK edge.
10. OE is “Don’t Care” for mailbox operation.
11. At least one of B0, B1, B2, or B3 must be LOW.
Document #: 38-06059 Rev. *C
Page 8 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
Address Counter and Mask Register
Operations [2, 12]
Each port of the CY7C085XV/CY7C083XV has a programmable burst address counter. The burst counter contains three
17-bit registers: a counter register, a mask register, and a
mirror register.
The counter register contains the address used to access the
RAM array. It is changed only by the Counter Load, Increment,
Counter Reset, and by master reset (MRST) operations.
The mask register value affects the Increment and Counter
Reset operations by preventing the corresponding bits of the
counter register from changing. It also affects the counter
interrupt output (CNTINT). The mask register is changed only
by the Mask Load and Mask Reset operations, and by the
MRST. The mask register defines the counting range of the
counter register. It divides the counter register into two
regions: zero or more “0s” in the most significant bits define
the masked region, one or more “1s” in the least significant bits
define the unmasked region. Bit 0 may also be “0,” masking
the least significant counter bit and causing the counter to
increment by two instead of one.
The mirror register is used to reload the counter register on
increment operations (see “retransmit,” below). It always
contains the value last loaded into the counter register, and is
changed only by the Counter Load, and Counter Reset operations, and by the MRST.
Table 1 summarizes the operation of these registers and the
required input control signals. The MRST control signal is
asynchronous. All the other control signals in Table 1
(CNT/MSK, CNTRST, ADS, CNTEN) are synchronized to the
port’s CLK. All these counter and mask operations are
independent of the port’s chip enable inputs (CE0 and CE1).
Counter Load Operation
The address counter and mirror registers are both loaded with
the address value presented at the address lines. This value
ranges from 0 to 1FFFF.
Mask Load Operation
The mask register is loaded with the address value presented
at the address lines. This value ranges from 0 to 1FFFF,
although not all values permit correct increment operations.
Permitted values are of the form 2n – 1 or 2n – 2. From the
most significant bit to the least significant bit, permitted values
have zero or more “0s,” one or more “1s,” or one “0.” Thus
1FFFF, 003FE, and 00001 are permitted values, but 1F0FF,
003FC, and 00000 are not.
Counter Readback Operation
The internal value of the counter register can be read out on
the address lines. Readback is pipelined; the address will be
valid tCA2 after the next rising edge of the port’s clock. If
address readback occurs while the port is enabled (CE0 LOW
and CE1 HIGH), the data lines (DQs) will be three-stated.
Figure 1 shows a block diagram of the operation.
CY7C0831V/CY7C0832V
Mask Readback Operation
The internal value of the mask register can be read out on the
address lines. Readback is pipelined; the address will be valid
tCM2 after the next rising edge of the port’s clock. If mask
readback occurs while the port is enabled (CE0 LOW and CE1
HIGH), the data lines (DQs) will be three-stated. Figure 1
shows a block diagram of the operation.
Mask Reset Operation
The mask register is reset to all “1s,” which unmasks every bit
of the counter. Master reset (MRST) also resets the mask
register to all “1s.”
Counter Reset Operation
All unmasked bits of the counter and mirror registers are reset
to “0.” All masked bits remain unchanged. A Mask Reset
followed by a Counter Reset will reset the counter and mirror
registers to 00000, as will master reset (MRST).
Increment Operation
Once the address counter register is initially loaded with an
external address, the counter can internally increment the
address value, potentially addressing the entire memory array.
Only the unmasked bits of the counter register are incremented. The corresponding bit in the mask register must be
a “1” for a counter bit to change. The counter register is incremented by 1 if the least significant bit is unmasked, and by 2
if it is masked. If all unmasked bits are “1,” the next increment
will wrap the counter back to the initially loaded value. If an
Increment results in all the unmasked bits of the counter being
“1s,” a counter interrupt flag (CNTINT) is asserted. The next
Increment will return the counter register to its initial value,
which was stored in the mirror register. The counter address
can instead be forced to loop to 00000 by externally
connecting CNTINT to CNTRST.[13] An increment that results
in one or more of the unmasked bits of the counter being “0”
will de-assert the counter interrupt flag. The example in
Figure 2 shows the counter mask register loaded with a mask
value of 0003Fh unmasking the first 6 bits with bit “0” as the
LSB and bit “16” as the MSB. The maximum value the mask
register can be loaded with is 1FFFFh. Setting the mask
register to this value allows the counter to access the entire
memory space. The address counter is then loaded with an
initial value of 8h. The base address bits (in this case, the 6th
address through the 16th address) are loaded with an address
value but do not increment once the counter is configured for
increment operation. The counter address will start at address
8h. The counter will increment its internal address value till it
reaches the mask register value of 3Fh. The counter wraps
around the memory block to location 8h at the next count.
CNTINT is issued when the counter reaches its maximum
value.
Hold Operation
The value of all three registers can be constantly maintained
unchanged for an unlimited number of clock cycles. Such
operation is useful in applications where wait states are
needed, or when address is available a few cycles ahead of
data in a shared bus interface.
Notes:
12. This section describes the CY7C0852V and CY7C0831V, which have 17 address bits and a maximum address value of 1FFFF. The CY7C0832V has 18 address
bits, register lengths of 18 bits, and a maximum address value of 3FFFF. The CY7C0851V has 16 address bits, register lengths of 16 bits, and a maximum
address value of FFFF.
13. CNTINT and CNTRST specs are guaranteed by design to operate properly at speed grade operating frequency when tied together.
Document #: 38-06059 Rev. *C
Page 9 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
Counter Interrupt
CY7C0831V/CY7C0832V
The counter interrupt (CNTINT) is asserted LOW when an
increment operation results in the unmasked portion of the
counter register being all “1s.” It is deasserted HIGH when an
Increment operation results in any other value. It is also
de-asserted by Counter Reset, Counter Load, Mask Reset
and Mask Load operations, and by MRST.
the counter unmasked portion reaches its maximum value set
by the mask register, it wraps back to the initial value stored in
this “mirror register.” If the counter is continuously configured
in increment mode, it increments again to its maximum value
and wraps back to the value initially stored into the “mirror
register.” Thus, the repeated access of the same data is
allowed without the need for any external logic.
Retransmit
Counting by Two
Retransmit is a feature that allows the Read of a block of
memory more than once without the need to reload the initial
address. This eliminates the need for external logic to store
and route data. It also reduces the complexity of the system
design and saves board space. An internal “mirror register” is
used to store the initially loaded address counter value. When
When the least significant bit of the mask register is “0,” the
counter increments by two. This may be used to connect the
CY7C0851V/CY7C0852V as a 72-bit single port SRAM in
which the counter of one port counts even addresses and the
counter of the other port counts odd addresses. This even-odd
address scheme stores one half of the 72-bit data in even
memory locations, and the other half in odd memory locations.
Document #: 38-06059 Rev. *C
Page 10 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
CNT/MSK
CNTEN
Decode
Logic
ADS
CNTRST
MRST
Bidirectional
Address
Lines
Mask
Register
Counter/
Address
Register
Address
RAM
Decode
Array
CLK
From
Address
Lines
Load/Increment
17
Mirror
Counter
1
To Readback
and Address
Decode
1
0
From
Mask
Register
0
17
Increment
Logic
Wrap
17
From
Mask
From
Counter
17
17
Bit 0
17
+1
Wrap
Detect
1
+2
Wrap
0
1
0
17
To
Counter
Figure 1. Counter, Mask, and Mirror Logic Block Diagram[1]
Document #: 38-06059 Rev. *C
Page 11 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
Example:
Load
Counter-Mask
Register = 3F
CNTINT
H
0
0
0s
216 215
H
X X
Xs
216 215
Max
Address
Register
L
X X
H
X X
216 215
1
1
1
1
1
Unmasked Address
X 0
0
1
0
0
Xs
X 1 1
1
1
Mask
Register
bit-0
0
26 25 24 23 22 21 20
216 215
Max + 1
Address
Register
0 1
26 25 24 23 22 21 20
Masked Address
Load
Address
Counter = 8
CY7C0831V/CY7C0832V
1
Address
Counter
bit-0
1
26 25 24 23 22 21 20
Xs
X 0
0
1
0 0
0
26 25 24 23 22 21 20
Figure 2. Programmable Counter-Mask Register Operation[1, 14]
IEEE 1149.1 Serial Boundary Scan (JTAG) [15]
The CY7C0851V/CY7C0852V/CY7C0853V incorporates an
IEEE 1149.1 serial boundary scan test access port (TAP). The
TAP controller functions in a manner that does not conflict with
the operation of other devices using 1149.1-compliant TAPs.
The TAP operates using JEDEC standard 3.3V I/O logic
levels. It is composed of three input connections and one
output connection required by the test logic defined by the
standard.
Disabling the JTAG Feature
It is possible to operate the CY7C0851V/CY7C0852V/
CY7C0853V without using the JTAG feature. To disable the
TAP controller, TCK must be tied LOW (VSS) to prevent
clocking of the device. TDI and TMS are internally pulled up
and may be unconnected. They may alternatively be
connected to VDD through a pull-up resistor. TDO should be
left unconnected.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the MSB on any register.
Test Data Out (TDO)
The TDO output pin is used to serially clock data out from the
registers. The output is active depending upon the current
state of the TAP state machine (see TAP Controller State
Diagram [FSM]). The output changes on the falling edge of
TCK. TDO is connected to the LSB of any register.
Performing a TAP Reset
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
A reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This reset does not affect the operation of the
CY7C0851V/CY7C0852V/CY7C0853V,
and
may
be
performed while the device is operating. An MRST must be
performed on the CY7C0851V/CY7C0852V/CY7C0853V
after power-up.
Test Mode Select (TMS)
Performing a Pause/Restart
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
When a SHIFT-DR PAUSE-DR SHIFT-DR is performed the
scan chain will output the next bit in the chain twice. For
example, if the value expected from the chain is 1010101, the
device will output a 11010101. This extra bit will cause some
testers to report an erroneous failure for the
CY7C0851/CY7C0852/CY7C0853 in a scan test. Therefore
the tester should be configured to never enter the PAUSE-DR
state.
Test Access Port–Test Clock (TCK)
Notes:
14. The “X” in this diagram represents the counter upper bits.
15. Boundary scan is IEEE 1149.1-compatible. See “Performing a Pause/Restart” for deviation from strict 1149.1 compliance.
Document #: 38-06059 Rev. *C
Page 12 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the
CY7C0851V/CY7C0852V/CY7C0853V test circuitry. Only one
register can be selected at a time through the instruction
registers. Data is serially loaded into the TDI pin on the rising
edge of TCK. Data is output on the TDO pin on the falling edge
of TCK.
Instruction Register (IR)
Four-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in Figure 4, the JTAG/BIST
Controller Block Diagram. On power-up, the instruction
register is loaded with the IDCODE instruction. It is also loaded
with the IDCODE instruction if the controller is placed in a reset
state, as described in the previous section.
When the TAP controller is in the CaptureIR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.
Bypass Register (BYR)
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain devices. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
CY7C0851V/CY7C0852V/CY7C0853V with minimal delay.
The bypass register is set to “0” on the rising edge of TCK
following entry into the Capture-DR state, if the current
instruction causes the bypass register to be in the serial path
between TDI and TDO.
Boundary Scan Register (BSR)
The boundary scan register is connected to all the input and
output pins on the CY7C0851V/CY7C0852V/CY7C0853V,
except the MRST pin. The boundary scan register is loaded
with the contents of the CY7C0851V/CY7C0852V/
CY7C0853V input and output ring when the TAP controller is
in the Capture-DR state. It is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST and SAMPLE/PRELOAD instructions can be
used to capture the contents of the input and output ring.
Identification Register (IDR)
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
in the instruction register. The IDCODE is hardwired into the
CY7C0851V/CY7C0852V/CY7C0853V and can be shifted out
when the TAP controller is in the Shift-DR state. The ID
register has a vendor code and other information described in
the Identification Register Definitions table.
TAP Instruction Set
Sixteen different instructions are possible with the four-bit
instruction register. All combinations are listed in Table 5.
Other code combinations are listed as RESERVED and should
not be used.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
Document #: 38-06059 Rev. *C
CY7C0831V/CY7C0832V
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST allows circuitry external to the CY7C0851V/
CY7C0852V/CY7C0853V package to be tested. Boundaryscan register cells at output pins are used to apply test stimuli,
while those at input pins capture test results.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
is loaded into the instruction register on power-up or whenever
the TAP controller is given a test logic reset state. The
IDCODE value for the CY7C0851V is 0C001069h. The
IDCODE value for the CY7C0852V is 0C002069h. The
IDCODE value for the CY7C0853V is 0C002069h.
High-Z
The High-Z instruction causes the bypass register to be
connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. It also places all CY7C0851V/
CY7C0852V/CY7C0853V outputs into a High-Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions loaded into the
instruction register and the TAP controller in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the
CY7C0851V/CY7C0852V/CY7C0853V clock operates more
than an order of magnitude faster. Because there is a large
difference in the clock frequencies, it is possible that during the
Capture-DR state, an input or output will undergo a transition.
The TAP may then try to capture a signal while in transition
(metastable state). This will not harm the device, but there is
no guarantee as to the value that will be captured. Repeatable
results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the CY7C0851V/CY7C0852V/
CY7C0853V signal must be stabilized long enough to meet the
TAP controller's capture set-up plus hold times. Once the data
is captured, it is possible to shift out the data by putting the TAP
into the Shift-DR state. This places the boundary scan register
between the TDI and TDO pins. If the TAP controller goes into
the Update-DR state, the sampled data will be updated.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected on
a board.
Page 13 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CLAMP
The optional CLAMP instruction allows the state of the signals
driven from CY7C0851V/CY7C0852V/CY7C0853V pins to be
determined from the boundary-scan register while the
BYPASS register is selected as the serial path between TDI
and TDO. CLAMP controls boundary cells to 1 or 0.
NBSRST
This is the Non-Boundary Scan Reset instruction. NBSRST
places the Bypass Register (BYR) between TDI and TDO
when selected. Its function is to reset every logic (similar to
MRST) except that it does not reset the JTAG logic.
Boundary Scan Cells (BSC)
Every CY7C0851V/CY7C0852V/CY7C0853V output has two
boundary scan cells; one for data, and one for three-state
1
CY7C0831V/CY7C0832V
control. JTAG TAP pins (TDI, TMS, TDO, TCK), MRST, and all
power and ground pins have no scan cell. Other
CY7C0851V/CY7C0852V/CY7C0853V inputs have only the
data scan cell.
Active and Standby Supply Current[17]
When the instruction in the JTAG instruction register selects
the Boundary Scan Register (BSR) and the TAP controller is
in any state except TEST-LOGIC-RESET or RUN-TEST/IDLE,
then the device supply current (ICC or ISB1/2/3/4) will
increase. With the JTAG logic in this state, and both ports
inactive with CMOS input levels, it is possible for the supply
current to exceed the ISB3 value given in the Electrical
Characteristics section of this datasheet.
TEST-LOGIC
RESET
0
0
RUN_TEST/
IDLE
1
1
1
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
SHIFT-IR
0
1
1
1
EXIT1-DR
0
0
PAUSE-DR
0
PAUSE-IR
1
1
0
EXIT2-DR
EXIT2-IR
1
1
UPDATE-DR
1
1
EXIT1-IR
0
0
0
0
UPDATE-IR
1
0
Figure 3. TAP Controller State Diagram (FSM)[16]
Notes:
16. The “0”/”1” next to each state represents the value at TMS at the rising edge of CLK.
17. ISB3 values only if JTAG pins are not active and mpdaster reset (MRST) not enabled.
Document #: 38-06059 Rev. *C
Page 14 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
0
Bypass Register (BYR)
3
2
1
0
Instruction Register (IR)
Selection
TDI
TDO
Circuitry
31
30
29
0
Identification Register (IDR)
n-1
(MUX)
0
Boundary Scan Register (BSR)
TCK
TAP
TMS
CONTROLLER
MRST
Figure 4. JTAG TAP Controller Block Diagram
Table 3. Identification Register Definitions
Instruction Field
Value
Revision Number (31:28)
Description
0h
Reserved for version number.
C002h
Defines Cypress part number for CY7C0852V.
Cypress JEDEC ID (11:1)
034h
Allows unique identification of CY7C0851V/CY7C0852V/
CY7C0853V vendor.
ID Register Presence (0)
1
Indicates the presence of an ID register.
[18]
Cypress Device ID
(27:12)
Table 4. Scan Registers Sizes
Register Name
Bit Size
Instruction
4
Bypass
1
Identification
32
Boundary Scan
n
Note:
18. Cypress Device ID is C001h for Cypress part CY7C0851V.
Document #: 38-06059 Rev. *C
Page 15 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Table 5. Instruction Identification Codes
Instruction
Code
Description
EXTEST
0000
Captures the Input/Output ring contents. Places the BSR between the TDI and TDO.
BYPASS
1111
Places the BYR between TDI and TDO.
IDCODE
1011
Loads the IDR with the vendor ID code and places the register between TDI and TDO.
HIGHZ
0111
Places BYR between TDI and TDO. Forces all CY7C0851V/CY7C0852V/ CY7C0853V
output drivers to a High-Z state.
CLAMP
0100
Controls boundary to 1/0. Places BYR between TDI and TDO.
SAMPLE/PRELOAD
1000
Captures the input/output ring contents. Places BSR between TDI and TDO.
NBSRST
1100
Resets the non-boundary scan logic. Places BYR between TDI and TDO.
RESERVED
All other codes
Other combinations are reserved. Do not use other than the above.
Document #: 38-06059 Rev. *C
Page 16 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
DC Input Voltage .............................. –0.5V to VDD + 0.5V[19]
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... > 2000V
Storage Temperature ................................ –65°C to + 150°C
(JEDEC JESD22-A114-2000B)
Ambient Temperature with
Power Applied............................................–55°C to + 125°C
Latch-up Current..................................................... > 200 mA
Operating Range
Supply Voltage to Ground Potential .............. –0.5V to + 4.6V
Range
DC Voltage Applied to
Outputs in High-Z State .........................–0.5V to VDD + 0.5V
Ambient Temperature
VDD
0°C to +70°C
3.3V ± 165 mV
–40°C to +85°C
3.3V ± 165 mV
Commercial
Industrial
Electrical Characteristics Over the Operating Range
CY7C0851V/CY7C0852V/CY7C0853V[6]
CY7C0831V/CY7C0832V
-150
Parameter
Description
-133
-100
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
VOH
Output HIGH Voltage (VDD = Min., IOH= –4.0 mA) 2.4
VOL
Output LOW Voltage (VDD = Min., IOL= +4.0 mA)
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
2.4
2.4
0.4
2.0
V
0.4
2.0
0.4
V
0.8
V
2.0
0.8
V
0.8
IOZ
Output Leakage Current
–10
10
–10
10
–10
10
µA
IIX1
Input Leakage Current Except TDI, TMS, MRST
–10
10
–10
10
–10
10
µA
IIX2
Input Leakage Current TDI, TMS, MRST
–0.1
1.0
–0.1
1.0
–0.1
ICC
Operating Current (VDD = Max.,
IOUT = 0 mA) Outputs Disabled
ISB1[5]
Standby Current (Both Ports TTL
Level) CEL and CER ≥ VIH, f = fMAX
ISB2[5]
Standby Current (One Port TTL Level)
CEL | CER ≥ VIH, f = fMAX
ISB3[17,5]
Standby Current (Both Ports CMOS
Level) CEL and CER ≥ VDD – 0.2V, f = 0
ISB4[5]
Standby Current (One Port CMOS
Level) CEL | CER ≥ VIH, f = fMAX
Com’l.
1.0
mA
300
450
270
400
200
310
mA
40
120
35
115
25
110
230
280
220
250
145
190
10
75
10
75
10
75
200
255
180
230
130
175
Indust.
Com’l.
mA
Indust.
Com’l.
mA
Indust.
Com’l.
mA
mA
Indust.
Com’l.
mA
mA
mA
Indust.
mA
mA
Shaded areas contain advance information.
Capacitance
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VDD = 3.3V
Max. (all)
Max. (CY7C0853)
Unit
13
22
pF
10
20
pF
Notes:
19. Pulse width < 20 ns.
20. (Internal I/O pad Capacitance = 10 pF) + AC Test Load.
21. External AC Test Load Capacitance = 10 pF.
22. Except JTAG signals (tr and tf < 10 ns [max.]).
Document #: 38-06059 Rev. *C
Page 17 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
AC Test Load and Waveforms
3.3V
Z0 = 50Ω
R = 50Ω
R1 = 590 Ω
OUTPUT
OUTPUT
C = 10 pF
C = 5 pF
VTH = 1.5V
(a) Normal Load (Load 1)
R2 = 435 Ω
(b) Three-state Delay (Load 2)
3.0V
90%
ALL INPUT PULSES
90%
10%
Vss
10%
< 2 ns
< 2 ns
Switching Characteristics Over the Operating Range
CY7C0851V/CY7C0852V/CY7C0853V[6]
CY7C0831V/CY7C0832V
-150
Parameter
Description
Min.
-133
Max.
Min.
Min.
133
Max.
Unit
100
MHz
fMAX2
Maximum Operating Frequency
tCYC2
Clock Cycle Time
6.7
7.5
10
ns
tCH2
Clock HIGH Time
2.7
3.0
4.0
ns
tCL2
Clock LOW Time
2.7
3.0
4.0
ns
tR
Clock Rise Time
tF
Clock Fall Time
tSA
Address Set-Up Time
2.3
2.5
3.0
ns
tHA
Address Hold Time
0.6
0.6
0.5
ns
tSB
Byte Select Set-Up Time
2.3
2.5
3.0
ns
tHB
Byte Select Hold Time
0.6
0.6
0.5
ns
tSC
Chip Enable Set-Up Time
2.3
2.5
3.0
ns
tHC
Chip Enable Hold Time
0.6
0.6
0.5
ns
tSW
R/W Set-Up Time
2.3
2.5
3.0
ns
tHW
R/W Hold Time
0.6
0.6
0.5
ns
tSD
Input Data Set-Up Time
2.3
2.5
3.0
ns
tHD
Input Data Hold Time
0.6
0.6
0.5
ns
tSAD
ADS Set-Up Time
2.3
2.5
3.0
ns
tHAD
ADS Hold Time
0.6
0.6
0.5
ns
tSCN
CNTEN Set-Up Time
2.3
2.5
3.0
ns
tHCN
CNTEN Hold Time
0.6
0.6
0.5
ns
tSRST
CNTRST Set-Up Time
2.3
2.5
3.0
ns
tHRST
CNTRST Hold Time
0.6
0.6
0.5
ns
tSCM
CNT/MSK Set-Up Time
2.3
2.5
3.0
ns
tHCM
CNT/MSK Hold Time
0.6
0.6
0.5
ns
Document #: 38-06059 Rev. *C
150
-100
Max.
2.0
2.0
2.0
2.0
3.0
ns
3.0
ns
Page 18 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Switching Characteristics Over the Operating Range (continued)
CY7C0851V/CY7C0852V/CY7C0853V[6]
CY7C0831V/CY7C0832V
-133
-150
Parameter
Description
Min.
Max.
tOE
Output Enable to Data Valid
tOLZ[23, 24]
OE to Low Z
0
tOHZ[23, 24]
OE to High Z
0
tCD2
Clock to Data Valid
4.0
tCA2
Clock to Counter Address Valid
tCM2
Clock to Mask Register Readback Valid
tDC
Min.
Max.
4.0
Data Output Hold After Clock HIGH
-100
Max.
Unit
5.0
ns
4.4
0
4.0
Min.
0
5.0
ns
4.4
5.0
ns
4.0
4.4
5.0
ns
4.0
4.4
5.0
ns
1.0
0
4.4
ns
1.0
0
1.0
ns
[23, 24]
Clock HIGH to Output High Z
0
4.0
0
4.4
0
5.0
ns
tCKLZ[23, 24]
Clock HIGH to Output Low Z
1.0
4.0
1.0
4.4
1.0
5.0
ns
tSINT
Clock to INT Set Time
0.5
6.7
0.5
7.5
0.5
10
ns
tRINT
Clock to INT Reset Time
0.5
6.7
0.5
7.5
0.5
10
ns
tSCINT
Clock to CNTINT Set Time
0.5
5.0
0.5
5.7
0.5
7.5
ns
tRCINT
Clock to CNTINT Reset time
0.5
5.0
0.5
5.7
0.5
7.5
ns
tCKHZ
Port to Port Delays
tCCS
Clock to Clock Skew
5.2
6.0
8.0
ns
Master Reset Timing
tRS
Master Reset Pulse Width
7.0
7.5
10
ns
tRSS
Master Reset Set-Up Time
6.0
6.0
8.5
ns
tRSR
Master Reset Recovery Time
6.0
tRSF
Master Reset to Outputs Inactive
6.0
6.5
8.0
ns
tRSCNTINT
Master Reset to Counter Interrupt Flag Reset Time
5.8
7.0
8.0
ns
7.5
10
ns
JTAG Timing and Switching Waveforms
CY7C0852V
-150/133/100
Parameter
Description
Min.
Max.
Unit
10
MHz
fJTAG
Maximum JTAG TAP Controller Frequency
tTCYC
TCK Clock Cycle Time
100
ns
tTH
TCK Clock HIGH Time
40
ns
tTL
TCK Clock LOW Time
40
ns
tTMSS
TMS Set-Up to TCK Clock Rise
10
ns
tTMSH
TMS Hold After TCK Clock Rise
10
ns
tTDIS
TDI Set-Up to TCK Clock Rise
10
ns
tTDIH
TDI Hold after TCK Clock Rise
10
ns
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
30
0
ns
ns
Notes:
23. This parameter is guaranteed by design, but it is not production tested.
24. Test conditions used are Load 2.
Document #: 38-06059 Rev. *C
Page 19 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
tTH
Test Clock
TCK
tTMSS
CY7C0831V/CY7C0832V
tTL
tTCYC
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOX
tTDOV
Switching Waveforms
Master Reset
tRS
MRST
ALL
ADDRESS/
DATA
LINES
tRSF
ALL
OTHER
INPUTS
tRSS
tRSR
INACTIVE
ACTIVE
TMS
CNTINT
INT
TDO
Document #: 38-06059 Rev. *C
Page 20 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Switching Waveforms (continued)
Read Cycle[25, 26, 27, 28, 9]
tCH2
tCYC2
tCL2
CLK
CE
tSC
tHC
tSB
tHB
tSW
tSA
tHW
tHA
tSC
tHC
B0–B3
R/W
ADDRESS
An
DATAOUT
An+1
1 Latency
An+2
tDC
tCD2
Qn
tCKLZ
An+3
Qn+1
tOHZ
Qn+2
tOLZ
OE
tOE
Notes:
25. OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge.
26. ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH.
27. The output is disabled (high-impedance state) by CE = VIH following the next rising edge of the clock.
28. Addresses do not have to be accessed sequentially since ADS = CNTEN = VIL with CNT/MSK = VIH constantly loads the address on the rising edge of the CLK.
Numbers are for reference only.
Document #: 38-06059 Rev. *C
Page 21 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Switching Waveforms (continued)
Bank Select Read[29, 30]
tCH2
tCYC2
tCL2
CLK
tHA
tSA
ADDRESS(B1)
A0
A1
A3
A2
A4
A5
tHC
tSC
CE(B1)
tCD2
tHC
tSC
tCD2
tHA
tSA
ADDRESS (B2)
A0
tDC
A1
tCKHZ
Q3
Q1
Q0
DATAOUT(B1)
tCD2
tCKHZ
tDC
tCKLZ
A3
A2
A4
A5
tHC
tSC
CE(B2)
tSC
tCD2
tHC
DATAOUT(B2)
tCKHZ
tCD2
Q4
Q2
tCKLZ
tCKLZ
Read-to-Write-to-Read (OE = LOW)[28, 31, 32, 33, 34]
tCH2
tCYC2
tCL2
CLK
CE
tSC
tHC
tSW
tHW
R/W
tSW
tHW
An
ADDRESS
tSA
An+1
An+2
An+3
An+4
tSD tHD
tHA
DATAIN
An+2
tCD2
tCKHZ
Dn+2
tCD2
Qn
DATAOUT
Qn+3
tCKLZ
READ
NO OPERATION
WRITE
READ
Notes:
29. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress CY7C085XV device from this data sheet.
ADDRESS(B1) = ADDRESS(B2).
30. ADS = CNTEN= B0 – B3 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.
31. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
32. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
33. CE0 = OE = B0 – B3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
34. CE0 = B0 – B3 = R/W = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be
completed (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.
Document #: 38-06059 Rev. *C
Page 22 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Switching Waveforms (continued)
Read-to-Write-to-Read (OE Controlled)[28, 31, 33, 34]
tCH2
tCYC2
tCL2
CLK
CE
tSC
tHC
tSW tHW
R/W
tSW
tHW
An
An+1
An+2
An+3
An+4
An+5
ADDRESS
tSA
tHA
tSD tHD
Dn+2
DATAIN
Dn+3
tCD2
DATAOUT
tCD2
Qn
Qn+4
tOHZ
OE
READ
WRITE
READ
[2, 33]
Read with Address Counter Advance
tCH2
tCYC2
tCL2
CLK
tSA
ADDRESS
tHA
An
tSAD
tHAD
ADS
tSAD
tHAD
tSCN
tHCN
CNTEN
tSCN
DATAOUT
tHCN
Qx–1
READ
EXTERNAL
ADDRESS
Document #: 38-06059 Rev. *C
tCD2
Qx
Qn
tDC
READ WITH COUNTER
Qn+1
COUNTER HOLD
Qn+2
Qn+3
READ WITH COUNTER
Page 23 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Switching Waveforms (continued)
Write with Address Counter Advance [2, 34]
tCH2
tCYC2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL
ADDRESS
An
tSAD
tHAD
tSCN
tHCN
An+1
An+2
An+3
An+4
ADS
CNTEN
Dn
DATAIN
tSD
tHD
WRITE EXTERNAL
ADDRESS
Document #: 38-06059 Rev. *C
Dn+1
Dn+1
WRITE WITH
COUNTER
Dn+2
WRITE COUNTER
HOLD
Dn+3
Dn+4
WRITE WITH COUNTER
Page 24 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Switching Waveforms (continued)
Counter Reset [2, 35, 36]
tCYC2
tCH2 tCL2
CLK
tSA
INTERNAL
ADDRESS
Ax
tSW
An
1
0
Ap
Am
An
ADDRESS
tHA
Ap
Am
tHW
R/W
ADS
CNTEN
tSRST tHRST
CNTRST
tSD tHD
DATAIN
D0
tCD2
tCD2
[48]
DATAOUT
Q0
Qn
Q1
tCKLZ
COUNTER
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS 1
READ
ADDRESS An
READ
ADDRESS Am
Notes:
35. CE0 = B0 – B3 = LOW; CE1 = MRST = CNT/MSK = HIGH.
36. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset.
Document #: 38-06059 Rev. *C
Page 25 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Switching Waveforms (continued)
Readback State of Address Counter or Mask Register[2, 37, 38, 39, 40]
tCYC2
tCH2 tCL2
CLK
tCA2 or tCM2
tSA tHA
EXTERNAL
ADDRESS
A0–A16
An*
An
INTERNAL
ADDRESS
An+1
An
An+2
An+3
An+4
tSAD tHAD
ADS
tSCN tHCN
CNTEN
tCD2
DATAOUT
Qx-1
Qn
READBACK
COUNTER
INTERNAL
ADDRESS
INCREMENT
Qx-2
LOAD
EXTERNAL
ADDRESS
tCKHZ
tCKLZ
Qn+1
Qn+2
Qn+3
Notes:
37. CE0 = OE = B0 – B3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
38. Address in output mode. Host must not be driving address bus after tCKLZ in next clock cycle.
39. Address in input mode. Host can drive address bus after tCKHZ.
40. An * is the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines.
Document #: 38-06059 Rev. *C
Page 26 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Switching Waveforms (continued)
Left_Port (L_Port) Write to Right_Port (R_Port) Read[41, 42, 43]
tCH2
tCYC2
tCL2
CLKL
tHA
tSA
L_PORT
ADDRESS
An
tSW
tHW
R/WL
tCKHZ
tSD
L_PORT
tCKLZ
Dn
DATAIN
CLKR
tHD
tCYC2
tCL2
tCCS
tCH2
tSA
R_PORT
ADDRESS
tHA
An
R/WR
tCD2
R_PORT
Qn
DATAOUT
tDC
Notes:
41. CE0 = OE = ADS = CNTEN = B0 – B3 = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH.
42. This timing is valid when one port is writing, and other port is reading the same location at the same time. If tCCS is violated, indeterminate data will be Read out.
43. If tCCS < minimum specified value, then R_Port will Read the most recent data (written by L_Port) only (2 * tCYC2 + tCD2) after the rising edge of R_Port's clock.
If tCCS > minimum specified value, then R_Port will Read the most recent data (written by L_Port) (tCYC2 + tCD2) after the rising edge of R_Port's clock.
Document #: 38-06059 Rev. *C
Page 27 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Switching Waveforms (continued)
Counter Interrupt and Retransmit[2, 44, 45, 46, 47, 48]
tCH2
tCYC2
tCL2
CLK
tSCM
tHCM
CNT/MSK
ADS
CNTEN
COUNTER
INTERNAL
ADDRESS
1FFFC
1FFFD
1FFFE
tSCINT
1FFFF
Last_Loaded
Last_Loaded +1
tRCINT
CNTINT
Notes:
44. CE0 = OE = B0 – B3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
45. CNTINT is always driven.
46. CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value.
47. The mask register assumed to have the value of 1FFFFh.
48. Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value.
Document #: 38-06059 Rev. *C
Page 28 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Switching Waveforms (continued)
MailBox Interrupt Timing[49, 50, 51, 52, 53]
tCH2
tCYC2
tCL2
CLKL
tSA
L_PORT
ADDRESS
tHA
1FFFF
An+1
An
An+2
An+3
tSINT
tRINT
INTR
tCH2
tCYC2
tCL2
CLKR
tSA
R_PORT
ADDRESS
tHA
Am+1
Am
1FFFF
Am+3
Am+4
Table 6. Read/Write and Enable Operation (Any Port)[1, 7, 54, 55, 56]
Inputs
OE
Outputs
CE0
CE1
R/W
DQ0 – DQ35
X
H
X
X
High-Z
Deselected
X
X
L
X
High-Z
Deselected
X
L
H
L
DIN
Write
L
L
H
H
DOUT
Read
L
H
X
High-Z
H
CLK
X
Operation
Outputs Disabled
Notes:
49. CE0 = OE = ADS = CNTEN = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH.
50. Address “1FFFF” is the mailbox location for R_Port.
51. L_Port is configured for Write operation, and R_Port is configured for Read operation.
52. At least one byte enable (B0 – B3) is required to be active during interrupt operations.
53. Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock.
54. OE is an asynchronous input signal.
55. When CE changes state, deselection and Read happen after one cycle of latency.
56. CE0 = OE = LOW; CE1 = R/W = HIGH.
Document #: 38-06059 Rev. *C
Page 29 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Ordering Information
256K × 36 (9M) 3.3V Synchronous CY7C0853V Dual-Port SRAM
Speed
(MHz)
Ordering Code
Package
Name
150
CY7C0853V-150BBC
BB172
172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Commercial
Package Type
Operating
Range
133
CY7C0853V-133BBC
BB172
172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Commercial
100
CY7C0853V-100BBC
BB172
172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Commercial
CY7C0853V-100BBI
BB172
172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Industrial
256K × 18 (4M) 3.3V Synchronous CY7C0832V Dual-Port SRAM
Speed
(MHz)
Ordering Code
Package
Name
Package Type
Operating
Range
150
CY7C0832V-150AC
A120
120-pin Flat Pack 14 mm × 14 mm (TQFP)
Commercial
133
CY7C0832V-133AC
A120
120-pin Flat Pack 14 mm × 14 mm (TQFP)
Commercial
100
CY7C0832V-100AC
A120
120-pin Flat Pack 14 mm × 14 mm (TQFP)
Commercial
CY7C0832V-100AI
A120
120-pin Flat Pack 14 mm × 14 mm (TQFP)
Industrial
128K × 36 (4M) 3.3V Synchronous CY7C0852V Dual-Port SRAM
150
CY7C0852V-150BBC
CY7C0852V-150AC
133
100
BB172
A176
172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Commercial
176-pin Flat Pack 24 mm × 24 mm (TQFP)
Commercial
CY7C0852V-133BBC
BB172
172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Commercial
CY7C0852V-133BBI
BB172
172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Industrial
CY7C0852V-133AC
A176
CY7C0852V-100BBC
BB172
CY7C0852V-100AC
A176
CY7C0852V-100BBI
BB172
CY7C0852V-100AI
A176
176-pin Flat Pack 24 mm × 24 mm (TQFP)
Commercial
172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Commercial
176-pin Flat Pack 24 mm × 24 mm (TQFP)
Commercial
172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Industrial
176-pin Flat Pack 24 mm × 24 mm (TQFP)
Industrial
128K × 18 (2M) 3.3V Synchronous CY7C0831V Dual-Port SRAM
Speed
(MHz)
Ordering Code
Package
Name
Package Type
Operating
Range
150
CY7C0831V-150AC
A120
120-pin Flat Pack 14 mm × 14 mm (TQFP)
Commercial
133
CY7C0831V-133AC
A120
120-pin Flat Pack 14 mm × 14 mm (TQFP)
Commercial
100
CY7C0831V-100AC
A120
120-pin Flat Pack 14 mm × 14 mm (TQFP)
Commercial
64K × 36 (2M) 3.3V Synchronous CY7C0851V Dual-Port SRAM
Speed
(MHz)
Ordering Code
Package
Name
150
CY7C0851V-150BBC
BB172
CY7C0851V-150AC
133
100
CY7C0851V-133BBC
A176
BB172
Package Type
Operating
Range
172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Commercial
176-pin Flat Pack 24 mm × 24 mm (TQFP)
Commercial
172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Commercial
CY7C0851V-133AC
A176
CY7C0851V-133BBI
BB172
172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Industrial
CY7C0851V-100BBC
BB172
172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Commercial
CY7C0851V-100AC
A176
176-pin Flat Pack 24 mm × 24 mm (TQFP)
176-pin Flat Pack 24 mm × 24 mm (TQFP)
Commercial
Commercial
Shaded areas contain advance information.
Document #: 38-06059 Rev. *C
Page 30 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Package Diagrams
120-pin thin Quad Flatpack (14 × 14 × 1.4 mm) A120
51-85100
176-lead Thin Quad Flat Pack (24 × 24 × 1.4 mm) A176
51-85132
Document #: 38-06059 Rev. *C
Page 31 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Package Diagrams (continued)
172-ball BGA BB172
51-85114-*A
FLEx36 is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-06059 Rev. *C
Page 32 of 33
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Document Title: CY7C0851V/CY7C0852V/CY7C0853V/CY7C0831V/CY7C0832V 3.3V 64K/128K/256K x 36 and
128K/256K x 18 Synchronous Dual-Port RAM
Document Number: 38-06059
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
111473
11/27/01
DSG
Change from Spec number: 38-01056 to 38-06059
*A
111942
12/21/01
JFU
Updated capacitance values
Updated switching parameters and ISB3
Updated “Read-to-Write-to-Read (OE Controlled)” waveform
Revised static discharge voltage
Revised footnote regarding ISB3
*B
113741
04/02/02
KRE
Updated Isb values
Updated ESD voltage
Corrected 0853 pins L3 and L12
*C
114704
04/24/02
KRE
Added discussion of Pause/Restart for JTAG boundary scan
Document #: 38-06059 Rev. *C
Page 33 of 33