CY7C09089V_11

CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09089V/99V CY7C09179V/99V 3.3 V 32 K/64 K/128 K × 8/9 Synchronous Dual-Port Static RAM 3.3 V 32 K/64 K/128 K × 8/9 Synchronous Dual-Port Static RAM Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High speed clock to data access 6.5[1]/7.5[1]/9/12 ns (max.) 3.3 V low operating power Active = 115 mA (typical) Standby = 10 A (typical) Fully synchronous interface for easier operation Burst counters increment addresses internally Shorten cycle times Minimize bus noise Supported in Flow-through and Pipelined modes Dual Chip Enables for easy depth expansion Automatic power down Commercial and Industrial temperature ranges Available in 100-pin TQFP Pb-free packages available True Dual-Ported memory cells which enable simultaneous access of the same memory location Flow-through and Pipelined devices 32 K × 9 organizations (CY7C09179V) 64 K × 8 organizations (CY7C09089V) 128 K × 8/9 organizations (CY7C09099V/199V) 3 Modes Flow-through Pipelined Burst Pipelined output mode on both ports enables fast 100 MHz operation 0.35-micron CMOS for optimum speed and power Note 1. See page 9 and page 10 for Load Conditions. Cypress Semiconductor Corporation Document #: 38-06043 Rev. *F • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 25, 2011 [+] Feedback CY7C09089V/99V CY7C09179V/99V Logic Block Diagram R/WL OEL R/WR OER CE0L CE1L 1 0/1 1 0/1 0 0 CE0R CE1R FT/PipeL [2] I/O0L–I/O7/8L 0/1 1 0 0 1 0/1 FT/PipeR I/O0R–I/O7/8R [2] 8/9 8/9 I/O Control 15/16/17 I/O Control 15/16/17 A0–A14/15/16L CLKL ADSL CNTENL CNTRSTL [3] Counter/ Address Register Decode True Dual-Ported RAM Array Counter/ Address Register Decode A0–A14/15/16R CLKR ADSR CNTENR CNTRSTR [3] Notes 2. I/O0–I/O7 for ×8 devices, I/O0–I/O8 for ×9 devices. 3. A0–A14 for 32K, A0–A15 for 64K, and A0–A16 for 128K devices. Document #: 38-06043 Rev. *F Page 2 of 28 [+] Feedback CY7C09089V/99V CY7C09179V/99V Functional Description The CY7C09089V/99V and CY7C09179V/99V are high speed synchronous CMOS 64 K/128 K × 8 and 32 K/128 K × 9 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory.[4] Registers on control, address, and data lines enable minimal setup and hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid tCD2 = 6.5 ns[5] (pipelined). Flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. In flow-through mode, data is available tCD1 = 18 ns after the address is clocked into the device. Pipelined output or flow-through mode is selected via the FT/Pipe pin. Each port contains a burst counter on the input address register. The internal write pulse width is independent of the LOW-to-HIGH transition of the clock signal. The internal write pulse is self-timed to enable the shortest possible cycle times. A HIGH on CE0 or LOW on CE1 for one clock cycle powers down the internal circuitry to reduce the static power consumption. The use of multiple Chip Enables enables easier banking of multiple chips for depth expansion configurations. In the pipelined mode, one cycle is required with CE0 LOW and CE1 HIGH to reactivate the outputs. Counter enable inputs are provided to stall the operation of the address input and use the internal address generated by the internal counter for fast interleaved memory applications. A port’s burst counter is loaded with the port’s Address Strobe (ADS). When the port’s Count Enable (CNTEN) is asserted, the address counter increments on each LOW-to-HIGH transition of that port’s clock signal. This reads/writes one word from/into each successive address location until CNTEN is deasserted. The counter can address the entire memory array and loops back to the start. Counter Reset (CNTRST) is used to reset the burst counter. All parts are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages. Notes 4. When writing simultaneously to the same location, the final value cannot be guaranteed. 5. See page 9 and page 10 for Load Conditions. Document #: 38-06043 Rev. *F Page 3 of 28 [+] Feedback CY7C09089V/99V CY7C09179V/99V Contents Pin Configurations ........................................................... 5 Selection Guide ................................................................ 7 Pin Definitions .................................................................. 7 Maximum Ratings ............................................................. 8 Operating Range ............................................................... 8 Electrical Characteristics ................................................. 8 Capacitance ...................................................................... 9 Switching Characteristics .............................................. 11 Switching Waveforms .................................................... 12 Read/Write and Enable Operation ................................. 23 Address Counter Control Operation ............................. 23 Ordering Information ...................................................... 24 64 K × 8 3.3 V Synchronous Dual-Port SRAM .......... 24 128 K × 8 3.3 V Synchronous Dual-Port SRAM ........ 24 32 K × 9 3.3 V Synchronous Dual-Port SRAM .......... 24 128 K × 9 3.3 V Synchronous Dual-Port SRAM ........ 24 Ordering Code Definitions ......................................... 24 Package Diagram ............................................................ 25 Acronyms ........................................................................ 26 Document Conventions ................................................. 26 Units of Measure ....................................................... 26 Document History Page ................................................. 27 Sales, Solutions, and Legal Information ...................... 28 Worldwide Sales and Design Support ....................... 28 Products .................................................................... 28 PSoC Solutions ......................................................... 28 Document #: 38-06043 Rev. *F Page 4 of 28 [+] Feedback CY7C09089V/99V CY7C09179V/99V Pin Configurations Figure 1. 100-pin TQFP (Top View) - CY7C09089V (64 K × 8), CY7C09099V (128 K × 8) CNTENR CNTENL ADSR CLKR ADSL CLKL GND A0R A1R A2R A3R A4R A5R A6R A6L A5L A4L A3L A2L A1L A0L NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC NC A7L A8L A9L A10L A11L A12L A13L A14L [6] NC 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC NC A7R A8R A9R A10R A11R A12R A13R A14R A15R A16R [6] GND NC NC NC NC CE0R CE1R CNTRSTR R/WR OER [7] FT/PIPER A15L A16L VCC NC NC NC NC CE0L CE1L CNTRSTL R/WL [7] OEL FT/PIPEL NC NC GND NC I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L I/O1L I/O0L I/O0R I/O2R I/O3R I/O4R I/O5R I/O6R I/O7R I/01R GND GND GND NC VCC VCC NC NC Notes 6. This pin is NC for CY7C09089V. 7. For CY7C09089V, pin #23 connected to VCC is pin compatible with an IDT 5 V, ×8 pipelined device; connecting pin #23 and #53 to GND is pin compatible with an IDT 5 V, ×16 flow-through device. Document #: 38-06043 Rev. *F NC Page 5 of 28 [+] Feedback CY7C09089V/99V CY7C09179V/99V Figure 2. 100-pin TQFP (Top View) - CY7C09179V (32 K × 9), CY7C09199V (128 K × 9) CNTENR CNTENL ADSR CLKR ADSL CLKL GND GND A0R A1R A2R A3R A4R A5R A6R A6L A5L A4L A3L A2L A1L A0L NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC NC A7L A8L A9L A10L A11L A12L A13L A14L [8] A15L [9] NC 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC NC A7R A8R A9R A10R A11R A12R A13R A14R A15R [8] A16R [9] GND NC NC NC NC CE0R CE1R CNTRSTR R/WR OER FT/PIPER GND NC A16L VCC NC NC NC NC CE0L CE1L CNTRSTL R/WL OEL FT/PIPEL NC NC I/O0R I/01R GND GND GND I/O2R I/O3R I/O4R I/O5R I/O6R I/O7R I/O8R VCC VCC NC I/O8L I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L I/O1L Notes 8. This pin is NC for CY7C09179V. 9. This pin is NC for CY7C09179V and CY7C09189V. Document #: 38-06043 Rev. *F I/O0L NC Page 6 of 28 [+] Feedback CY7C09089V/99V CY7C09179V/99V Selection Guide Description fMAX2 (MHz) (Pipelined) Max. Access Time (ns) (Clock to Data, Pipelined) Typical Operating Current ICC (mA) Typical Standby Current for ISB1 (mA) (Both Ports TTL Level) Typical Standby Current for ISB3 (A) (Both Ports CMOS Level) CY7C09179V -6[10] 100 6.5 175 25 10 CY7C09099V -7[10] 83 7.5 155 25 10 CY7C09199V -9 67 9 135 20 10 CY7C09089V/99V CY7C09179V -12 50 12 115 20 10 Pin Definitions Left Port A0L–A16L ADSL Right Port A0R–A16R ADSR Description Address Inputs (A0–A14 for 32K; A0–A15 for 64K; and A0–A16 for 128K devices). Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to access the part using an externally supplied address. Asserting this signal LOW also loads the burst counter with the address present on the address pins. Chip Enable Input. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0  VIL and CE1 VIH). Clock Signal. This input can be free running or strobed. Maximum clock input rate is fMAX. Counter Enable Input. Asserting this signal LOW increments the burst address counter of its respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted LOW. Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN. Data Bus Input/Output (I/O0–I/O7 for ×8 devices; I/O0–I/O8 for ×9 devices). Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read operations. Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For read operations, assert this pin HIGH. Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW. For pipelined mode operation, assert this pin HIGH. Ground Input. No Connect. Power Input. CE0L, CE1L CLKL CNTENL CE0R, CE1R CLKR CNTENR CNTRSTL I/O0L–I/O8L OEL R/WL FT/PIPEL GND NC VCC CNTRSTR I/O0R–I/O8R OER R/WR FT/PIPER Note 10. See page 9 and page 10 for Load Conditions. Document #: 38-06043 Rev. *F Page 7 of 28 [+] Feedback CY7C09089V/99V CY7C09179V/99V Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.[11] Storage Temperature .............................. –65 °C to +150 °C Ambient Temperature with Power Applied ...................................–55 °C to +125 °C Supply Voltage to Ground Potential ............ –0.5 V to +4.6 V DC Voltage Applied to Outputs in High Z State .......................–0.5 V to VCC + 0.5 V DC Input Voltage .................................–0.5 V to VCC + 0.5 V Output Current into Outputs (LOW) ............................20 mA Static Discharge Voltage .........................................> 2001 V Latch-Up Current ...................................................> 200 mA Operating Range Range Commercial Industrial [12] Ambient Temperature 0 °C to +70 °C –40 °C to +85 °C VCC 3.3 V  300 mV 3.3 V  300 mV Electrical Characteristics Over the Operating Range CY7C09079V/89V/99V CY7C09179V/89V/99V -7[13] -9 Max Max Max Min Min Min Typ Typ Parameter Description Min -6[13] Typ -12 Max Typ Unit V V V V A mA mA mA mA mA mA A A mA mA [+] Feedback VOH VOL VIH VIL IOZ ICC ISB1 ISB2 ISB3 ISB4 Output HIGH Voltage (VCC = Min., 2.4 – – 2.4 – – 2.4 – – 2.4 – – IOH = –4.0 mA) – 0.4 – 0.4 – 0.4 – 0.4 Output LOW Voltage (VCC = Min., IOH = +4.0 mA) Input HIGH Voltage 2.0 – 2.0 – 2.0 – 2.0 – Input LOW Voltage – 0.8 – 0.8 – 0.8 – 0.8 Output Leakage Current –10 10 –10 10 –10 10 –10 10 Operating Current Commercial – 175 320 – 155 275 – 135 225 – 115 205 (VCC = Max., IOUT = 0 mA) Industrial[12] – 275 390 185 295 – – Outputs Disabled Standby Current Commercial 25 95 25 85 20 65 20 50 (Both Ports TTL Level)[14] Industrial[12] – 85 120 35 75 – – CEL & CER  VIH, f = fMAX Standby Current Commercial 115 175 105 165 95 150 85 140 (One Port TTL Level)[14] – 165 210 105 160 – – Industrial[12] CEL | CER  VIH, f = fMAX Commercial 10 250 10 250 10 250 10 250 Standby Current (Both Ports CMOS Industrial[12] – 10 250 10 250 – – Level)[14] CEL & CER  VCC – 0.2 V, f=0 Standby Current Commercial 105 135 95 125 85 115 75 100 (One Port CMOS Level)[14] Industrial[12] – 125 170 95 125 – – CEL | CER  VIH, f = fMAX Notes 11. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. 12. Industrial parts are available in CY7C09099V and CY7C09199V only. 13. See page 9 and page 10 for Load Conditions. 14. CEL and CER are internal signals. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0  VIL and CE1 VIH). Document #: 38-06043 Rev. *F Page 8 of 28 CY7C09089V/99V CY7C09179V/99V Capacitance Parameter CIN COUT Description Input Capacitance Output Capacitance Figure 3. AC Test Loads 3.3 V 3.3 V R1 = 590  OUTPUT C = 30 pF R2 = 435  OUTPUT C = 30 pF VTH = 1.4 V RTH = 250  R1 = 590  OUTPUT C = 5 pF R2 = 435  Test Conditions TA = 25 °C, f = 1 MHz, VCC = 3.3 V Max 10 10 Unit pF pF (a) Normal Load (Load 1) (b) Thévenin Equivalent (Load 1) (c) Three-State Delay (Load 2) (Used for tCKLZ, tOLZ, & tOHZ including scope and jig) Figure 4. AC Test Loads (Applicable to -6 and -7 only)[15] OUTPUT C Z0 = 50  R = 50  3.0 V GND VTH = 1.4 V 10%  3 ns ALL INPUT PULSES 90% 90% 10%  3 ns (a) Load 1 (-6 and -7 only) Note 15. Test Conditions: C = 10 pF. Document #: 38-06043 Rev. *F Page 9 of 28 [+] Feedback CY7C09089V/99V CY7C09179V/99V Figure 5. Load Derating Curve 0. 60 0. 50 (ns) for all -7 access times 0. 40 0. 30 0. 20 0. 1 0 0. 00 10 15 20 25 30 35 Capacitance (pF) Document #: 38-06043 Rev. *F Page 10 of 28 [+] Feedback CY7C09089V/99V CY7C09179V/99V Switching Characteristics Over the Operating Range CY7C09079V/89V/99V CY7C09179V/89V/99V Parameter Description -6[16] Min fMAX1 fMAX2 tCYC1 tCYC2 tCH1 tCL1 tCH2 tCL2 tR tF tSA tHA tSC tHC tSW tHW tSD tHD tSAD tHAD tSCN tHCN tSRST tHRST tOE tOLZ [17, 18] -7[16] Min – – 22 12 7.5 7.5 5 5 – – 4 0 4 0 4 0 4 0 4 0 4.5 0 4 0 – 2 1 – – 2 2 2 Max 45 83 – – – – – – 3 3 – – – – – – – – – – – – – – 9 – 7 18 7.5 – 9 – Min – – 25 15 12 12 6 6 – – 4 1 4 1 4 1 4 1 4 1 5 1 4 1 – 2 1 – – 2 2 2 -9 Max 40 67 – – – – – – 3 3 – – – – – – – – – – – – – – 10 – 7 20 9 – 9 – Min – – 30 20 12 12 8 8 – – 4 1 4 1 4 1 4 1 4 1 5 1 4 1 – 2 1 – – 2 2 2 -12 Max 33 50 – – – – – – 3 3 – – – – – – – – – – – – – – 12 – 7 25 12 – 9 – Unit Max 53 100 – – – – – – 3 3 – – – – – – – – – – – – – – 8 – 7 15 6.5 – 9 – fMax Flow-through fMax Pipelined Clock Cycle Time - Flow-through Clock Cycle Time - Pipelined Clock HIGH Time - Flow-through Clock LOW Time - Flow-through Clock HIGH Time - Pipelined Clock LOW Time - Pipelined Clock Rise Time Clock Fall Time Address Set-Up Time Address Hold Time Chip Enable Set-Up Time Chip Enable Hold Time R/W Set-Up Time R/W Hold Time Input Data Set-Up Time Input Data Hold Time ADS Set-Up Time ADS Hold Time CNTEN Set-Up Time CNTEN Hold Time CNTRST Set-Up Time CNTRST Hold Time Output Enable to Data Valid OE to Low Z OE to High Z Clock to Data Valid - Flow-through Clock to Data Valid - Pipelined Data Output Hold After Clock HIGH Clock HIGH to Output High Z Clock HIGH to Output Low Z – – 19 10 6.5 6.5 4 4 – – 3.5 0 3.5 0 3.5 0 3.5 0 3.5 0 3.5 0 3.5 0 – 2 1 – – 2 2 2 MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tOHZ[17, 18] tCD1 tCD2 tDC tCKHZ[17, 18] tCKLZ[17, 18] Notes 16. See page 9 and page 10 for Load Conditions. 17. Test conditions used are Load 2. 18. This parameter is guaranteed by design, but it is not production tested. Document #: 38-06043 Rev. *F Page 11 of 28 [+] Feedback CY7C09089V/99V CY7C09179V/99V Switching Characteristics (continued) Over the Operating Range CY7C09079V/89V/99V CY7C09179V/89V/99V Parameter Description -6[16] Min Port to Port Delays tCWDD tCCS Write Port Clock HIGH to Read Data Delay Clock to Clock Set-Up Time – – 30 9 – – 35 10 – – 40 15 – – 40 15 ns ns Max -7[16] Min Max Min -9 Max Min -12 Max Unit Switching Waveforms Figure 6. Read Cycle for Flow-through Output (FT/PIPE = VIL)[19, 20, 21, 22] tCH1 CLK tCYC1 tCL1 CE0 tSC CE1 tHC tSC tHC R/W tSW tSA An tHW tHA An+1 tCD1 tDC Qn tCKLZ Qn+1 tOHZ tOLZ tDC An+2 An+3 tCKHZ Qn+2 ADDRESS DATAOUT OE tOE Notes 19. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 20. ADS = VIL, CNTEN and CNTRST = VIH. 21. The output is disabled (high-impedance state) by CE0 = VIH or CE1 = VIL following the next rising edge of the clock. 22. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only. Document #: 38-06043 Rev. *F Page 12 of 28 [+] Feedback CY7C09089V/99V CY7C09179V/99V Switching Waveforms (continued) Figure 7. Read Cycle for Pipelined Operation (FT/PIPE = VIH)[23, 24, 25, 26] tCH2 CLK tCYC2 tCL2 CE0 tSC CE1 tHC tSC tHC R/W tSW tSA ADDRESS DATAOUT An 1 Latency tHW tHA An+1 tCD2 Qn tCKLZ OE tOE An+2 tDC Qn+1 tOHZ An+3 Qn+2 tOLZ Notes 23. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 24. ADS = VIL, CNTEN and CNTRST = VIH. 25. The output is disabled (high-impedance state) by CE0 = VIH or CE1 = VIL following the next rising edge of the clock. 26. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only. Document #: 38-06043 Rev. *F Page 13 of 28 [+] Feedback CY7C09089V/99V CY7C09179V/99V Switching Waveforms (continued) Figure 8. Bank Select Pipelined Read[27, 28] - tCH2 CLKL tSA ADDRESS(B1) tSC CE0(B1) A0 tCYC2 tCL2 tHA A1 tHC A2 A3 A4 A5 tCD2 DATAOUT(B1) tSA ADDRESS(B2) A0 tHA A1 tSC CE0(B2) tSC DATAOUT(B2) tHC tSC D0 tHC tCD2 D1 tCKHZ tCD2 D3 tCKHZ tDC A2 tHC tDC A3 A4 tCKLZ A5 tCD2 D2 tCKLZ tCKHZ tCD2 D4 tCKLZ Notes 27. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this datasheet. ADDRESS(B1) = ADDRESS(B2). 28. OE and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH. Document #: 38-06043 Rev. *F Page 14 of 28 [+] Feedback CY7C09089V/99V CY7C09179V/99V Switching Waveforms (continued) Figure 9. Left Port Write to Flow-through Right Port Read[29, 30, 31, 32] CLKL R/WL tSW tHW tSA ADDRESSL tSD DATAINL CLKR R/WR ADDRESSR tSW tSA VALID tCCS MATCH tHA NO MATCH tHD tCD1 tHW tHA NO MATCH tCWDD tCD1 VALID tDC tDC VALID MATCH DATAOUTR Notes 29. The same waveforms apply for a right port write to flow-through left port read. 30. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 31. OE = VIL for the right port, which is being read from. OE = VIH for the left port, which is being written to. 32. It tCCS  maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS > maximum specified, then data is not valid until tCCS + tCD1. tCWDD does not apply in this case. Document #: 38-06043 Rev. *F Page 15 of 28 [+] Feedback CY7C09089V/99V CY7C09179V/99V Switching Waveforms (continued) Figure 10. Pipelined Read-to-Write-to-Read (OE = VIL)[33, 34, 35, 36] tCH2 CLK tCYC2 tCL2 CE0 tSC CE1 tSW R/W tSW ADDRESS tSA DATAIN An tHA tCD2 Qn READ NO OPERATION WRITE READ tCKHZ tHW An+1 An+2 An+2 tSD tHD Dn+2 tCKLZ tCD2 Qn+3 An+3 An+4 tHW tHC DATAOUT Notes 33. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only. 34. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals. 35. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 36. During “No Operation”, data in memory at the selected address may be corrupted and should be re-written to ensure data integrity. Document #: 38-06043 Rev. *F Page 16 of 28 [+] Feedback CY7C09089V/99V CY7C09179V/99V Switching Waveforms (continued) Figure 11. Pipelined Read-to-Write-to-Read (OE Controlled)[37, 38, 39, 40] tCH2 CLK tCYC2 tCL2 CE0 tSC tHC CE1 tSW tHW R/W tSW An tSA tHW An+1 tHA tCD2 An+2 tSD tHD Dn+2 Dn+3 tCKLZ Qn tOHZ tCD2 Qn+4 An+3 An+4 An+5 ADDRESS DATAIN DATAOUT OE READ WRITE READ Notes 37. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only. 38. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals. 39. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 40. During “No Operation”, data in memory at the selected address may be corrupted and should be re-written to ensure data integrity. Document #: 38-06043 Rev. *F Page 17 of 28 [+] Feedback CY7C09089V/99V CY7C09179V/99V Switching Waveforms (continued) Figure 12. Flow-through Read-to-Write-to-Read (OE = VIL)[41, 42, 43, 44, 45] tCH1 CLK tCYC1 tCL1 CE0 tSC CE1 tSW R/W tSW ADDRESS tSA DATAIN DATAOUT tCD1 Qn tDC READ An tHA tCD1 Qn+1 tCKHZ NO OPERATION tCKLZ WRITE tHW An+1 An+2 tSD Dn+2 tCD1 Qn+3 tDC READ tCD1 An+2 tHD An+3 An+4 tHW tHC Notes 41. ADS = VIL, CNTEN and CNTRST = VIH. 42. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only. 43. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals. 44. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 45. During “No Operation”, data in memory at the selected address may be corrupted and should be re-written to ensure data integrity. Document #: 38-06043 Rev. *F Page 18 of 28 [+] Feedback CY7C09089V/99V CY7C09179V/99V Switching Waveforms (continued) Figure 13. Flow-through Read-to-Write-to-Read (OE Controlled)[46, 47, 48, 49, 50] tCH1 CLK tCYC1 tCL1 CE0 tSC CE1 tSW R/W tSW ADDRESS tSA DATAIN DATAOUT OE READ WRITE READ tCD1 Qn tOHZ tCKLZ An tHA tDC tHW An+1 tSD Dn+2 An+2 tHD Dn+3 tOE tCD1 Qn+4 tDC tCD1 An+3 An+4 An+5 tHW tHC Notes 46. ADS = VIL, CNTEN and CNTRST = VIH. 47. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this datasheet. ADDRESS(B1) = ADDRESS(B2). 48. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals. 49. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 50. During “No Operation”, data in memory at the selected address may be corrupted and should be re-written to ensure data integrity. Document #: 38-06043 Rev. *F Page 19 of 28 [+] Feedback CY7C09089V/99V CY7C09179V/99V Switching Waveforms (continued) Figure 14. Pipelined Read with Address Counter Advance[51] tCH2 CLK tSA ADDRESS tSAD ADS tSAD CNTEN tSCN DATAOUT Qx-1 READ EXTERNAL ADDRESS tHCN Qx tDC tCD2 Qn READ WITH COUNTER tSCN Qn+1 COUNTER HOLD tHCN Qn+2 Qn+3 tHAD An tHAD tHA tCYC2 tCL2 READ WITH COUNTER Figure 15. Flow-through Read with Address Counter Advance[51] tCH1 CLK tSA ADDRESS tSAD ADS tSAD CNTEN tSCN DATAOUT tHCN tCD1 Qx tDC READ EXTERNAL ADDRESS Qn Qn+1 tSCN tHCN tHAD An tHAD tHA tCYC1 tCL1 Qn+2 READ WITH COUNTER Qn+3 READ WITH COUNTER COUNTER HOLD Note 51. CE0 and OE = VIL; CE1, R/W and CNTRST = VIH. Document #: 38-06043 Rev. *F Page 20 of 28 [+] Feedback CY7C09089V/99V CY7C09179V/99V Switching Waveforms (continued) Figure 16. Write with Address Counter Advance (Flow-through or Pipelined Outputs)[52, 53] tCH2 CLK tSA ADDRESS An tHA tCYC2 tCL2 INTERNAL ADDRESS tSAD ADS tHAD An An+1 An+2 An+3 An+4 CNTEN tSCN DATAIN tSD Dn tHD WRITE EXTERNAL ADDRESS tHCN Dn+1 WRITE WITH COUNTER Dn+1 Dn+2 Dn+3 Dn+4 WRITE COUNTER HOLD WRITE WITH COUNTER Notes 52. CE0 and R/W = VIL; CE1 and CNTRST = VIH. 53. The “Internal Address” is equal to the “External Address” when ADS = VIL and equals the counter output when ADS = VIH. Document #: 38-06043 Rev. *F Page 21 of 28 [+] Feedback CY7C09089V/99V CY7C09179V/99V Switching Waveforms (continued) Figure 17. Counter Reset (Pipelined Outputs)[54, 55, 56, 57] tCH2 CLK tSA ADDRESS INTERNAL ADDRESS R/W tSAD ADS tSCN CNTEN tSRST CNTRST DATAIN DATAOUT COUNTER RESET WRITE ADDRESS 0 READ ADDRESS 0 tHRST tSD D0 Q0 READ ADDRESS 1 Q1 READ ADDRESS n Qn tHD tHCN tHAD AX tSW tHW 0 1 An An tHA An+1 An+1 tCYC2 tCL2 Notes 54. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only. 55. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals. 56. CE0 = VIL; CE1 = VIH. 57. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. Document #: 38-06043 Rev. *F Page 22 of 28 [+] Feedback CY7C09089V/99V CY7C09179V/99V Read/Write and Enable Operation [58, 59, 60] Inputs OE X X X L H X CLK CE0 H X L L L CE1 X L H H H R/W X X L H X High Z High Z DIN DOUT High Z Outputs I/O0–I/O9 Operation Deselected[61] Deselected[61] Write Read[61] Outputs Disabled Address Counter Control Operation [58, 62, 63, 64] Address X An X X Previous Address X X An An CLK ADS X L H H CNTEN X X H L CNTRST L H H H I/O Dout(0) Dout(n) Dout(n) Dout(n+1) Mode Reset Load Hold Increment Operation Counter Reset to Address 0 Address Load into Counter External Address Blocked—Counter Disabled Counter Enabled—Internal Address Generation Notes 58. “X” = “Don’t Care”, “H” = VIH, “L” = VIL. 59. ADS, CNTEN, CNTRST = “Don’t Care.” 60. OE is an asynchronous input signal. 61. When CE changes state in the pipelined mode, deselection and read happen in the following clock cycle. 62. CE0 and OE = VIL; CE1 and R/W = VIH. 63. Data shown for flow-through mode; pipelined mode output will be delayed by one cycle. 64. Counter operation is independent of CE0 and CE1. Document #: 38-06043 Rev. *F Page 23 of 28 [+] Feedback CY7C09089V/99V CY7C09179V/99V Ordering Information The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. 64 K × 8 3.3 V Synchronous Dual-Port SRAM Speed (ns) 12 Ordering Code CY7C09089V-12AXI Package Name A100 Package Type 100-pin Thin Quad Flat Pack (Pb-free) Operating Range Industrial 128 K × 8 3.3 V Synchronous Dual-Port SRAM Speed (ns) 7.5 [65] Ordering Code CY7C09099V-7AXI CY7C09099V-12AXC Package Name A100 A100 Package Type 100-pin Thin Quad Flat Pack (Pb-free) 100-pin Thin Quad Flat Pack (Pb-free) Operating Range Industrial Commercial 12 32 K × 9 3.3 V Synchronous Dual-Port SRAM Speed (ns) 6.5 [65] Ordering Code CY7C09179V-6AXC CY7C09179V-12AXC Package Name A100 A100 Package Type 100-pin Thin Quad Flat Pack (Pb-free) 100-pin Thin Quad Flat Pack (Pb-free) Operating Range Commercial Commercial 12 128 K × 9 3.3 V Synchronous Dual-Port SRAM Speed (ns) 9 Ordering Code CY7C09199V-9AXC Package Name A100 Package Type 100-pin Thin Quad Flat Pack (Pb-free) Operating Range Commercial Ordering Code Definitions CY 7C 09 X X9 V - XX AX X Temperature Range: X = C or I C = Commercial; I = Industrial X = Pb-free (RoHS Compliant) Package Type: A = 100-pin TQFP Speed Grade: 12 ns or 7.5 ns or 6.5 ns or 9 ns V = 3.3 V X9 = Depth: X = 7 or 8 or 9 7 = 32K; 8 = 64K; 9 = 128K X = Width: X = 0 or 1 0 = × 8; 1 = × 9 09 = Sync 7C = Dual Port SRAM Company ID: CY = Cypress Device Note 65. See page 9 and page 10 for Load Conditions. Document #: 38-06043 Rev. *F Page 24 of 28 [+] Feedback CY7C09089V/99V CY7C09179V/99V Package Diagram Figure 18. 100-pin TQFP 14 × 14 × 1.4 mm A100SA (51-85048) 51-85048 *E Document #: 38-06043 Rev. *F Page 25 of 28 [+] Feedback CY7C09089V/99V CY7C09179V/99V Acronyms Acronym CMOS I/O OE SRAM TQFP TTL WE input/output output enable static random access memory thin quad flat pack transistor transistor logic write enable Description complementary metal oxide semiconductor Document Conventions Units of Measure Symbol °C MHz µA mA mm ms mV ns  % pF V W degree Celcius Mega Hertz micro Amperes milli Amperes milli meter milli seconds milli Volts nano seconds Ohms percent pico Farad Volts Watts Unit of Measure Document #: 38-06043 Rev. *F Page 26 of 28 [+] Feedback CY7C09089V/99V CY7C09179V/99V Document History Page Document Title: CY7C09089V/99V, CY7C09179V/99V, 3.3 V 32 K/64 K/128 K × 8/9 Synchronous Dual-Port Static RAM Document Number: 38-06043 Rev. ** *A *B ECN No. 110191 122293 365034 Orig. of Change SZV RBI PCN Orig. of Change 09/29/01 12/27/02 Description of Change Change from Spec number: 38-00667 to 38-06043 Power up requirements added to Operating Conditions Information See ECN Added Pb-Free Logo Added Pb-Free Part Ordering Information: CY7C09089V-6AXC, CY7C09089V-12AXC, CY7C09099V-6AXC, CY7C09099V-7AI, CY7C09099V-7AXI, CY7C09099V-12AXC, CY7C09179V-6AXC, CY7C09179V-12AXC, CY7C09189V-6AXC, CY7C09189V-12AXC, CY7C09199V-6AXC, CY7C09199V-7AXC, CY7C09199V-9AXC, CY7C09199V-9AXI, CY7C09199V-12AXC 12/17/08 03/22/10 Added CY7C09089V-12AXI part in the Ordering information table Removed inactive parts from ordering information table. Updated package diagram. Added Note in ordering information section. *C *D *E *F 2623658 2897159 3110406 3264673 VKN/PYRS RAME ADMU ADMU 12/14/2010 Updated Ordering Information. Added Ordering Code Definitions. 05/24/2011 Updated Document Title to read “CY7C09089V/99V, CY7C09179V/99V, 3.3 V 32 K/64 K/128 K × 8/9 Synchronous Dual-Port Static RAM”. Updated Features. Updated Pin Configurations (Removed the Note “This pin is NC for CY7C09079V.” in page 5). Updated Selection Guide. Updated Package Diagram. Added Acronyms and Units of Measure. Updated in new template. Document #: 38-06043 Rev. *F Page 27 of 28 [+] Feedback CY7C09089V/99V CY7C09179V/99V Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2001-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-06043 Rev. *F Revised May 25, 2011 Page 28 of 28 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback