CY7C09269A-6AC

25/0251 CY7C09269A CY7C09369A 16K x16/18 Synchronous Dual Port Static RAM Features • True dual-ported memory cells which allow simultaneous access of the same memory location • Two Flow-Through/Pipelined devices — 16K x 16/18 organization (CY7C09269A/369A) • Three Modes — Flow-Through — Pipelined — Burst • Pipelined output mode on both ports allows fast 100MHz cycle time • 0.35-micron CMOS for optimum speed/power • High-speed clock to data access 6.5[1]/7.5/9/12 ns (max.) • • • • • • • Low operating power — Active = 195 mA (typical) — Standby = 0.05 mA (typical) • Fully synchronous interface for easier operation • Burst counters increment addresses internally — Shorten cycle times — Minimize bus noise — Supported in Flow-Through and Pipelined modes Dual Chip Enables for easy depth expansion Upper and Lower Byte Controls for Bus Matching Automatic power-down Commercial temperature range Available in 100-pin TQFP Pin-compatible and functionally equivalent to IDT709269 Logic Block Diagram R/WL UBL R/WR UBR CE0L CE1L LBL OEL 1 0/1 1 0/1 0 0 CE0R CE1R LBR OER FT/PipeL [2] 0/1 1b 0b 1a 0a b a 0a 1a 0b 1b a b 0/1 FT/PipeR 8/9 [2] 8/9 I/O8/9L–I/O15/17L [3] I/O8/9R–I/O15/17R 8/9 14 I/O Control I/O Control 8/9 14 I/O0L–I/O7/8L A0L–A13L CLKL ADSL CNTENL CNTRSTL Counter/ Address Register Decode Counter/ Address Register Decode I/O0R–I/O7/8R A0R–A13R CLKR ADSR CNTENR CNTRSTR [3] True Dual-Ported RAM Array Notes: 1. See page 6 for Load Conditions. 2. I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices. 3. I/O0–I/O7 for x16 devices. I/O0–I/O8 for x18 devices. For the most recent information, visit the Cypress web site at www.cypress.com Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Document #: 38-06050 Rev. *A Revised December 27, 2002 CY7C09269A CY7C09369A Functional Description The CY7C09269A and CY7C09369A are high-speed synchronous CMOS 16K, 32K, and 64K x 16/18 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory.[4] Registers on control, address, and data lines allow for minimal setup and hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid tCD2 = 6.5 ns[1] (pipelined). Flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. In flow-through mode data will be available tCD1 = 15 ns after the address is clocked into the device. Pipelined output or flowthrough mode is selected via the FT/PIPE pin. Each port contains a burst counter on the input address register. The internal write pulse width is independent of the LOWto-HIGH transition of the clock signal. The internal write pulse is self-timed to allow the shortest possible cycle times. A HIGH on CE0 or LOW on CE1 for one clock cycle will power down the internal circuitry to reduce the static power consumption. The use of multiple Chip Enables allows easier banking of multiple chips for depth expansion configurations. In the pipelined mode, one cycle is required with CE0 LOW and CE1 HIGH to reactivate the outputs. Counter enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. A port’s burst counter is loaded with the port’s Address Strobe (ADS). When the port’s Count Enable (CNTEN) is asserted, the address counter will increment on each LOW-to-HIGH transition of that port’s clock signal. This will read/write one word from/into each successive address location until CNTEN is deasserted. The counter can address the entire memory array and will loop back to the start. Counter Reset (CNTRST) is used to reset the burst counter. All parts are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages. Pin Configurations 100-Pin TQFP (Top View) CNTENR CNTENL ADSR CLKR ADSL CLKL GND A0R A1R A2R A3R A4R A5R A6R A7R A8R 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A8L A7L A6L A5L A4L A3L A2L A1L A0L 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A9L A10L A11L A12L A13L NC NC NC NC LBL UBL CE0L CE1L CNTRSTL VCC R/WL OEL [5] FT/PIPEL GND I/O15L I/O14L I/O13L I/O12L I/O11L I/O10L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 A9R A10R A11R A12R A13R NC NC NC NC LBR UBR CE0R CE1R CNTRSTR GND R/WR OER FT/PIPER [5] GND I/O15R I/O14R I/O13R I/O12R I/O11R I/O10R CY7C09269A (16K x 16) I/O0R I/01R I/O2R I/O3R I/O4R I/O5R I/O6R I/O7R I/O8R I/O9R VCC GND GND VCC I/O9L I/O8L I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L I/O1L Notes: 4. When writing simultaneously to the same location, the final value cannot be guaranteed. 5. For CY7C09269A pin #18 connected to VCC is equivalent to an IDT x16 pipelined device; connecting pin #18 and #58 to GND is equivalent to an IDT x16 flowthrough device. Document #: 38-06050 Rev. *A I/O0L NC Page 2 of 17 CY7C09269A CY7C09369A Pin Configurations (continued) 100-Pin TQFP (Top View) CNTENR CNTENL ADSR CLKR ADSL CLKL GND GND A0R A1R A2R A3R A4R A5R A6R 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A9L A10L A11L A12L A13L NC NC LBL UBL CE0L CE1L CNTRSTL R/WL OEL VCC FT/PIPEL I/O17L I/O16L GND I/O15L I/O14L I/O13L 1/012L I/O11L I/O10L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 A8R A9R A10R A11R A12R A13R NC NC LBR UBR CE0R CE1R CNTRSTR R/WR GND OER FT/PIPER I/O17R GND I/O16R I/O15R I/O14R I/O13R I/O12R I/O11R A7R 63 62 61 60 59 58 57 56 55 54 53 52 51 I/10R A8L A7L A6L A5L A4L A3L A2L A1L CY7C09369A (16K x 18) A0L I/O0R I/01R VCC GND GND I/O2R I/O3R I/O4R I/O5R I/O6R VCC I/O7R I/O8R Selection Guide CY7C09269A CY7C09369A -6[1] fMAX2 (MHz) (Pipelined) Max Access Time (ns) (Clock to Data, Pipelined) Typical Operating Current ICC (mA) Typical Standby Current for ISB1 (mA) (Both Ports TTL Level) Typical Standby Current for ISB3 (mA) (Both Ports CMOS Level) 100 6.5 250 45 0.05 CY7C09269A CY7C09369A -7 83 7.5 235 40 0.05 CY7C09269A CY7C09369A -9 67 9 215 35 0.05 CY7C09269A CY7C09369A -12 50 12 195 30 0.05 Document #: 38-06050 Rev. *A I/O9R I/O9L I/O8L I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L I/O1L I/O0L Page 3 of 17 CY7C09269A CY7C09369A Pin Definitions Left Port A0L–A13L ADSL Right Port A0R–A13R ADSR Address Inputs. Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to access the part using an externally supplied address. Asserting this signal LOW also loads the burst counter with the address present on the address pins. Chip Enable Input. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 ≤ VIL and CE1 ≥ VIH). Clock Signal. This input can be free running or strobed. Maximum clock input rate is fMAX. Counter Enable Input. Asserting this signal LOW increments the burst address counter of its respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted LOW. Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN. Data Bus Input/Output (I/O0–I/O15 for x16 devices). Lower Byte Select Input. Asserting this signal LOW enables read and write operations to the lower byte. (I/O0–I/O8 for x18, I/O0–I/O7 for x16) of the memory array. For read operations both the LB and OE signals must be asserted to drive output data on the lower byte of the data pins. Upper Byte Select Input. Same function as LB, but to the upper byte (I/O8/9L–I/O15/17L). Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read operations. Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For read operations, assert this pin HIGH. Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW. For pipelined mode operation, assert this pin HIGH. Ground Input. No Connect. Power Input. DC Input Voltage ............................................ –0.5V to +7.0V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage............................................ >1100V Latch-Up Current..................................................... >200 mA Description CE0L,CE1L CLKL CNTENL CE0R,CE1R CLKR CNTENR CNTRSTL I/O0L–I/O17L LBL CNTRSTR I/O0R–I/O17R LBR UBL OEL R/WL FT/PIPEL GND NC VCC UBR OER R/WR FT/PIPER Maximum Ratings[6] (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied .. –55°C to +125°C Supply Voltage to Ground Potential ............... –0.3V to +7.0V DC Voltage Applied to Outputs in High Z State.................................. –0.5V to +7.0V Operating Range Range Commercial Ambient Temperature 0°C to +70°C VCC 5V ± 10% Note: 6. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Document #: 38-06050 Rev. *A Page 4 of 17 CY7C09269A CY7C09369A Electrical Characteristics Over the Operating Range CY7C09269A CY7C09369A -6[1] Parameter VOH VOL VIH VIL IOZ ICC Description Output HIGH Voltage (VCC = Min., IOH = –4.0 mA) Output LOW Voltage (VCC = Min., IOH = +4.0 mA) Input HIGH Voltage Input LOW Voltage Output Leakage Current Operating Current (VCC = Max., IOUT = 0 mA) Outputs Disabled Com’l. –10 250 2.2 0.8 10 450 –10 235 2.4 0.4 2.2 0.8 10 420 –10 215 2.4 0.4 2.2 0.8 10 360 –10 195 -7 2.4 0.4 2.2 0.8 10 300 -9 2.4 0.4 -12 V V V V µA mA Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit ISB1 Standby Current (Both Com’l. Ports TTL Level)[7] CEL & CER ≥ VIH, f = fMAX Standby Current (One Com’l. Port TTL Level)[7] CEL | CER ≥ VIH, f = fMAX Standby Current (Both Com’l. Ports CMOS Level)[7] CEL & CER ≥ VCC – 0.2V, f = 0 Standby Current (One Com’l. Port CMOS Level)[7] CEL | CER ≥ VIH, f = fMAX 45 115 40 105 35 95 30 85 mA ISB2 175 235 160 220 145 205 125 190 mA ISB3 0.05 0.5 0.05 0.5 0.05 0.5 0.05 0.5 mA ISB4 160 200 145 185 130 170 110 150 mA Capacitance Parameter CIN Description Input Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 10 Unit pF COUT Output Capacitance 10 pF Note: 7. CEL and CER are internal signals. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 ≤ VIL and CE1 ≥ VIH). Document #: 38-06050 Rev. *A Page 5 of 17 CY7C09269A CY7C09369A AC Test Loads 5V 5V R1 = 893Ω OUTPUT C = 30 pF R2 = 347Ω OUTPUT C = 30 pF VTH = 1.4V RTH = 250Ω R1 = 893Ω OUTPUT C = 5 pF R2 = 347Ω (b) Thévenin Equivalent (Load 1) (a) Normal Load (Load 1) (c) Three-State Delay (Load 2) (Used for tCKLZ, tOLZ, & tOHZ including scope and jig) AC Test Loads (Applicable to -6 only)[8] Z0 = 50Ω OUTPUT C R = 50Ω 3.0V GND VTH = 1.4V 10% ≤ 3 ns ALL INPUT PULSES 90% 90% 10% ≤ 3 ns (a) Load 1 (-6 only) 0. 60 0. 50 ∆ (ns) for all -12 access times 0. 40 0. 30 0. 20 0. 1 0 0. 00 10 15 20 25 30 35 Capacitance (pF) (b) Load Derating Curve Note: 8. Test Conditions: C = 10 pF. Document #: 38-06050 Rev. *A Page 6 of 17 CY7C09269A CY7C09369A Switching Characteristics Over the Operating Range CY7C09269A CY7C09369A -6[1] Parameter fMAX1 fMAX2 tCYC1 tCYC2 tCH1 tCL1 tCH2 tCL2 tR tF tSA tHA tSC tHC tSW tHW tSD tHD tSAD tHAD tSCN tHCN tSRST tHRST tOE tOLZ [9, 10] -7 Min. Max. 45 83 22 12 7.5 7.5 5 5 3 3 3 3 4 0 4 0 4 0 4 0 4 0 4 0 4 0 8 9 2 7 15 6.5 1 7 18 7.5 2 9 2 2 30 9 35 10 9 2 2 2 2 1 4 1 4 1 4 1 4 1 4 1 4 1 4 1 25 15 12 12 6 6 Min. 53 -9 Max. 40 67 30 20 12 12 8 8 3 3 4 1 4 1 4 1 4 1 4 1 4 1 4 1 10 2 7 20 9 2 9 2 2 40 15 1 -12 Min. Max. 33 50 Unit MHz MHz ns ns ns ns ns ns 3 3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 12 7 25 12 9 ns ns ns ns ns ns ns ns 40 15 ns ns Description fMax Flow-Through fMax Pipelined Clock Cycle Time - Flow-Through Clock Cycle Time - Pipelined Clock HIGH Time - Flow-Through Clock LOW Time - Flow-Through Clock HIGH Time - Pipelined Clock LOW Time - Pipelined Clock Rise Time Clock Fall Time Address Set-Up Time Address Hold Time Chip Enable Set-Up Time Chip Enable Hold Time R/W Set-Up Time R/W Hold Time Input Data Set-Up Time Input Data Hold Time ADS Set-Up Time ADS Hold Time CNTEN Set-Up Time CNTEN Hold Time CNTRST Set-Up Time CNTRST Hold Time Output Enable to Data Valid OE to Low Z OE to High Z Clock to Data Valid - Flow-Through Clock to Data Valid - Pipelined Data Output Hold After Clock HIGH Min. Max. 100 19 10 6.5 6.5 4 4 3.5 0 3.5 0 3.5 0 3.5 0 3.5 0 3.5 0 3.5 0 2 1 tOZ[9, 10] tCD1 tCD2 tDC tCKHZ tCKLZ [9, 10] [9, 10] 2 2 2 Clock HIGH to Output High Z Clock HIGH to Output Low Z Write Port Clock HIGH to Read Data Delay Clock to Clock Set-Up Time Port to Port Delays tCWDD tCCS Notes: 9. Test conditions used are Load 2. 10. This parameter is guaranteed by design, but it is not production tested. Document #: 38-06050 Rev. *A Page 7 of 17 CY7C09269A CY7C09369A Switching Waveforms Read Cycle for Flow-Through Output (FT/PIPE = VIL)[11, 12, 13, 14] tCH1 CLK tCYC1 tCL1 CE0 tSC CE1 tHC tSC tHC R/W tSW tSA ADDRESS DATAOUT tCKLZ tOHZ OE tOE tOLZ An tCD1 tHW tHA An+1 tDC Qn Qn+1 An+2 An+3 tCKHZ Qn+2 tDC Read Cycle for Pipelined Operation (FT/PIPE = VIH)[11, 12, 13, 14] tCH2 CLK tCYC2 tCL2 CE0 tSC CE1 tHC tSC tHC R/W tSW tSA ADDRESS DATAOUT An 1 Latency tHW tHA An+1 tCD2 Qn tCKLZ OE tOE Notes: 11. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 12. ADS = VIL, CNTEN and CNTRST = VIH. 13. The output is disabled (high-impedance state) by CE0=VIH or CE1 = VIL following the next rising edge of the clock. 14. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only. An+2 tDC Qn+1 tOHZ An+3 Qn+2 tOLZ Document #: 38-06050 Rev. *A Page 8 of 17 CY7C09269A CY7C09369A Switching Waveforms (continued) Bank Select Pipelined Read[15, 16] tCH2 CLKL tSA ADDRESS(B1) tSC CE0(B1) tCD2 DATAOUT(B1) tSA ADDRESS(B2) A0 tHA A1 tSC CE0(B2) tSC DATAOUT(B2) tCKLZ tHC tCD2 D2 tCKLZ tCKHZ tCD2 D4 tSC D0 tDC A2 tHC tHC tCD2 D1 tDC A3 A4 tCKLZ A5 tCKHZ tCD2 D3 tCKHZ A0 tHC tHA A1 A2 A3 A4 A5 tCYC2 tCL2 Left Port Write to Flow-Through Right Port Read[17, 18, 19, 20] CLKL tSW R/WL tSA ADDRESSL tSD DATAINL CLKR R/WR ADDRESSR tSW tSA tHW tHA NO MATCH tCWDD DATAOUTR tDC VALID tDC tCD1 VALID VALID tCCS tCD1 MATCH tHD tHA NO MATCH tHW MATCH Notes: 15. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; each Bank consists of one Cypress dual-port device from this data sheet. ADDRESS(B1) = ADDRESS(B2). 16. UB, LB, OE and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH. 17. The same waveforms apply for a right port write to flow-through left port read. 18. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 19. OE = VIL for the right port, which is being read from. OE = VIH for the left port, which is being written to. 20. It tCCS ≤ maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS>maximum specified, then data is not valid until tCCS + tCD1. tCWDD does not apply in this case. Document #: 38-06050 Rev. *A Page 9 of 17 CY7C09269A CY7C09369A Switching Waveforms (continued) Pipelined Read-to-Write-to-Read (OE = VIL)[14, 21, 22, 23] tCH2 CLK tCYC2 tCL2 CE0 tSC CE1 tSW R/W tSW ADDRESS tSA DATAIN An tHA tCD2 Qn READ NO OPERATION [14, 21, 22, 23] tHC tHW tHW An+1 An+2 An+2 tSD tHD tCKHZ Dn+2 tCKLZ tCD2 Qn+3 WRITE READ An+3 An+4 DATAOUT Pipelined Read-to-Write-to-Read (OE Controlled) tCH2 CLK tCYC2 tCL2 CE0 tSC tHC CE1 tSW tHW R/W tSW An tHW An+1 tHA An+2 tSD tHD Dn+2 tCD2 Dn+3 tCKLZ Qn tOHZ tCD2 Qn+4 An+3 An+4 An+5 ADDRESS tSA DATAIN DATAOUT OE READ WRITE READ Notes: 21. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals. 22. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 23. During “No operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. Document #: 38-06050 Rev. *A Page 10 of 17 CY7C09269A CY7C09369A Switching Waveforms (continued) Flow-Through Read-to-Write-to-Read (OE = VIL)[12, 14, 21, 22] tCH1 CLK tCYC1 tCL1 CE0 tSC CE1 tSW R/W tSW ADDRESS tSA DATAIN tCD1 Qn tDC READ An tHA tCD1 Qn+1 tCKHZ NO OPERATION tCKLZ WRITE tHW An+1 An+2 tSD Dn+2 tCD1 Qn+3 tDC READ tCD1 An+2 tHD An+3 An+4 tHW tHC DATAOUT Flow-Through Read-to-Write-to-Read (OE Controlled)[12, 14, 21, 22] tCH1 CLK tCYC1 tCL1 CE0 tSC CE1 tSW R/W tSW An ADDRESS tSA DATAIN tCD1 Qn tOHZ tCKLZ tHA tDC tSD Dn+2 tHD Dn+3 tOE tCD1 Qn+4 tDC tCD1 tHW An+1 An+2 An+3 An+4 An+5 tHW tHC DATAOUT OE READ WRITE READ Document #: 38-06050 Rev. *A Page 11 of 17 CY7C09269A CY7C09369A Switching Waveforms (continued) Pipelined Read with Address Counter Advance[24] tCYC2 tCL2 tCH2 CLK tSA ADDRESS tSAD ADS An tHA tHAD tSAD CNTEN tSCN DATAOUT Qx-1 READ EXTERNAL ADDRESS tHCN Qx tDC READ WITH COUNTER tCD2 Qn tSCN Qn+1 tHAD tHCN Qn+2 Qn+3 COUNTER HOLD READ WITH COUNTER Flow-Through Read with Address Counter Advance[24] tCYC1 tCL1 tCH1 CLK tSA ADDRESS tSAD ADS An tHA tHAD tSAD tHAD CNTEN tSCN tHCN tCD1 Qx tDC Qn Qn+1 Qn+2 tSCN tHCN DATAOUT Qn+3 READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD READ WITH COUNTER Note: 24. CE0 and OE = VIL; CE1, R/W and CNTRST = VIH. Document #: 38-06050 Rev. *A Page 12 of 17 CY7C09269A CY7C09369A Switching Waveforms (continued) Write with Address Counter Advance (Flow-Through or Pipelined Outputs)[25, 26] tCH2 CLK tSA ADDRESS An tHA tCYC2 tCL2 INTERNAL ADDRESS tSAD ADS tHAD An An+1 An+2 An+3 An+4 CNTEN tSCN DATAIN tSD Dn tHD WRITE EXTERNAL ADDRESS tHCN Dn+1 WRITE WITH COUNTER Dn+1 Dn+2 Dn+3 Dn+4 WRITE COUNTER HOLD WRITE WITH COUNTER Notes: 25. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH. 26. The “Internal Address” is equal to the “External Address” when ADS = VIL and equals the counter output when ADS = VIH. Document #: 38-06050 Rev. *A Page 13 of 17 CY7C09269A CY7C09369A Switching Waveforms (continued) Counter Reset (Pipelined Outputs)[14, 26, 27, 28] tCYC2 tCL2 tCH2 CLK tSA ADDRESS INTERNAL ADDRESS AX tSW tHW 0 1 An tHA An+1 An An+1 R/W tSAD ADS tSCN CNTEN tSRST CNTRST DATAIN tHRST tSD D0 tHD tHCN tHAD DATAOUT COUNTER RESET WRITE ADDRESS 0 READ ADDRESS 0 Q0 READ ADDRESS 1 Q1 READ ADDRESS n Qn Notes: 27. CE0, UB, and LB = VIL; CE1 = VIH. 28. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. Document #: 38-06050 Rev. *A Page 14 of 17 CY7C09269A CY7C09369A Read/Write and Enable Operation[29, 30, 31] Inputs OE X X X L H X CLK CE0 H X L L L CE1 X L H H H R/W X X L H X Outputs I/O0–I/O17 High-Z High-Z DIN DOUT High-Z Operation Deselected[32] Deselected[32] Write Read[34] Outputs Disabled Address Counter Control Operation[29, 33, 34, 35] Address X An X X Previous Address X X An An CLK ADS X L H H CNTEN X X H L CNTRST L H H H I/O Dout(0) Dout(n) Dout(n) Dout(n+1) Mode Reset Load Hold Increment Operation Counter Reset to Address 0 Address Load into Counter External Address Blocked—Counter Disabled Counter Enabled—Internal Address Generation Notes: 29. “X” = “Don’t Care,” “H” = VIH, “L” = VIL. 30. ADS, CNTEN, CNTRST = “Don’t Care.” 31. OE is an asynchronous input signal. 32. When CE changes state in the pipelined mode, deselection and read happen in the following clock cycle. 33. CE0 and OE = VIL; CE1 and R/W = VIH. 34. Data shown for flow-through mode; pipelined mode output will be delayed by one cycle. 35. Counter operation is independent of CE0 and CE1. Document #: 38-06050 Rev. *A Page 15 of 17 CY7C09269A CY7C09369A Ordering Information 16K x16 Synchronous Dual-Port SRAM Speed (ns) 6.5[1] 7.5 9 12 Ordering Code CY7C09269A-6AC CY7C09269A-7AC CY7C09269A-9AC CY7C09269A-12AC Package Name A100 A100 A100 A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack Operating Range Commercial Commercial Commercial Commercial 16K x18 Synchronous Dual-Port SRAM Speed (ns) 6.5[1] 7.5 9 12 Ordering Code CY7C09369A-6AC CY7C09369A-7AC CY7C09369A-9AC CY7C09369A-12AC Package Name A100 A100 A100 A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack Operating Range Commercial Commercial Commercial Commercial Package Diagram 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 51-85048-B Document #: 38-06050 Rev. *A Page 16 of 17 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C09269A CY7C09369A Document Title: CY7C09269A/CY7C09369A 16K x 16/18 Synchronous Dual Port Static RAM Document Number: 38-06050 REV. ** *A ECN NO. 110202 122300 Issue Date 11/11/01 12/27/02 Orig. of Change SZV RBI Description of Change Change from Spec number: 38-00836 to 38-06050 Power up requirements added to Maximum Ratings Information Document #: 38-06050 Rev. *A Page 17 of 17