25/0251
CY7C09349A
CY7C09359A
4K/8K x 18
Synchronous Dual-Port Static RAM
Features
• True dual-ported memory cells which allow simultaneous access of the same memory location
• Two Flow-Through/Pipelined devices
— 4K x 18 organization (CY7C09349A)
— 8K x 18 organization (CY7C09359A)
• Three Modes
— Flow-Through
• Low operating power
— Active = 200 mA (typical)
— Standby = 0.05 mA (typical)
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally
— Shorten cycle times
— Minimize bus noise
— Pipelined
— Burst
• Pipelined output mode on both ports allows fast
100-MHz cycle time
• 0.35-micron CMOS for optimum speed/power
• High-speed clock to data access 6.5[1]/7.5/9/12 ns
(max.)
•
•
•
•
•
— Supported in Flow-Through and Pipelined modes
Dual Chip Enables for easy depth expansion
Upper and lower byte controls for bus matching
Automatic power-down
Commercial and Industrial temperature ranges
Available in 100-pin TQFP
v
Logic Block Diagram
R/WL
UBL
R/WR
UBR
CE0L
CE1L
LBL
1
CE0R
CE1R
LBR
1
0
0
0/1
0/1
OEL
OER
0/1
FT/PipeL
1b 0b 1a 0a
b
0a 1a 0b 1b
a
a
b
0/1
9
FT/PipeR
9
I/O9L–I/O17L
I/O9R–I/O17R
I/O
Control
9
I/O
Control
9
I/O0L–I/O8L
[2]
A0L–A11/12L
CLKL
ADSL
CNTENL
CNTRSTL
I/O0R–I/O8R
12/13
12/13
Counter/
Address
Register
Decode
True Dual-Ported
RAM Array
Counter/
Address
Register
Decode
[2]
A0R–A11/12R
CLKR
ADSR
CNTENR
CNTRSTR
Notes:
1. See page 6 for Load Conditions.
2. A0–A11 for 4K; A0–A12 for 8K devices.
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-06048 Rev. **
Revised September 19, 2001
CY7C09349A
CY7C09359A
Functional Description
The CY7C09349A and CY7C09359A are high-speed synchronous CMOS 4K and 8K x 18 dual-port static RAMs. Two ports
are provided, permitting independent, simultaneous access
for reads and writes to any location in memory.[3] Registers on
control, address, and data lines allow for minimal set-up and
hold times. In pipelined output mode, data is registered for
decreased cycle time. Clock to data valid tCD2 = 6.5 ns[1] (pipelined). Flow-through mode can also be used to bypass the
pipelined output register to eliminate access latency. In flowthrough mode data will be available tCD1 = 15 ns after the
address is clocked into the device. Pipelined output or flowthrough mode is selected via the FT/Pipe pin.
Each port contains a burst counter on the input address register. The internal write pulse width is independent of the LOWto-HIGH transition of the clock signal. The internal write pulse
is self-timed to allow the shortest possible cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce the static power consumption. The use of multiple Chip Enables allows easier banking
of multiple chips for depth expansion configurations. In the
pipelined mode, one cycle is required with CE0 LOW and CE1
HIGH to reactivate the outputs.
Counter enable inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS). When the port’s Count Enable (CNTEN) is asserted,
the address counter will increment on each LOW-to-HIGH
transition of that port’s clock signal. This will read/write one
word from/into each successive address location until CNTEN
is deasserted. The counter can address the entire memory
array and will loop back to the start. Counter Reset (CNTRST)
is used to reset the burst counter.
All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.
Note:
3. When simultaneously writing to the same location, final value cannot be determined.
Document #: 38-06048 Rev. **
Page 2 of 17
CY7C09349A
CY7C09359A
Pin Configuration
A7R
A6R
A5R
A4R
A3R
A2R
A1R
A0R
CNTENR
CLKR
ADSR
GND
GND
ADSL
CLKL
CNTENL
A0L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
100-Pin TQFP (Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
A9L
1
75
A8R
A10L
2
74
A9R
A11L
3
73
A10R
[3] A12L
4
72
NC
5
71
A11R
[3]
A12R
NC
6
70
NC
NC
7
69
NC
LBL
8
68
NC
UBL
9
67
LBR
CE0L
10
66
UBR
CE1L
11
65
CE0R
CNTRSTL
12
64
CE1R
R/WL
13
63
CNTRSTR
OEL
14
62
R/WR
VCC
15
61
GND
FT/PIPEL
16
60
OER
I/O17L
17
59
FT/PIPER
I/O16L
18
58
I/O17R
GND
19
57
GND
I/O15L
20
56
I/O16R
I/O14L
21
55
I/O15R
I/O13L
22
54
I/O14R
1/012L
23
53
I/O13R
I/O11L
24
52
I/O12R
I/O10L
25
51
I/O11R
CY7C09359A (8K x 18)
CY7C09349A (4K x 18)
I/10R
I/O9R
I/O8R
I/O7R
VCC
I/O6R
I/O5R
I/O4R
I/O3R
I/O2R
I/01R
I/O0R
GND
I/O0L
I/O1L
GND
I/O2L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
VCC
I/O8L
I/O9L
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Selection Guide
CY7C09349A
CY7C09359A
-6[1]
CY7C09349A
CY7C09359A
-7
CY7C09349A
CY7C09359A
-9
CY7C09349A
CY7C09359A
-12
fMAX2 (MHz) (Pipelined)
100
83
67
50
Max. Access Time (ns) (Clock to Data, Pipelined)
6.5
7.5
9
12
Typical Operating Current ICC (mA)
250
235
215
195
Typical Standby Current for ISB1 (mA)
(Both Ports TTL Level)
45
40
35
30
Typical Standby Current for ISB3 (mA)
(Both Ports CMOS Level)
0.05
0.05
0.05
0.05
Note:
4. This pin is NC for CY7C09349A.
Document #: 38-06048 Rev. **
Page 3 of 17
CY7C09349A
CY7C09359A
Pin Definitions
Left Port
Right Port
Description
A0L–A12L
A0R–A12R
Address Inputs (A0–A11 for 4K, A0–A12 for 8K devices).
ADSL
ADSR
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW during
normal read or write transactions. Asserting this signal LOW also loads the burst address
counter with data present on the I/O pins.
CE0L,CE1L
CE0R,CE1R
Chip Enable Input. To select either the left or right port, both CE0 AND CE1 must be asserted
to their active states (CE0 ≤ VIL and CE1 ≥ VIH).
CLKL
CLKR
Clock Signal. This input can be free running or strobed. Maximum clock input rate is fMAX.
CNTENL
CNTENR
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted
LOW.
CNTRSTL
CNTRSTR
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
I/O0L–I/O17L
I/O0R–I/O17R
Data Bus Input/Output (I/O0–I/O15 for x16 devices).
LBL
LBR
Lower Byte Select Input. Asserting this signal LOW enables read and write operations to the
lower byte (I/O0–I/O8 for x18, I/O0–I/O7 for x16) of the memory array. For read operations both
the LB and OE signals must be asserted to drive output data on the lower byte of the data pins.
UBL
UBR
Upper Byte Select Input. Same function as LB, but to the upper byte (I/O8/9L–I/O15/17L).
OEL
OER
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read
operations.
R/WL
R/WR
Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array.
For read operations, assert this pin HIGH.
FT/PIPEL
FT/PIPER
Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW.
For pipelined mode operation, assert this pin HIGH.
GND
Ground Input.
NC
No Connect.
VCC
Power Input.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with Power Applied ..–55°C to +125°C
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage ........................................... >2001V
Latch-Up Current..................................................... >200 mA
Operating Range
Supply Voltage to Ground Potential ............... –0.3V to +7.0V
Range
Ambient
Temperature
DC Voltage Applied to
Outputs in High Z State ................................. –0.5V to +7.0V
VCC
Commercial
0°C to +70°C
5V ± 10%
Industrial[5]
–40°C to +85°C
5V ± 10%
DC Input Voltage............................................ –0.5V to +7.0V
Note:
5. Industrial Parts are available in CY7C09359A only.
Document #: 38-06048 Rev. **
Page 4 of 17
CY7C09349A
CY7C09359A
Electrical Characteristics Over the Operating Range
CY7C09349A
CY7C09359A
-6[1]
Parameter
Description
Output HIGH Voltage
(VCC = Min., IOH = –4.0 mA)
VOL
Output LOW Voltage
(VCC = Min., IOH = +4.0 mA)
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IOZ
Output Leakage Current
ICC
Operating Current
(VCC = Max,
IOUT = 0 mA)
Outputs Disabled
ISB2
ISB3
ISB4
-9
-12
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
VOH
ISB1
-7
2.4
2.4
2.4
0.4
2.2
0.4
2.2
Com’l.
10
250
450
10
235
420
Ind.[5]
Standby Current (Both Com’l.
Ports TTL Level)[6] CEL
Ind.[5]
& CER ≥ VIH, f = fMAX
45
Standby Current (One Com’l.
Port TTL Level)[6] CEL |
Ind.[5]
CER ≥ VIH, f = fMAX
175
Standby Current (Both Com’l.
Ports CMOS Level)[6]
Ind.[5]
CEL & CER ≥ VCC –
0.2V, f = 0
0.05
Standby Current (One
Port CMOS Level)[6]
CEL | CER ≥ VIH,
f = fMAX
160
Com’l.
115
235
0.5
200
40
160
0.05
145
105
220
0.5
185
Ind.[5]
0.4
2.2
0.8
–10
V
0.4
2.2
0.8
–10
2.4
V
0.8
–10
10
215
360
240
410
35
95
50
110
145
205
160
220
0.05
0.5
0.05
0.5
130
170
145
185
V
–10
195
0.8
V
10
µA
300
mA
mA
30
85
mA
mA
125
190
mA
mA
0.05
0.5
mA
mA
110
150
mA
mA
Capacitance
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
10
pF
10
pF
Note:
6. CEL and CER are internal signals. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 ≤ VIL and CE1 ≥ VIH).
Document #: 38-06048 Rev. **
Page 5 of 17
CY7C09349A
CY7C09359A
AC Test Loads
5V
5V
R1 = 893Ω
OUTPUT
C = 30 pF
RTH = 250Ω
OUTPUT
R1 = 893Ω
OUTPUT
C = 30 pF
R2 = 347Ω
C = 5 pF
R2 = 347Ω
VTH = 1.4V
(a) Normal Load (Load 1)
(c) Three-State Delay (Load 2)
(Used for tCKLZ, tOLZ, & tOHZ
including scope and jig)
(b) Thévenin Equivalent (Load 1)
AC Test Loads (Applicable to -6 only)[7]
OUTPUT
Z0 = 50Ω
ALL INPUT PULSES
R = 50Ω
3.0V
C
GND
90%
10%
90%
10%
≤ 3 ns
≤ 3 ns
VTH = 1.4V
(a) Load 1 (-6 only)
1 . 00
0. 90
∆ (ns) for all -12 access times
0. 80
0. 70
0. 60
0. 50
0. 40
0. 30
0. 20
0. 1 0
0. 00
10
15
20
25
30
35
Capacitance (pF)
(b) Load Derating Curve
Note:
7. Test Conditions: C = 10 pF.
Document #: 38-06048 Rev. **
Page 6 of 17
CY7C09349A
CY7C09359A
Switching Characteristics Over the Operating Range
CY7C09349A
CY7C09359A
-6[1]
Parameter
Description
-7
-9
-12
Max.
Unit
fMAX1
fMax Flow-Through
53
45
40
33
MHz
fMAX2
fMax Pipelined
100
83
67
50
MHz
tCYC1
Clock Cycle Time - Flow-Through
tCYC2
Clock Cycle Time - Pipelined
tCH1
Clock HIGH Time - Flow-Through
tCL1
Clock LOW Time - Flow-Through
tCH2
Min.
Max.
Max.
Min.
Max.
Min.
22
25
30
ns
10
12
15
20
ns
6.5
7.5
12
12
ns
6.5
7.5
12
12
ns
Clock HIGH Time - Pipelined
4
5
6
8
ns
tCL2
Clock LOW Time - Pipelined
4
tR
Clock Rise Time
3
3
3
3
ns
tF
Clock Fall Time
3
3
3
3
ns
tSA
Address Set-up Time
tHA
Address Hold Time
tSC
Chip Enable Set-up Time
tHC
Chip Enable Hold Time
tSW
R/W Set-up Time
tHW
R/W Hold Time
tSD
Input Data Set-up Time
tHD
Input Data Hold Time
tSAD
ADS Set-up Time
tHAD
ADS Hold Time
tSCN
CNTEN Set-up Time
tHCN
CNTEN Hold Time
tSRST
CNTRST Set-up Time
tHRST
CNTRST Hold Time
tOE
Output Enable to Data Valid
tOLZ
19
Min.
6
8
ns
3.5
4
4
4
ns
0
0
1
1
ns
3.5
4
4
4
ns
0
0
1
1
ns
3.5
4
4
4
ns
0
0
1
1
ns
3.5
4
4
4
ns
0
0
1
1
ns
3.5
4
4
4
ns
0
0
1
1
ns
3.5
4
4
4
ns
0
0
1
1
ns
3.5
4
4
4
ns
0
0
8
[8]
OE to Low Z
2
[8]
OE to High Z
1
tOHZ
5
1
9
2
7
1
1
10
2
7
1
ns
12
2
7
1
ns
ns
7
ns
tCD1
Clock to Data Valid - Flow-Through
15
18
20
25
ns
tCD2
Clock to Data Valid - Pipelined
6.5
7.5
9
12
ns
tDC
Data Output Hold After Clock HIGH
2
Clock HIGH to Output High Z
2
Clock HIGH to Output Low Z
2
tCKHZ
tCKLZ
[8]
2
9
2
2
9
2
2
2
9
2
2
ns
9
2
ns
ns
Port to Port Delays
tCWDD
Write Port Clock HIGH to Read Data Delay
30
35
40
40
ns
tCCS
Clock to Clock Set-up Time
9
10
15
15
ns
Note:
8. Test conditions used are Load 2.
Document #: 38-06048 Rev. **
Page 7 of 17
CY7C09349A
CY7C09359A
Switching Waveforms
Read Cycle for Flow-Through Output (FT/PIPE = VIL)[9, 10, 11, 12]
tCH1
tCYC1
tCL1
CLK
CE0
tSC
tHC
tSW
tSA
tHW
tHA
tSC
tHC
CE1
R/W
An
ADDRESS
An+1
An+2
An+3
tCKHZ
tDC
tCD1
DATAOUT
Qn
Qn+1
Qn+2
tDC
tCKLZ
tOHZ
tOLZ
OE
tOE
Read Cycle for Pipelined Operation (FT/PIPE = VIH)[9, 10, 11, 12]
tCH2
tCYC2
tCL2
CLK
CE0
tSC
tHC
tSW
tSA
tHW
tHA
tSC
tHC
CE1
R/W
ADDRESS
An
DATAOUT
An+1
1 Latency
An+2
tDC
tCD2
Qn
tCKLZ
An+3
Qn+1
tOHZ
Qn+2
tOLZ
OE
tOE
Notes:
9. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
10. ADS = VIL, CNTEN and CNTRST = VIH.
11. The output is disabled (high-impedance state) by CE0=VIH or CE1 = VIL following the next rising edge of the clock.
12. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
Document #: 38-06048 Rev. **
Page 8 of 17
CY7C09349A
CY7C09359A
Switching Waveforms (continued)
Bank Select Pipelined Read[13, 14]
tCH2
tCYC2
tCL2
CLKL
tHA
tSA
ADDRESS(B1)
A0
A1
A3
A2
A4
A5
tHC
tSC
CE0(B1)
tCD2
tHC
tSC
tCD2
tHA
tSA
tDC
A0
ADDRESS(B2)
A1
tDC
tSC
tCKLZ
A3
A2
tCKHZ
D3
D1
D0
DATAOUT(B1)
tCD2
tCKHZ
A4
A5
tHC
CE0(B2)
tSC
tCD2
tHC
DATAOUT(B2)
tCKHZ
tCD2
D4
D2
tCKLZ
tCKLZ
Left Port Write to Flow-Through Right Port Read[15, 16, 17, 18]
CLKL
tSW
tHW
tSA
tHA
R/WL
ADDRESSL
NO
MATCH
MATCH
tHD
tSD
DATAINL
VALID
tCCS
CLKR
R/WR
ADDRESSR
tCD1
tSW
tSA
tHW
tHA
NO
MATCH
MATCH
tCWDD
DATAOUTR
tCD1
VALID
tDC
VALID
tDC
Notes:
13. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this data sheet.
ADDRESS(B1) = ADDRESS(B2).
14. UB, LB, OE and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.
15. The same waveforms apply for a right port write to flow-through left port read.
16. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
17. OE = VIL for the right port, which is being read from. OE = VIH for the left port, which is being written to.
18. It tCCS ≤ maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS>maximum specified, then data is not valid
until tCCS + tCD1. tCWDD does not apply in this case.
Document #: 38-06048 Rev. **
Page 9 of 17
CY7C09349A
CY7C09359A
Switching Waveforms (continued)
Pipelined Read-to-Write-to-Read (OE = VIL)[12, 19, 20, 21]
tCH2
tCYC2
tCL2
CLK
CE0
tSC
tHC
CE1
tSW
tHW
R/W
tSW
tHW
An
ADDRESS
An+1
tSA
An+2
An+2
An+3
An+4
tSD tHD
tHA
DATAIN
tCD2
tCKHZ
Dn+2
tCD2
tCKLZ
Qn
DATAOUT
READ
Qn+3
NO OPERATION
WRITE
READ
Pipelined Read-to-Write-to-Read (OE Controlled)[12, 19, 20, 21]
tCH2
tCYC2
tCL2
CLK
CE0
tSC
tHC
CE1
R/W
tSW tHW
tSW
tHW
An
An+1
An+2
An+3
An+4
An+5
ADDRESS
tSA
tHA
tSD tHD
Dn+2
DATAOUT
Dn+3
tCD2
DATAIN
tCKLZ
tCD2
Qn
Qn+4
tOHZ
OE
READ
WRITE
READ
Notes:
19. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals.
20. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
21. During “No operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
Document #: 38-06048 Rev. **
Page 10 of 17
CY7C09349A
CY7C09359A
Switching Waveforms (continued)
Flow-Through Read-to-Write-to-Read (OE = VIL)[10, 12, 19, 20]
tCH1
tCYC1
tCL1
CLK
CE0
tSC
tHC
CE1
tSW
tHW
R/W
tSW
tHW
An
ADDRESS
An+1
tSA
DATAIN
An+2
An+2
tSD
tHA
An+3
tHD
Dn+2
tCD1
tCD1
DATAOUT
An+4
tCD1
Qn
Qn+1
tDC
tCKHZ
READ
tCD1
Qn+3
tCKLZ
NO
OPERATION
WRITE
tDC
READ
Flow-Through Read-to-Write-to-Read (OE Controlled)[10, 12, 19, 20]
tCH1
tCYC1
tCL1
CLK
CE0
tSC
tHC
CE1
tSW
tHW
R/W
tSW
tHW
An
An+1
An+2
An+3
An+4
An+5
ADDRESS
tSA
DATAIN
tSD
tHA
DATAOUT
Dn+2
tDC
tCD1
tHD
Dn+3
tOE
tCD1
Qn
tCD1
Qn+4
tOHZ
tCKLZ
tDC
OE
READ
Document #: 38-06048 Rev. **
WRITE
READ
Page 11 of 17
CY7C09349A
CY7C09359A
Switching Waveforms (continued)
Pipelined Read with Address Counter Advance[22]
tCH2
tCYC2
tCL2
CLK
tSA
tHA
ADDRESS
An
tSAD
tHAD
ADS
tSAD
tHAD
tSCN
tHCN
CNTEN
tSCN
DATAOUT
tHCN
Qx-1
tCD2
Qx
READ
EXTERNAL
ADDRESS
Qn
Qn+1
tDC
READ WITH COUNTER
Qn+2
COUNTER HOLD
Qn+3
READ WITH COUNTER
Flow-Through Read with Address Counter Advance[22]
tCH1
tCYC1
tCL1
CLK
tSA
tHA
An
ADDRESS
tSAD
tHAD
ADS
tSAD
tHAD
tSCN
tHCN
CNTEN
tSCN
DATAOUT
tHCN
tCD1
Qx
Qn
Qn+1
tDC
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
Qn+3
Qn+2
COUNTER HOLD
READ
WITH
COUNTER
Note:
22. CE0 and OE = VIL; CE1, R/W and CNTRST = VIH.
Document #: 38-06048 Rev. **
Page 12 of 17
CY7C09349A
CY7C09359A
Switching Waveforms (continued)
Write with Address Counter Advance (Flow-Through or Pipelined Outputs)[23, 24]
tCH2
tCYC2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL
ADDRESS
An
tSAD
tHAD
tSCN
tHCN
An+1
An+2
An+3
An+4
ADS
CNTEN
Dn
DATAIN
tSD
tHD
WRITE EXTERNAL
ADDRESS
Dn+1
Dn+1
WRITE WITH
COUNTER
Dn+2
WRITE COUNTER
HOLD
Dn+3
Dn+4
WRITE WITH COUNTER
Notes:
23. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH.
24. The “Internal Address” is equal to the “External Address” when ADS = VIL and equals the counter output when ADS = VIH.
Document #: 38-06048 Rev. **
Page 13 of 17
CY7C09349A
CY7C09359A
Switching Waveforms (continued)
Counter Reset (Pipelined Outputs)[12, 19, 25, 26]
tCH2
tCYC2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL
ADDRESS
AX
0
tSW
tHW
tSD
tHD
1
An+1
An
An+1
R/W
tSAD
tHAD
tSCN
tHCN
tSRST
tHRST
ADS
CNTEN
CNTRST
DATAIN
D0
DATAOUT
Q0
COUNTER
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS 1
Q1
Qn
READ
ADDRESS n
Notes:
25. CE0, UB, and LB = VIL; CE1 = VIH.
26. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset.
Document #: 38-06048 Rev. **
Page 14 of 17
CY7C09349A
CY7C09359A
Read/Write and Enable Operation[27, 28, 29]
Inputs
OE
CLK
CE0
Outputs
CE1
R/W
I/O0–I/O17
Operation
[30]
X
H
X
X
High-Z
Deselected
X
X
L
X
High-Z
Deselected[30]
X
L
H
L
DIN
L
L
H
H
DOUT
Read[30]
L
H
X
High-Z
Outputs Disabled
H
X
Write
Address Counter Control Operation[27, 31, 32, 33]
Address
Previous
Address
X
CLK
ADS
CNTEN
CNTRST
I/O
Mode
Operation
X
X
X
L
Dout(0)
Reset
Counter Reset to Address 0
An
X
L
X
H
Dout(n)
Load
Address Load into Counter
X
An
H
H
H
Dout(n)
Hold
External Address Blocked—Counter
Disabled
X
An
H
L
H
Dout(n+1)
Increment
Counter Enabled—Internal Address
Generation
Notes:
27. “X” = “Don’t Care,” “H” = VIH, “L” = VIL.
28. ADS, CNTEN, CNTRST = “Don’t Care.”
29. OE is an asynchronous input signal.
30. When CE changes state in the pipelined mode, deselection and read happen in the following clock cycle.
31. CE0 and OE = VIL; CE1 and R/W = VIH.
32. Data shown for flow-through mode; pipelined mode output will be delayed by one cycle.
33. Counter operation is independent of CE0 and CE1.
Document #: 38-06048 Rev. **
Page 15 of 17
CY7C09349A
CY7C09359A
Ordering Information
4K x18 Synchronous Dual-Port SRAM
Speed
(ns)
Package
Name
Ordering Code
Package Type
Operating
Range
6.5[1]
CY7C09349A-6AC
A100
100-Pin Thin Quad Flat Pack
Commercial
7.5
CY7C09349A-7AC
A100
100-Pin Thin Quad Flat Pack
Commercial
9
CY7C09349A-9AC
A100
100-Pin Thin Quad Flat Pack
Commercial
12
CY7C09349A-12AC
A100
100-Pin Thin Quad Flat Pack
Commercial
8K x18 Synchronous Dual-Port SRAM
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
6.5[1]
CY7C09359A-6AC
A100
100-Pin Thin Quad Flat Pack
Commercial
7.5
CY7C09359A-7AC
A100
100-Pin Thin Quad Flat Pack
Commercial
9
CY7C09359A-9AC
A100
100-Pin Thin Quad Flat Pack
Commercial
CY7C09359A-9AI
A100
100-Pin Thin Quad Flat Pack
Industrial
CY7C09359A-12AC
A100
100-Pin Thin Quad Flat Pack
Commercial
12
Package Diagram
100-Pin Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-B
Document #: 38-06048 Rev. **
Page 16 of 17
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C09349A
CY7C09359A
Document Title: CY7C09349A/CY7C09359A 4K/8K x 18 Synchronous Dual-Port Static RAM
Document Number: 38-06048
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
110200
09/29/01
SZV
Change from Spec number: 38-00834 to 38-06048
Document #: 38-06048 Rev. **
Page 17 of 17
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