CY7C09369V-9AXCT

CY7C09269V/79V/89V CY7C09369V/89V 3.3 V 16K / 32K / 64K × 16 / 18 Synchronous Dual-Port Static RAM 3.3 V 16K / 32K / 64K × 16 / 18 Synchronous Dual-Port Static RAM Features ❐ ❐ ■ True dual-ported memory cells that allow simultaneous access of the same memory location ■ Six flow through/pipelined devices: ❐ 16K × 16 / 18 organization (CY7C09269V/369V) ❐ 32K × 16 organization (CY7C09279V) ❐ 64K × 16 / 18 organization (CY7C09289V/389V) ■ Three modes: ❐ Flow through ❐ Pipelined ❐ Burst ■ Pipelined output mode on both ports allows fast 100 MHz operation ■ 0.35 micron CMOS for optimum speed and power ■ High speed clock to data access: 7.5[1], 9, 12 ns (max) ■ 3.3 V low operating power: Active = 115 mA (typical) Standby = 10 A (typical) ■ Fully synchronous interface for easier operation ■ Burst counters increment addresses internally: ❐ Shorten cycle times ❐ Minimize bus noise ❐ Supported in flow through and pipelined modes ■ Dual chip enables easy depth expansion ■ Upper and lower byte controls for bus matching ■ Automatic power down ■ Commercial and industrial temperature ranges ■ Pb-free 100-pin TQFP package available Functional Description For a complete list of related documentation, click here. Logic Block Diagram R/WL UBL R/WR UBR CE0L CE1L LBL 1 CE0R CE1R LBR 1 0 0 0/1 0/1 OEL OER 1b 0b 1a 0a 0/1 FT/PipeL [2] b 0a 1a 0b 1b a a b 0/1 8/9 FT/PipeR 8/9 I/O8/9L–I/O15/17L [3] I/O Control 8/9 I/O Control 8/9 I/O0L–I/O7/8L [4] A0L–A13/14/15L CLKL ADSL CNTENL CNTRSTL [2] I/O8/9R–I/O15/17R [3] I/O0R–I/O7/8R 14/15/16 14/15/16 Counter/ Address Register Decode Counter/ Address Register Decode True Dual-Ported RAM Array [4] A0R–A13/14/15R CLKR ADSR CNTENR CNTRSTR Notes 1. See Figure 4 on page 8 for Load Conditions. 2. I/O8–I/O15 for × 16 devices; I/O9–I/O17 for × 18 devices. 3. I/O0–I/O7 for × 16 devices. I/O0–I/O8 for × 18 devices. 4. A0–A13 for 16K; A0–A14 for 32K; A0–A15 for 64K devices. Cypress Semiconductor Corporation Document Number: 38-06056 Rev. *M • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 21, 2016 CY7C09269V/79V/89V CY7C09369V/89V Contents Pin Configurations ........................................................... 3 Selection Guide ................................................................ 5 Pin Definitions .................................................................. 5 Functional Overview ........................................................ 6 Maximum Ratings ............................................................. 7 Operating Range ............................................................... 7 Electrical Characteristics ................................................. 7 Capacitance ...................................................................... 7 AC Test Loads and Waveforms ....................................... 8 Switching Characteristics ................................................ 9 Switching Waveforms .................................................... 10 Read/Write and Enable Operation ................................. 18 Address Counter Control Operation ............................. 18 Ordering Information ...................................................... 19 16K × 16 3.3 V Synchronous Dual-Port SRAM ......... 19 32K × 16 3.3 V Synchronous Dual-Port SRAM ......... 19 Document Number: 38-06056 Rev. *M 16K × 18 3.3 V Synchronous Dual-Port SRAM ......... 19 64K × 18 3.3 V Synchronous Dual-Port SRAM ......... 19 Ordering Code Definitions ......................................... 20 Package Diagrams .......................................................... 21 Acronyms ........................................................................ 22 Document Conventions ................................................. 22 Units of Measure ....................................................... 22 Document History Page ................................................. 23 Sales, Solutions, and Legal Information ...................... 25 Worldwide Sales and Design Support ....................... 25 Products .................................................................... 25 PSoC® Solutions ...................................................... 25 Cypress Developer Community ................................. 25 Technical Support ..................................................... 25 Page 2 of 25 CY7C09269V/79V/89V CY7C09369V/89V Pin Configurations A8R A7R A6R A5R A4R A3R A2R A1R A0R CNTENR CLKR ADSR GND ADSL CLKL CNTENL A0L A1L A2L A3L A4L A5L A6L A7L A8L Figure 1. 100-pin TQFP pinout (Top View) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A9L 1 75 A9R A10L 2 74 A10R A11L 3 73 A11R A12L 4 72 A12R A13L 5 71 A13R [5] A14L [6] A15L 6 70 A14R [5] 7 69 A15R [6] NC 8 68 NC NC 9 67 NC LBL 10 66 LBR UBL 11 CE0L 12 CY7C09289V (64K × 16) CY7C09279V (32K × 16) CY7C09269V (16K × 16) 65 UBR 64 CE0R 63 CE1R 62 CNTRSTR 61 GND CE1L 13 CNTRSTL 14 VCC 15 R/WL 16 60 R/WR OEL 17 59 OER FT/PIPEL 18 58 FT/PIPER [7] GND 19 57 GND I/O15L 20 56 I/O15R I/O14L 21 55 I/O14R I/O13L 22 54 I/O13R I/O12L 23 53 I/O12R I/O11L 24 52 I/O11R I/O10L 25 51 I/O10R [7] NC I/O9R I/O8R I/O7R VCC I/O6R I/O5R I/O4R I/O3R I/O2R I/O1R I/O0R GND I/O0L I/O1L GND I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L VCC I/O8L I/O9L 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Notes 5. This pin is NC for CY7C09269V. 6. This pin is NC for CY7C09269V and CY7C09279V. 7. For CY7C09269V and CY7C09279V, pin #18 connected to VCC is pin compatible to an IDT 5 V × 16 pipelined device; connecting pin #18 and #58 to GND is pin compatible to an IDT 5 V × 16 flow through device. Document Number: 38-06056 Rev. *M Page 3 of 25 CY7C09269V/79V/89V CY7C09369V/89V Pin Configurations (continued) A7R A6R A5R A4R A3R A2R A1R A0R CNTENR CLKR ADSR GND GND ADSL CLKL CNTENL A0L A1L A2L A3L A4L A5L A6L A7L A8L Figure 2. 100-pin TQFP pinout (Top View) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A9L 1 75 A8R A10L 2 74 A9R A11L 3 73 A10R A12L 4 72 A11R A13L 5 71 A12R [8] A14L [9] A15L 6 70 A13R 7 69 A14R LBL 8 68 A15R LBR [8] [9] UBL 9 67 CE0L 10 66 UBR CE1L 11 65 CE0R CNTRSTL 12 64 CE1R R/WL 13 63 CNTRSTR OEL 14 62 R/WR VCC 15 61 GND FT/PIPEL 16 60 OER I/O17L 17 59 FT/PIPER I/O16L 18 58 I/O17R CY7C09389V (64K × 18) CY7C09369V (16K × 18) GND 19 57 GND I/O15L 20 56 I/O16R I/O14L 21 55 I/O15R I/O13L 22 54 I/O14R I/O12L 23 53 I/O13R I/O11L 24 52 I/O12R I/O10L 25 51 I/O11R I/O10R I/O9R I/O8R I/O7R VCC I/O6R I/O5R I/O4R I/O3R I/O2R I/01R I/O0R GND I/O0L I/O1L GND I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L VCC I/O8L I/O9L 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Notes 8. This pin is NC for CY7C09369V. 9. This pin is NC for CY7C09369V. Document Number: 38-06056 Rev. *M Page 4 of 25 CY7C09269V/79V/89V CY7C09369V/89V Selection Guide Specifications CY7C09269V/79V/89V CY7C09369V/89V CY7C09269V/79V/89V CY7C09369V/89V CY7C09269V/79V/89V CY7C09369V/89V -7[10] -9 -12 fMAX2 (MHz) (Pipelined) 83 67 50 Max. Access Time (ns) (Clock to Data, Pipelined) 7.5 9 12 Typical Operating Current ICC (mA) 155 135 115 Typical Standby Current for ISB1 (mA) (Both Ports TTL Level) 25 20 20 Typical Standby Current for ISB3 (A) (Both Ports CMOS Level) 10 10 10 Pin Definitions Left Port Right Port Description A0L–A15L A0R–A15R Address Inputs (A0–A14 for 32K, A0–A13 for 16K devices). ADSL ADSR Address Strobe Input. Used as an address qualifier. This signal must be asserted LOW to access the part using an externally supplied address. Asserting this signal LOW also loads the burst counter with the address present on the address pins. CE0L, CE1L CE0R,CE1R Chip Enable Input. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0  VIL and CE1 VIH). CLKL CLKR Clock Signal. This input can be free running or strobed. Maximum clock input rate is fMAX. CNTENL CNTENR Counter Enable Input. Asserting this signal LOW increments the burst address counter of its respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted LOW. CNTRSTL CNTRSTR Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN. I/O0L–I/O17L I/O0R–I/O17R Data Bus Input/Output (I/O0–I/O15 for × 16 devices). LBL LBR Lower Byte Select Input. Asserting this signal LOW enables read and write operations to the lower byte. (I/O0–I/O8 for × 18, I/O0–I/O7 for × 16) of the memory array. For read operations both the LB and OE signals must be asserted to drive output data on the lower byte of the data pins. UBL UBR Upper Byte Select Input. Same function as LB, but to the upper byte (I/O8/9L–I/O15/17L). OEL OER Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read operations. R/WL R/WR Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For read operations, assert this pin HIGH. FT/PIPEL FT/PIPER Flow Through/Pipelined Select Input. For flow through mode operation, assert this pin LOW. For pipelined mode operation, assert this pin HIGH. GND Ground Input. NC No Connect. VCC Power Input. Note 10. See Figure 4 on page 8 for Load Conditions. Document Number: 38-06056 Rev. *M Page 5 of 25 CY7C09269V/79V/89V CY7C09369V/89V Functional Overview The CY7C09269V/79V/89V and CY7C09369V/89V are high speed 3.3 V synchronous CMOS 16K, 32K, and 64K × 16 and 16K and 64K × 18 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory [11]. Registers on control, address, and data lines allow for minimal setup and hold times. In pipelined output mode, data is registered for decreased cycle time and clock to data valid tCD2 = 7.5 ns [12] (pipelined). Flow through mode can also be used to bypass the pipelined output register to eliminate access latency. In flow through mode, data is available tCD1 = 18 ns after the address is clocked into the device. Pipelined output or flow through mode is selected through the FT/Pipe pin. Each port contains a burst counter on the input address register. The internal write pulse width is independent of the LOW to HIGH transition of the clock signal. The internal write pulse is self timed to allow the shortest possible cycle times. A HIGH on CE0 or LOW on CE1 for one clock cycle powers down the internal circuitry to reduce the static power consumption. The use of multiple Chip Enables enables easier banking of multiple chips for depth expansion configurations. In the pipelined mode, one cycle is required with CE0 LOW and CE1 HIGH to reactivate the outputs. Counter enable inputs are provided to stall the operation of the address input and use the internal address generated by the internal counter for fast interleaved memory applications. A port’s burst counter is loaded with the port’s Address Strobe (ADS). When the port’s Count Enable (CNTEN) is asserted, the address counter increments on each LOW to HIGH transition of that port’s clock signal. This reads/writes one word from or into each successive address location, until CNTEN is deasserted. The counter can address the entire memory array and loop back to the start. Counter Reset (CNTRST) is used to reset the burst counter. All parts are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages. Notes 11. When writing simultaneously to the same location, the final value cannot be guaranteed. 12. See Figure 4 on page 8 for Load Conditions. Document Number: 38-06056 Rev. *M Page 6 of 25 CY7C09269V/79V/89V CY7C09369V/89V DC Input Voltage  0.5 V to VCC + 0.5 V Maximum Ratings Exceeding maximum ratings [13] may impair the useful life of the device. These user guidelines are not tested. Storage Temperature 65 C to +150 °C Ambient Temperature with Power Applied 55 C to +125 C Supply Voltage to Ground Potential  0.5 V to +4.6 V DC Voltage Applied to Outputs in High Z State  0.5 V to VCC + 0.5 V Output Current into Outputs (LOW) ............................ 20 mA Static Discharge Voltage (per MIL-STD-883, Method 3015) .......................... > 1100 V Latch up Current .................................................... > 200 mA Operating Range Range Ambient Temperature VCC 0 °C to +70 °C 3.3 V  300 mV –40 °C to +85 °C 3.3 V  300 mV Commercial Industrial Electrical Characteristics Over the Operating Range CY7C09269V/79V/89V CY7C09369V/89V Parameter Description -7[14] Min -9 Typ Max Min Unit -12 Typ Max Min Typ Max VOH Output HIGH Voltage (VCC = Min, lOH = –4.0 mA) 2.4 – – 2.4 – – 2.4 – – V VOL Output LOW Voltage (VCC = Min, lOH = +4.0 mA) – – 0.4 – – 0.4 – – 0.4 V VIH Input HIGH Voltage 2.0 – – 2.0 – – 2.0 – – V VIL Input LOW Voltage IOZ Output Leakage Current ICC Operating Current (VCC = Max, IOUT = 0 mA) Outputs Disabled ISB1 ISB2 ISB3 ISB4 – – 0.8 – – 0.8 – – 0.8 V –10 – 10 –10 – 10 –10 – 10 A Commercial – 155 275 – 135 230 – 115 180 mA Industrial – 275 390 – 185 300 – – – mA Standby Current (Both Ports TTL Level) [15] CEL & CER  VIH, f = fMAX Commercial – 25 85 – 20 75 – 20 70 mA Industrial – 85 120 – 35 85 – – – mA Standby Current (One Port TTL Level) [15] CEL | CER  VIH, f = fMAX Commercial – 105 165 – 95 155 – 85 140 mA Industrial – 165 210 – 105 165 – – – mA Standby Current (Both Ports CMOS Level) [15] CEL & CER  VCC – 0.2 V, f = 0 Commercial – 10 250 – 10 250 – 10 250 A Industrial – 10 250 – 10 250 – – – A Standby Current (One Port CMOS Level) [15] CEL | CER  VIH, f = fMAX Commercial – 95 125 – 85 115 – 75 100 mA Industrial – 125 170 – 95 125 – – – mA Capacitance Parameter [16] Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 3.3 V Max Unit 10 pF 10 pF Notes 13. The voltage on any input or I/O pin can not exceed the power pin during power up. 14. See Figure 4 on page 8 for Load Conditions. 15. CEL and CER are internal signals. To select either the left or right port, both CE0 and CE1 must be asserted to their active states (CE0  VIL and CE1 VIH). 16. Tested initially and after any design or process changes that may affect these parameters. Document Number: 38-06056 Rev. *M Page 7 of 25 CY7C09269V/79V/89V CY7C09369V/89V AC Test Loads and Waveforms Figure 3. AC Test Loads and Waveforms 3.3 V 3.3 V R1 = 590  C = 30 pF RTH = 250  OUTPUT OUTPUT R1 = 590  OUTPUT C = 30 pF R2 = 435  C = 5 pF VTH = 1.4 V (a) Normal Load (Load 1) R2 = 435  (c) Three-State Delay(Load 2) (Used for tCKLZ, tOLZ, and tOHZ including scope and jig) (b) Thévenin Equivalent (Load 1) Figure 4. AC Test Loads (Applicable to -7 only) [17] ALL INPUT PULSES Z0 = 50  R = 50  OUTPUT 3.0 V C GND 10% 90% 10% 90%  3 ns  3 ns VTH = 1.4 V (a) Load 1 (-7 only) 0. 60 Δ (ns) for all -7 access times 0. 50 0. 40 0. 30 0. 20 0. 1 0 0. 00 10 15 20 25 30 35 Capacitance (pF) (b) Load Derating Curve Note 17. Test Conditions: C = 10 pF. Document Number: 38-06056 Rev. *M Page 8 of 25 CY7C09269V/79V/89V CY7C09369V/89V Switching Characteristics Over the Operating Range CY7C09269V/79V/89V CY7C09369V/89V Parameter Description -7 [18] -9 Unit -12 Min Max Min Max Min Max fMAX1 fMax Flow Through – 45 – 40 – 33 MHz fMAX2 fMax Pipelined – 83 – 67 – 50 MHz tCYC1 Clock Cycle Time - Flow Through 22 – 25 – 30 – ns tCYC2 Clock Cycle Time - Pipelined 12 – 15 – 20 – ns tCH1 Clock HIGH Time - Flow Through 7.5 – 12 – 12 – ns tCL1 Clock LOW Time - Flow Through 7.5 – 12 – 12 – ns tCH2 Clock HIGH Time - Pipelined 5 – 6 – 8 – ns tCL2 Clock LOW Time - Pipelined 5 – 6 – 8 – ns tR Clock Rise Time – 3 – 3 – 3 ns tF Clock Fall Time – 3 – 3 – 3 ns tSA Address Set-Up Time 4 – 4 – 4 – ns tHA Address Hold Time 0 – 1 – 1 – ns tSC Chip Enable Setup Time 4 – 4 – 4 – ns tHC Chip Enable Hold Time 0 – 1 – 1 – ns tSW R/W Set-Up Time 4 – 4 – 4 – ns tHW R/W Hold Time 0 – 1 – 1 – ns tSD Input Data Setup Time 4 – 4 – 4 – ns tHD Input Data Hold Time 0 – 1 – 1 – ns tSAD ADS Set-Up Time 4 – 4 – 4 – ns tHAD ADS Hold Time 0 – 1 – 1 – ns CNTEN Setup Time 4.5 – 5 – 5 – ns CNTEN Hold Time 0 – 1 – 1 – ns tSRST CNTRST Setup Time 4 – 4 – 4 – ns tHRST CNTRST Hold Time 0 – 1 – 1 – ns 9 – 10 – 12 ns tSCN tHCN Output Enable to Data Valid – tOLZ [19, 20] OE to Low Z 2 – 2 – 2 – ns [19, 20] OE to High Z 1 7 1 7 1 7 ns tOE tOHZ tCD1 Clock to Data Valid - Flow Through – 18 – 20 – 25 ns tCD2 Clock to Data Valid - Pipelined – 7.5 – 9 – 12 ns tDC Data Output Hold After Clock HIGH 2 – 2 – 2 – ns tCKHZ [19, 20] Clock HIGH to Output High Z 2 9 2 9 2 9 ns [19, 20] Clock HIGH to Output Low Z 2 – 2 – 2 – ns tCKLZ Port to Port Delays tCWDD Write Port Clock HIGH to Read Data Delay – 35 – 40 – 40 ns tCCS Clock to Clock Setup Time – 10 – 15 – 15 ns Notes 18. See Figure 4 on page 8 for Load Conditions. 19. Test conditions used are Load 2. 20. This parameter is guaranteed by design, but it is not production tested. Document Number: 38-06056 Rev. *M Page 9 of 25 CY7C09269V/79V/89V CY7C09369V/89V Switching Waveforms Figure 5. Read Cycle for Flow Through Output (FT/PIPE = VIL) [21, 22, 23, 24] tCYC1 tCH1 tCL1 CLK CE0 tSC tHC tSW tSA tHW tHA tSC tHC CE1 R/W An ADDRESS An+1 An+2 An+3 tCKHZ tDC tCD1 DATAOUT Qn Qn+1 Qn+2 tDC tCKLZ tOHZ tOLZ OE tOE Figure 6. Read Cycle for Pipelined Operation (FT/PIPE = VIH) tCH2 tCYC2 [21, 22, 23, 24] tCL2 CLK CE0 tSC tHC tSW tSA tHW tHA tSC tHC CE1 R/W ADDRESS DATAOUT An An+1 1 Latency An+2 tDC tCD2 Qn tCKLZ An+3 Qn+1 tOHZ Qn+2 tOLZ OE tOE Notes 21. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 22. ADS = VIL, CNTEN and CNTRST = VIH. 23. The output is disabled (high impedance state) by CE0=VIH or CE1 = VIL following the next rising edge of the clock. 24. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only. Document Number: 38-06056 Rev. *M Page 10 of 25 CY7C09269V/79V/89V CY7C09369V/89V Switching Waveforms (continued) Figure 7. Bank Select Pipelined Read [25, 26] tCH2 tCYC2 tCL2 CLKL tHA tSA ADDRESS(B1) A0 A1 A3 A2 A4 A5 tHC tSC CE0(B1) tCD2 tHC tSC tCD2 tHA tSA tDC A0 ADDRESS(B2) A1 tDC tSC tCKLZ A3 A2 tCKHZ D3 D1 D0 DATAOUT(B1) tCD2 tCKHZ A4 A5 tHC CE0(B2) tSC tCD2 tHC DATAOUT(B2) tCKHZ tCD2 D4 D2 tCKLZ Figure 8. Left Port Write to Flow Through Right Port Read tCKLZ [27, 28, 29, 30] CLKL tSW tHW tSA tHA R/WL ADDRESSL tHD tSD DATAINL NO MATCH MATCH VALID tCCS CLKR R/WR ADDRESSR tCD1 tSW tSA tHW tHA NO MATCH MATCH tCWDD DATAOUTR tCD1 VALID tDC VALID tDC Notes 25. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this datasheet. ADDRESS(B1) = ADDRESS(B2). 26. UB, LB, OE and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH. 27. The same waveforms apply for a right port write to flow through left port read. 28. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 29. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to. 30. It tCCS  maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS>maximum specified, then data is not valid until tCCS + tCD1. tCWDD does not apply in this case. Document Number: 38-06056 Rev. *M Page 11 of 25 CY7C09269V/79V/89V CY7C09369V/89V Switching Waveforms (continued) Figure 9. Pipelined Read-to-Write-to-Read (OE = VIL) [31, 32, 33, 34] tCH2 tCYC2 tCL2 CLK CE0 tSC tHC CE1 tSW tHW R/W tSW tHW An ADDRESS An+1 tSA An+2 An+2 An+3 An+4 tSD tHD tHA DATAIN tCD2 tCKHZ Dn+2 tCD2 tCKLZ Qn DATAOUT READ Qn+3 NO OPERATION WRITE READ Figure 10. Pipelined Read-to-Write-to-Read (OE Controlled) [31, 32, 33, 34] tCH2 tCYC2 tCL2 CLK CE0 tSC tHC CE1 R/W tSW tHW tSW tHW An An+1 An+2 An+3 An+4 An+5 ADDRESS tSA tHA tSD tHD Dn+2 DATAIN Dn+3 tCD2 DATAOUT tCKLZ tCD2 Qn Qn+4 tOHZ OE READ WRITE READ Notes 31. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only. 32. Output state (High, LOW, or high impedance) is determined by the previous cycle control signals. 33. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 34. During “No Operation”, data in memory at the selected address may be corrupted and must be rewritten to ensure data integrity. Document Number: 38-06056 Rev. *M Page 12 of 25 CY7C09269V/79V/89V CY7C09369V/89V Switching Waveforms (continued) Figure 11. Flow Through Read-to-Write-to-Read (OE = VIL) [35, 36, 37, 38] tCH1 tCYC1 tCL1 CLK CE0 tSC tHC CE1 tSW tHW R/W tSW tHW An ADDRESS An+1 tSA DATAIN DATAOUT An+2 An+2 tSD tHA An+3 An+4 tHD Dn+2 tCD1 tCD1 Qn tCD1 Qn+1 tDC tCKHZ READ tCD1 Qn+3 NO OPERATION tCKLZ WRITE tDC READ Notes 35. ADS = VIL, CNTEN and CNTRST = VIH. 36. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only. 37. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 38. During “No Operation”, data in memory at the selected address may be corrupted and must be rewritten to ensure data integrity. Document Number: 38-06056 Rev. *M Page 13 of 25 CY7C09269V/79V/89V CY7C09369V/89V Switching Waveforms (continued) Figure 12. Flow Through Read-to-Write-to-Read (OE Controlled) [39, 40, 41, 42, 43] tCH1 tCYC1 tCL1 CLK CE0 tSC tHC CE1 tSW tHW R/W tSW tHW An An+1 An+2 An+3 An+4 An+5 ADDRESS tSA DATAIN tSD tHA DATAOUT Dn+2 tDC tCD1 tHD Dn+3 tOE tCD1 Qn tCD1 Qn+4 tOHZ tCKLZ tDC OE READ WRITE READ Notes 39. ADS = VIL, CNTEN and CNTRST = VIH. 40. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only. 41. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 42. During “No Operation”, data in memory at the selected address may be corrupted and must be rewritten to ensure data integrity. 43. Output state (High, LOW, or high impedance) is determined by the previous cycle control signals. Document Number: 38-06056 Rev. *M Page 14 of 25 CY7C09269V/79V/89V CY7C09369V/89V Switching Waveforms (continued) Figure 13. Pipelined Read with Address Counter Advance [44] tCH2 tCYC2 tCL2 CLK tSA ADDRESS tHA An tSAD tHAD ADS tSAD tHAD tSCN tHCN CNTEN tSCN DATAOUT tHCN Qx-1 tCD2 Qx Qn tDC READ EXTERNAL ADDRESS READ WITH COUNTER Qn+1 Qn+2 COUNTER HOLD Qn+3 READ WITH COUNTER Figure 14. Flow Through Read with Address Counter Advance [44] tCH1 tCYC1 tCL1 CLK tSA tHA An ADDRESS tSAD tHAD ADS tSAD tHAD tSCN tHCN CNTEN tSCN DATAOUT tHCN tCD1 Qx Qn Qn+1 Qn+2 Qn+3 tDC READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD READ WITH COUNTER Note 44. CE0 and OE = VIL; CE1, R/W and CNTRST = VIH. Document Number: 38-06056 Rev. *M Page 15 of 25 CY7C09269V/79V/89V CY7C09369V/89V Switching Waveforms (continued) Figure 15. Write with Address Counter Advance (Flow Through or Pipelined Outputs) [45, 46] Write D(An) Write D(An+1) Write D(An+1) Write D(An+2) Write D(An+3) Write D(An+4) Notes 45. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH. 46. The “Internal Address” is equal to the “External Address” when ADS = VIL and equals the counter output when ADS = VIH. Document Number: 38-06056 Rev. *M Page 16 of 25 CY7C09269V/79V/89V CY7C09369V/89V Switching Waveforms (continued) Figure 16. Counter Reset (Pipelined Outputs) [47, 48, 49, 50] tCH2 tCYC2 tCL2 CLK tSA tHA An ADDRESS INTERNAL ADDRESS AX 0 tSW tHW tSD tHD 1 An+1 An An+1 R/W tSAD tHAD tSCN tHCN tSRST tHRST ADS CNTEN CNTRST DATAIN D0 DATAOUT Q0 COUNTER RESET WRITE ADDRESS 0 READ ADDRESS 0 READ ADDRESS 1 Q1 Qn READ ADDRESS n Notes 47. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only. 48. Output state (High, LOW, or high impedance) is determined by the previous cycle control signals. 49. CE0, UB, and LB = VIL; CE1 = VIH. 50. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. Document Number: 38-06056 Rev. *M Page 17 of 25 CY7C09269V/79V/89V CY7C09369V/89V Read/Write and Enable Operation The Read/Write and Enable Operation is described as follows. [51, 52, 53] Inputs OE Operation CE0 CE1 R/W I/O0–I/O17 X H X X High Z Deselected [54] X X L X High Z Deselected [54] X L H L DIN L L H H DOUT Read [55] L H X High Z Outputs Disabled H CLK Outputs X Write Address Counter Control Operation The Address Counter Control Operation is described as follows. [51, 56, 57, 58] Address Previous Address X X X X An X L X An X An CLK ADS CNTEN CNTRST I/O Mode Operation L Dout(0) Reset Counter Reset to Address 0 X H Dout(n) Load Address Load into Counter H H H Dout(n) Hold External Address Blocked — Counter Disabled H L H Dout(n+1) Increment Counter Enabled — Internal Address Generation Notes 51. “X” = “Don’t Care”, “H” = VIH, “L” = VIL. 52. ADS, CNTEN, CNTRST = “Don’t Care”. 53. OE is an asynchronous input signal. 54. When CE changes state in the pipelined mode, deselection and read happen in the following clock cycle. 55. ADS = VIL, CNTEN and CNTRST = VIH. 56. CE0 and OE = VIL; CE1 and R/W = VIH. 57. Data shown for flow through mode; pipelined mode output is delayed by one cycle. 58. Counter operation is independent of CE0 and CE1. Document Number: 38-06056 Rev. *M Page 18 of 25 CY7C09269V/79V/89V CY7C09369V/89V Ordering Information 16K × 16 3.3 V Synchronous Dual-Port SRAM Speed (ns) 9 Ordering Code CY7C09269V-9AXC Package Diagram Package Type 51-85048 100-pin TQFP (Pb-free) Operating Range Commercial 32K × 16 3.3 V Synchronous Dual-Port SRAM Speed (ns) Ordering Code 7.5 [59] CY7C09279V-7AXC 12 CY7C09279V-12AXC Package Diagram Package Type Operating Range 51-85048 100-pin TQFP (Pb-free) Commercial 51-85048 100-pin TQFP (Pb-free) Commercial 64K × 16 3.3 V Synchronous Dual-Port SRAM Speed (ns) 9 12 Ordering Code Package Diagram Package Type Operating Range CY7C09289V-9AXC 51-85048 100-pin TQFP (Pb-free) Commercial CY7C09289V-9AXI 51-85048 100-pin TQFP (Pb-free) Industrial CY7C09289V-12AXC 51-85048 100-pin TQFP (Pb-free) Commercial 16K × 18 3.3 V Synchronous Dual-Port SRAM Speed (ns) 12 Ordering Code CY7C09369V-12AXC Package Diagram Package Type 51-85048 100-pin TQFP (Pb-free) Operating Range Commercial 64K × 18 3.3 V Synchronous Dual-Port SRAM Speed (ns) 9 Ordering Code CY7C09389V-9AI Package Diagram 51-85048 100-pin TQFP Package Type Operating Range Industrial Note 59. See page 6 for Load Conditions. Document Number: 38-06056 Rev. *M Page 19 of 25 CY7C09269V/79V/89V CY7C09369V/89V Ordering Code Definitions CY 7 C 09 X X9 V - XX X X X Temperature Range: X = C or I C = Commercial; I = Industrial X = Pb-free (RoHS Compliant) Package Type: A = 100-pin TQFP Speed Grade: XX = 7.5 ns or 9 ns or 12 ns V = 3.3 V X9 = Depth: X = 6 or 7 or 8 6 = 16K; 7 = 32K; 8 = 64K Width: X = 2 or 3 2 = × 16; 3 = × 18 09 = Sync Technology Code: C = CMOS Marketing Code: 7 = Dual Port SRAM Company ID: CY = Cypress Document Number: 38-06056 Rev. *M Page 20 of 25 CY7C09269V/79V/89V CY7C09369V/89V Package Diagrams Figure 17. 100-pin TQFP (14 × 14 × 1.4 mm) A100SA Package Outline, 51-85048 51-85048 *J Document Number: 38-06056 Rev. *M Page 21 of 25 CY7C09269V/79V/89V CY7C09369V/89V Acronyms Acronym Document Conventions Description Units of Measure CE Chip Enable CMOS Complementary Metal Oxide Semiconductor °C degree Celsius I/O Input/Output MHz megahertz OE Output Enable µA microampere SRAM Static Random Access Memory mA milliampere TQFP Thin Quad Flat Pack mm millimeter mV millivolt TTL Transistor-Transistor Logic Document Number: 38-06056 Rev. *M Symbol Unit of Measure ns nanosecond  ohm % percent pF picofarad V volt Page 22 of 25 CY7C09269V/79V/89V CY7C09369V/89V Document History Page Document Title: CY7C09269V/79V/89V/CY7C09369V/89V, 3.3 V 16K / 32K / 64K × 16 / 18 Synchronous Dual-Port Static RAM Document Number: 38-06056 Revision ECN Submission Date Orig. of Change Description of Change ** 110215 12/18/01 SZV Change from Spec number: 38-00668 to 38-06056 *A 122306 12/27/02 RBI Updated Maximum Ratings: Added Power up requirements. *B 344354 See ECN PCX Updated Ordering Information (Added Pb-Free Parts). *C 2678221 03/25/2009 VKN / AESA Updated Ordering Information (Added CY7C09379V-12AXCT part). Updated Package Diagrams (updated spec 51-85048 to *C). *D 2896210 03/22/2010 RAME Updated Ordering Information. Updated Package Diagrams. *E 3111417 12/15/2010 ADMU Updated Ordering Information. Added Ordering Code Definitions. *F 3124048 12/30/2010 ADMU No technical updates. *G 3352110 08/23/2011 ADMU Updated Features (Removed CY7C09379V information and also removed -6 speed bin information). Updated Pin Configurations (Removed CY7C09379V information). Updated Selection Guide (Removed CY7C09379V information and also removed -6 speed bin information). Updated Functional Overview (Removed CY7C09379V information). Updated Electrical Characteristics (Removed CY7C09379V information and also removed -6 speed bin information). Updated AC Test Loads and Waveforms (Removed -6 speed bin information). Updated Switching Characteristics (Removed CY7C09379V information and also removed -6 speed bin information). Updated Ordering Information (Removed part CY7C09279V-7AC). Updated Package Diagrams. Added Acronyms and Units of Measure. Updated to new template. *H 3402091 10/12/2011 ADMU Updated Ordering Information (Removed pruned part CY7C09289V-9AI). Updated Package Diagrams. *I 3680923 08/01/2012 ADMU / SMCH Updated Pin Configurations (Updated Figure 2). Updated Switching Characteristics (Changed name of parameter from tCKZ to tCKHZ, changed name of parameter from tCKZ to tCKLZ in the next corresponding row). Updated Switching Waveforms (Updated Figure 15). Updated Address Counter Control Operation. Updated Ordering Information (Removed pruned part CY7C09289V-9AC). Updated Package Diagrams (spec 51-85048 (Changed revision from *E to *G)). *J 3859909 01/07/2013 SMCH Updated Ordering Information (Updated part numbers). *K 4580622 11/27/2014 SMCH Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. Updated Package Diagrams: spec 51-85048 – Changed revision from *G to *I. *L 4918880 09/14/2015 VINI Document Number: 38-06056 Rev. *M Updated Ordering Information (Updated part numbers). Updated to new template. Completing Sunset Review. Page 23 of 25 CY7C09269V/79V/89V CY7C09369V/89V Document History Page (continued) Document Title: CY7C09269V/79V/89V/CY7C09369V/89V, 3.3 V 16K / 32K / 64K × 16 / 18 Synchronous Dual-Port Static RAM Document Number: 38-06056 Revision ECN Submission Date Orig. of Change *M 5183282 03/21/2016 VINI Document Number: 38-06056 Rev. *M Description of Change Updated Pin Configurations: Updated Figure 1 (Fixed typo error in pin number 50). Updated Package Diagrams: spec 51-85048 – Changed revision from *I to *J. Updated to new template. Completing Sunset Review. Page 24 of 25 CY7C09269V/79V/89V CY7C09369V/89V Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products ARM® Cortex® Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers cypress.com/clocks Interface Lighting & Power Control cypress.com/interface cypress.com/psoc PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training cypress.com/powerpsoc Memory PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/memory cypress.com/psoc Technical Support cypress.com/support cypress.com/touch cypress.com/usb cypress.com/wireless © Cypress Semiconductor Corporation 2001-2016. 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Document Number: 38-06056 Rev. *M Revised March 21, 2016 Page 25 of 25