CY7C09379V-12AC

CY7C09269V/79V/89V CY7C09369V/79V/89V 3.3V 16K/32K/64K x 16/18 Synchronous Dual-Port Static RAM Features ■ True dual-ported memory cells that allow simultaneous access of the same memory location ■ Six flow through/pipelined devices: ❐ 16K x 16/18 organization (CY7C09269V/369V) ❐ 32K x 16/18 organization (CY7C09279V/379V) ❐ 64K x 16/18 organization (CY7C09289V/389V) ■ Three modes: ❐ Flow through ❐ Pipelined ❐ Burst ■ 3.3V low operating power: ❐ Active = 115 mA (typical) ❐ Standby = 10 μA (typical) ■ Fully synchronous interface for easier operation ■ Burst counters increment addresses internally: ❐ Shorten cycle times ❐ Minimize bus noise ❐ Supported in flow through and pipelined modes ■ Dual chip enables easy depth expansion ■ Upper and lower byte controls for bus matching ■ Automatic power down ■ Pipelined output mode on both ports allows fast 100 MHz operation ■ Commercial and industrial temperature ranges ■ 0.35 micron CMOS for optimum speed and power ■ Pb-Free 100-pin TQFP package available ■ High speed clock to data access: 6.5[1, 2], 7.5[2], 9, 12 ns (max) Logic Block Diagram R/WL UBL R/WR UBR CE0L CE1L LBL 1 1 0 0 0/1 CE0R CE1R LBR 0/1 OEL OER 1b 0b 1a 0a 0/1 FT/PipeL [3] I/O8/9L–I/O15/17L [4] b 0a 1a 0b 1b a a b 0/1 8/9 FT/PipeR 8/9 I/O Control 8/9 I/O Control 8/9 I/O0L–I/O7/8L [5] A0L–A13/14/15L CLKL ADSL CNTENL CNTRSTL [3] I/O8/9R–I/O15/17R [4] I/O0R–I/O7/8R 14/15/16 14/15/16 Counter/ Address Register Decode Counter/ Address Register Decode True Dual-Ported RAM Array [5] A0R–A13/14/15R CLKR ADSR CNTENR CNTRSTR Notes 1. Call for availability. 2. See page 6 for Load Conditions. 3. I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices. 4. I/O0–I/O7 for x16 devices. I/O0–I/O8 for x18 devices. 5. A0–A13 for 16K; A0–A14 for 32K; A0–A15 for 64K devices. Cypress Semiconductor Corporation Document #: 38-06056 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 25, 2009 [+] Feedback CY7C09269V/79V/89V CY7C09369V/79V/89V Pinouts A8R A7R A6R A5R A4R A3R A2R A1R A0R CNTENR CLKR ADSR GND ADSL CLKL CNTENL A0L A1L A2L A3L A4L A5L A6L A7L A8L Figure 1. 100-Pin TQFP (Top View) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A9L 1 75 A9R A10L 2 74 A10R A11L 3 73 A11R A12L 4 72 A12R A13L 5 71 A13R [6] A14L [7] A15L 6 70 A14R [6] 7 69 A15R [7] NC 8 68 NC NC 9 67 NC LBL 10 66 LBR 65 UBR 64 CE0R 63 CE1R 62 CNTRSTR 61 GND CY7C09289V (64K x 16) CY7C09279V (32K x 16) CY7C09269V (16K x 16) UBL 11 CE0L 12 CE1L 13 CNTRSTL 14 VCC 15 R/WL 16 60 R/WR OEL 17 59 OER FT/PIPEL 18 58 FT/PIPER [8] GND 19 57 GND I/O15L 20 56 I/O15R I/O14L 21 55 I/O14R I/O13L 22 54 I/O13R I/O12L 23 53 I/O12R I/O11L 24 52 I/O11R I/O10L 25 51 I/O10R [8] NC I/O9R I/O8R I/O7R VCC I/O6R I/O5R I/O4R I/O3R I/O2R I/01R I/O0R GND I/O0L I/O1L GND I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L VCC I/O8L I/O9L 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Notes 6. This pin is NC for CY7C09269V. 7. This pin is NC for CY7C09269V and CY7C09279V. 8. For CY7C09269V and CY7C09279V, pin #18 connected to VCC is pin compatible to an IDT 5V x16 pipelined device; connecting pin #18 and #58 to GND is pin compatible to an IDT 5V x16 flow through device. Document #: 38-06056 Rev. *C Page 2 of 19 [+] Feedback CY7C09269V/79V/89V CY7C09369V/79V/89V Pinouts (continued) A7R A6R A5R A4R A3R A2R A1R A0R CNTENR CLKR ADSR GND GND ADSL CLKL CNTENL A0L A1L A2L A3L A4L A5L A6L A7L A8L Figure 2. 100-Pin TQFP (Top View) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A9L 1 75 A8R A10L 2 74 A9R A11L 3 73 A10R A12L 4 72 A11R A13L 5 71 A12R [9] A14L [10] A15L 6 70 A13R 7 69 A14R LBL 8 68 A15R [9] [10] UBL 9 67 LBR CE0L 10 66 UBR 65 CE0R 64 CE1R 63 CNTRSTR 62 R/WR 61 GND 60 OER FT/PIPER CY7C09389V (64K x 18) CE1L 11 CNTRSTL 12 R/WL 13 OEL 14 VCC 15 FT/PIPEL 16 I/O17L 17 59 I/O16L 18 58 I/O17R GND 19 57 GND I/O15L 20 56 I/O16R I/O14L 21 55 I/O15R I/O13L 22 54 I/O14R 1/012L 23 53 I/O13R I/O11L 24 52 I/O12R I/O10L 25 51 I/O11R CY7C09379V (32K x 18) CY7C09369V (16K x 18) I/10R I/O9R I/O8R I/O7R VCC I/O6R I/O5R I/O4R I/O3R I/O2R I/01R I/O0R GND I/O0L I/O1L GND I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L VCC I/O8L I/O9L 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Selection Guide CY7C09269V/79V/89V CY7C09369V/79V/89V CY7C09269V/79V/89V CY7C09369V/79V/89V CY7C09269V/79V/89V CY7C09369V/79V/89V CY7C09269V/79V/89V CY7C09369V/79V/89V -6[1, 2] -7[2] fMAX2 (MHz) (Pipelined) -9 -12 100 83 67 50 Max. Access Time (ns) (Clock to Data, Pipelined) 6.5 7.5 9 12 Typical Operating Current ICC (mA) 175 155 135 115 Typical Standby Current for ISB1 (mA) (Both Ports TTL Level) 25 25 20 20 Typical Standby Current for ISB3 (μA) (Both Ports CMOS Level) 10 10 10 10 Specifications Notes 9. This pin is NC for CY7C09369V. 10. This pin is NC for CY7C09369V and CY7C09379V. Document #: 38-06056 Rev. *C Page 3 of 19 [+] Feedback CY7C09269V/79V/89V CY7C09369V/79V/89V Pin Definitions Left Port Right Port Description A0L–A15L A0R–A15R Address Inputs (A0–A14 for 32K, A0–A13 for 16K devices). ADSL ADSR Address Strobe Input. Used as an address qualifier. This signal must be asserted LOW to access the part using an externally supplied address. Asserting this signal LOW also loads the burst counter with the address present on the address pins. CE0L, CE1L CE0R,CE1R Chip Enable Input. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 ≤ VIL and CE1 ≥ VIH). CLKL CLKR Clock Signal. This input can be free running or strobed. Maximum clock input rate is fMAX. CNTENL CNTENR Counter Enable Input. Asserting this signal LOW increments the burst address counter of its respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted LOW. CNTRSTL CNTRSTR Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN. I/O0L–I/O17L I/O0R–I/O17R LBL LBR Data Bus Input/Output (I/O0–I/O15 for x16 devices). Lower Byte Select Input. Asserting this signal LOW enables read and write operations to the lower byte. (I/O0–I/O8 for x18, I/O0–I/O7 for x16) of the memory array. For read operations both the LB and OE signals must be asserted to drive output data on the lower byte of the data pins. UBL UBR Upper Byte Select Input. Same function as LB, but to the upper byte (I/O8/9L–I/O15/17L). OEL OER Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read operations. R/WL R/WR Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For read operations, assert this pin HIGH. FT/PIPEL FT/PIPER Flow Through/Pipelined Select Input. For flow through mode operation, assert this pin LOW. For pipelined mode operation, assert this pin HIGH. GND Ground Input. NC No Connect. VCC Power Input. Functional Description The CY7C09269V/79V/89V and CY7C09369V/79V/89V are high speed 3.3V synchronous CMOS 16K, 32K, and 64K x 16/18 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory[11]. Registers on control, address, and data lines allow for minimal setup and hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid tCD2 = 6.5 ns[1, 2] (pipelined). Flow through mode can also be used to bypass the pipelined output register to eliminate access latency. In flow through mode, data is available tCD1 = 18 ns after the address is clocked into the device. Pipelined output or flow through mode is selected through the FT/Pipe pin. Each port contains a burst counter on the input address register. The internal write pulse width is independent of the LOW to HIGH transition of the clock signal. The internal write pulse is self timed to allow the shortest possible cycle times. A HIGH on CE0 or LOW on CE1 for one clock cycle powers down the internal circuitry to reduce the static power consumption. The use of multiple Chip Enables enables easier banking of multiple chips for depth expansion configurations. In the pipelined mode, one cycle is required with CE0 LOW and CE1 HIGH to reactivate the outputs. Counter enable inputs are provided to stall the operation of the address input and use the internal address generated by the internal counter for fast interleaved memory applications. A port’s burst counter is loaded with the port’s Address Strobe (ADS). When the port’s Count Enable (CNTEN) is asserted, the address counter increments on each LOW to HIGH transition of that port’s clock signal. This reads/writes one word from or into each successive address location, until CNTEN is deasserted. The counter can address the entire memory array and loop back to the start. Counter Reset (CNTRST) is used to reset the burst counter. All parts are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages. Note 11. When writing simultaneously to the same location, the final value cannot be guaranteed. Document #: 38-06056 Rev. *C Page 4 of 19 [+] Feedback CY7C09269V/79V/89V CY7C09369V/79V/89V DC Input Voltage ..........................................−0.5V to VCC+0.5V Maximum Ratings [12] Output Current into Outputs (LOW)............................. 20 mA Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Static Discharge Voltage.......................................... > 1100V (per MIL-STD-883, Method 3015) Storage Temperature ..................................... −65°C to +150°C Latch up Current.................................................... > 200 mA Ambient Temperature with Power Applied.................................................. −55°C to +125°C Operating Range Supply Voltage to Ground Potential .................−0.5V to +4.6V Range DC Voltage Applied to Outputs in High Z State ..............................................−0.5V to VCC+0.5V Ambient Temperature VCC 0°C to +70°C 3.3V ± 300 mV –40°C to +85°C 3.3V ± 300 mV Commercial Industrial Electrical Characteristics Over the Operating Range CY7C09269V/79V/89V CY7C09369V/79V/89V Parameter Description -6[1, 2] -7[2] -9 Min Typ Max Min Typ Max Min VOH Output HIGH Voltage (VCC = Min. lOH = –4.0 mA) VOL Output LOW Voltage (VCC = Min. lOH = +4.0 mA) VIH Input HIGH Voltage VIL Input LOW Voltage IOZ Output Leakage Current ICC Operating Current (VCC = Max, IOUT = 0 mA) Outputs Disabled ISB1 ISB2 ISB3 ISB4 2.4 2.4 2.0 2.0 Com’l. 10 2.0 175 320 Indust. Standby Current (Both Ports TTL Level)[13] CEL & CER ≥ VIH, f = fMAX Com’l. Indust. Standby Current (One Port TTL Level)[13] CEL | CER ≥ VIH, f = fMAX Indust. Com’l. 25 95 115 175 Com’l. Standby Current (Both Ports CMOS Level)[13] Indust. CEL & CER ≥ VCC – 0.2V, f = 0 10 Standby Current (One Port CMOS Level)[13] CEL | CER ≥ VIH, f = fMAX 105 135 Com’l. Indust. 250 10 V 0.4 0.4 2.0 0.8 –10 Typ Max 2.4 0.4 0.8 –10 Typ Max Min 2.4 0.4 Unit -12 V 0.8 –10 10 155 275 135 230 275 390 185 300 25 85 20 75 85 120 35 85 105 165 95 155 165 210 105 165 10 250 10 250 10 250 10 250 95 125 85 115 125 170 95 125 V –10 115 0.8 V 10 μA 180 mA mA 20 70 mA mA 85 140 mA mA 10 250 μA μA 75 100 mA mA Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max Unit 10 pF 10 pF Notes 12. The voltage on any input or I/O pin can not exceed the power pin during power up. 13. CEL and CER are internal signals. To select either the left or right port, both CE0 and CE1 must be asserted to their active states (CE0 ≤ VIL and CE1 ≥ VIH). Document #: 38-06056 Rev. *C Page 5 of 19 [+] Feedback CY7C09269V/79V/89V CY7C09369V/79V/89V Figure 3. AC Test Loads and Waveforms 3.3V 3.3V R1 = 590Ω RTH = 250Ω OUTPUT OUTPUT R1 = 590Ω OUTPUT C = 30 pF C = 30 pF R2 = 435Ω C = 5 pF VTH = 1.4V (a) Normal Load (Load 1) R2 = 435Ω (c) Three-State Delay(Load 2) (Used for tCKLZ, tOLZ, and tOHZ including scope and jig) (b) Thévenin Equivalent (Load 1) Figure 4. AC Test Loads (Applicable to -6 and -7 only) [14] Z0 = 50Ω OUTPUT ALL INPUT PULSES R = 50Ω 3.0V C GND 10% 90% 10% 90% ≤ 3 ns ≤ 3 ns VTH = 1.4V (a) Load 1 (-6 and -7 only) 0. 60 '(ns) for all -7 access times 0. 50 0. 40 0. 30 0. 20 0. 1 0 0. 00 10 15 20 25 30 35 Capacitance (pF) (b) Load Derating Curve Note 14. Test Conditions: C = 10 pF. Document #: 38-06056 Rev. *C Page 6 of 19 [+] Feedback CY7C09269V/79V/89V CY7C09369V/79V/89V Switching Characteristics Over the Operating Range CY7C09269V/79V/89V CY7C09369V/79V/89V Parameter Description -6 [1, 2] Min Max -7[2] Min -9 Max Min Unit -12 Max Min Max fMAX1 fMax Flow Through 53 45 40 33 MHz fMAX2 fMax Pipelined 100 83 67 50 MHz tCYC1 Clock Cycle Time - Flow Through 19 22 25 30 ns tCYC2 Clock Cycle Time - Pipelined 10 12 15 20 ns tCH1 Clock HIGH Time - Flow Through 6.5 7.5 12 12 ns tCL1 Clock LOW Time - Flow Through 6.5 7.5 12 12 ns tCH2 Clock HIGH Time - Pipelined 4 5 6 8 ns tCL2 Clock LOW Time - Pipelined 4 5 6 8 ns tR Clock Rise Time 3 3 3 3 ns tF Clock Fall Time 3 3 3 3 ns tSA Address Set-Up Time tHA Address Hold Time tSC Chip Enable Setup Time 3.5 4 4 4 ns tHC Chip Enable Hold Time 0 0 1 1 ns tSW R/W Set-Up Time tHW R/W Hold Time tSD tHD tSAD ADS Set-Up Time tHAD ADS Hold Time 3.5 4 4 4 ns 0 0 1 1 ns 3.5 4 4 4 ns 0 0 1 1 ns Input Data Setup Time 3.5 4 4 4 ns Input Data Hold Time 0 0 1 1 ns 3.5 4 4 4 ns 0 0 1 1 ns CNTEN Setup Time 3.5 4.5 5 5 ns tHCN CNTEN Hold Time 0 0 1 1 ns tSRST CNTRST Setup Time 3.5 4 4 4 ns tHRST CNTRST Hold Time 0 tSCN 0 8 1 9 1 10 ns 12 ns tOE Output Enable to Data Valid tOLZ[15,16] OE to Low Z 2 tOHZ[15,16] OE to High Z 1 tCD1 Clock to Data Valid - Flow Through 15 18 20 25 ns tCD2 Clock to Data Valid - Pipelined 6.5 7.5 9 12 ns tDC Data Output Hold After Clock HIGH 2 tCKZ[15,16] Clock HIGH to Output High Z 2 tCKZ[15,16] Clock HIGH to Output Low Z 2 2 7 1 2 7 2 9 2 1 2 7 2 9 2 2 1 ns 7 2 9 2 2 ns ns 9 2 ns ns Port to Port Delays tCWDD Write Port Clock HIGH to Read Data Delay 30 35 40 40 ns tCCS Clock to Clock Setup Time 9 10 15 15 ns Notes 15. Test conditions used are Load 2. 16. This parameter is guaranteed by design, but it is not production tested. Document #: 38-06056 Rev. *C Page 7 of 19 [+] Feedback CY7C09269V/79V/89V CY7C09369V/79V/89V Switching Waveforms Figure 5. Read Cycle for Flow Through Output (FT/PIPE = VIL) [17, 18, 19, 20] tCH1 tCYC1 tCL1 CLK CE0 tSC tHC tSW tSA tHW tHA tSC tHC CE1 R/W An ADDRESS An+1 An+2 An+3 tCKHZ tDC tCD1 DATAOUT Qn Qn+1 Qn+2 tDC tCKLZ tOHZ tOLZ OE tOE Figure 6. Read Cycle for Pipelined Operation (FT/PIPE = VIH)[17, 18, 19, 20] tCH2 tCYC2 tCL2 CLK CE0 tSC tHC tSW tSA tHW tHA tSC tHC CE1 R/W ADDRESS An DATAOUT An+1 1 Latency An+2 tDC tCD2 Qn tCKLZ An+3 Qn+1 tOHZ Qn+2 tOLZ OE tOE Notes 17. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 18. ADS = VIL, CNTEN and CNTRST = VIH. 19. The output is disabled (high impedance state) by CE0=VIH or CE1 = VIL following the next rising edge of the clock. 20. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only. Document #: 38-06056 Rev. *C Page 8 of 19 [+] Feedback CY7C09269V/79V/89V CY7C09369V/79V/89V Switching Waveforms (continued) Figure 7. Bank Select Pipelined Read[21, 22] tCH2 tCYC2 tCL2 CLKL tHA tSA ADDRESS(B1) A0 A1 A3 A2 A4 A5 tHC tSC CE0(B1) tCD2 tHC tSC tCD2 tHA tSA tDC A0 ADDRESS(B2) A1 tDC tSC tCKLZ A3 A2 tCKHZ D3 D1 D0 DATAOUT(B1) tCD2 tCKHZ A4 A5 tHC CE0(B2) tSC tCD2 tHC DATAOUT(B2) tCKHZ tCD2 D4 D2 tCKLZ tCKLZ Figure 8. Left Port Write to Flow Through Right Port Read[23, 24, 25, 26] CLKL tSW tHW tSA tHA R/WL ADDRESSL NO MATCH MATCH tHD tSD DATAINL VALID tCCS CLKR R/WR ADDRESSR tCD1 tSW tSA tHW tHA NO MATCH MATCH tCWDD DATAOUTR tCD1 VALID tDC VALID tDC Notes 21. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this datasheet. ADDRESS(B1) = ADDRESS(B2). 22. UB, LB, OE and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH. 23. The same waveforms apply for a right port write to flow through left port read. 24. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 25. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to. 26. It tCCS ≤ maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS>maximum specified, then data is not valid until tCCS + tCD1. tCWDD does not apply in this case. Document #: 38-06056 Rev. *C Page 9 of 19 [+] Feedback CY7C09269V/79V/89V CY7C09369V/79V/89V Switching Waveforms (continued) Figure 9. Pipelined Read-to-Write-to-Read (OE = VIL)[20, 27, 28, 29] tCH2 tCYC2 tCL2 CLK CE0 tSC tHC CE1 tSW tHW R/W tSW tHW An ADDRESS An+1 tSA An+2 An+2 An+3 An+4 tSD tHD tHA DATAIN tCD2 tCKHZ Dn+2 tCD2 tCKLZ Qn DATAOUT READ Qn+3 NO OPERATION WRITE READ Figure 10. Pipelined Read-to-Write-to-Read (OE Controlled)[20, 27, 28, 29] tCH2 tCYC2 tCL2 CLK CE0 tSC tHC CE1 R/W tSW tHW tSW tHW An An+1 An+2 An+3 An+4 An+5 ADDRESS tSA tHA tSD tHD Dn+2 DATAIN Dn+3 tCD2 DATAOUT tCKLZ tCD2 Qn Qn+4 tOHZ OE READ WRITE READ Notes 27. Output state (High, LOW, or high impedance) is determined by the previous cycle control signals. 28. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 29. During “No Operation”, data in memory at the selected address may be corrupted and must be rewritten to ensure data integrity. Document #: 38-06056 Rev. *C Page 10 of 19 [+] Feedback CY7C09269V/79V/89V CY7C09369V/79V/89V Switching Waveforms (continued) Figure 11. Flow Through Read-to-Write-to-Read (OE = VIL)[18, 20, 28, 29] tCH1 tCYC1 tCL1 CLK CE0 tSC tHC CE1 tSW tHW R/W tSW tHW An ADDRESS An+1 tSA DATAIN An+2 An+2 tSD tHA An+3 tHD Dn+2 tCD1 tCD1 DATAOUT An+4 tCD1 Qn Qn+1 tDC tCKHZ READ tCD1 Qn+3 tCKLZ NO OPERATION WRITE tDC READ Figure 12. Flow Through Read-to-Write-to-Read (OE Controlled)[18, 20, 27, 28, 29] tCH1 tCYC1 tCL1 CLK CE0 tSC tHC CE1 tSW tHW R/W tSW tHW An An+1 An+2 An+3 An+4 An+5 ADDRESS tSA DATAIN tSD tHA DATAOUT Dn+2 tDC tCD1 tHD Dn+3 tOE tCD1 Qn tCD1 Qn+4 tOHZ tCKLZ tDC OE READ Document #: 38-06056 Rev. *C WRITE READ Page 11 of 19 [+] Feedback CY7C09269V/79V/89V CY7C09369V/79V/89V Switching Waveforms (continued) Figure 13. Pipelined Read with Address Counter Advance[30] tCH2 tCYC2 tCL2 CLK tSA ADDRESS tHA An tSAD tHAD ADS tSAD tHAD tSCN tHCN CNTEN tSCN DATAOUT tHCN Qx-1 tCD2 Qx Qn tDC READ EXTERNAL ADDRESS READ WITH COUNTER Qn+1 Qn+2 COUNTER HOLD Qn+3 READ WITH COUNTER Figure 14. Flow Through Read with Address Counter Advance[30] tCH1 tCYC1 tCL1 CLK tSA tHA An ADDRESS tSAD tHAD ADS tSAD tHAD tSCN tHCN CNTEN tSCN DATAOUT tHCN tCD1 Qx Qn Qn+1 Qn+2 Qn+3 tDC READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD READ WITH COUNTER Note 30. CE0 and OE = VIL; CE1, R/W and CNTRST = VIH. Document #: 38-06056 Rev. *C Page 12 of 19 [+] Feedback CY7C09269V/79V/89V CY7C09369V/79V/89V Switching Waveforms (continued) Figure 15. Write with Address Counter Advance (Flow Through or Pipelined Outputs)[31, 32] tCH2 tCYC2 tCL2 CLK tSA tHA An ADDRESS INTERNAL ADDRESS An tSAD tHAD tSCN tHCN An+1 An+2 An+3 An+4 ADS CNTEN Dn DATAIN tSD tHD WRITE EXTERNAL ADDRESS Dn+1 Dn+1 WRITE WITH COUNTER Dn+2 WRITE COUNTER HOLD Dn+3 Dn+4 WRITE WITH COUNTER Notes 31. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH. 32. The “Internal Address” is equal to the “External Address” when ADS = VIL and equals the counter output when ADS = VIH. Document #: 38-06056 Rev. *C Page 13 of 19 [+] Feedback CY7C09269V/79V/89V CY7C09369V/79V/89V Switching Waveforms (continued) Figure 16. Counter Reset (Pipelined Outputs)[20, 27, 33, 34] tCH2 tCYC2 tCL2 CLK tSA tHA An ADDRESS INTERNAL ADDRESS AX 0 tSW tHW tSD tHD 1 An+1 An An+1 R/W tSAD tHAD tSCN tHCN tSRST tHRST ADS CNTEN CNTRST DATAIN D0 DATAOUT Q0 COUNTER RESET WRITE ADDRESS 0 READ ADDRESS 0 READ ADDRESS 1 Q1 Qn READ ADDRESS n Notes 33. CE0, UB, and LB = VIL; CE1 = VIH. 34. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. Document #: 38-06056 Rev. *C Page 14 of 19 [+] Feedback CY7C09269V/79V/89V CY7C09369V/79V/89V Read/Write and Enable Operation[35, 36, 37] Inputs OE Outputs Operation CE0 CE1 R/W I/O0–I/O17 X H X X High-Z Deselected[38] X X L X High-Z Deselected[38] X L H L DIN L L H H DOUT Read[35] L H X High-Z Outputs Disabled H CLK X Write Address Counter Control Operation[35, 39, 40, 41] Address Previous Address X CLK ADS CNTEN CNTRST I/O Mode Operation X X X L Dout(0) Reset Counter Reset to Address 0 An X L X H Dout(n) Load Address Load into Counter X An H H H Dout(n) Hold External Address Blocked—Counter Disabled X An H L H Dout(n+1) Increment Counter Enabled—Internal Address Generation X An H L H Dout(n+1) Increment Counter Enabled—Internal Address Generation Notes 35. “X” = “Don’t Care”, “H” = VIH, “L” = VIL. 36. ADS, CNTEN, CNTRST = “Don’t Care”. 37. OE is an asynchronous input signal. 38. When CE changes state In the pipelined mode, deselection and read happen in the following clock cycle. 39. CE0 and OE = VIL; CE1 and R/W = VIH. 40. Data shown for flow through mode; pipelined mode output is delayed by one cycle. 41. Counter operation is independent of CE0 and CE1. Document #: 38-06056 Rev. *C Page 15 of 19 [+] Feedback CY7C09269V/79V/89V CY7C09369V/79V/89V Ordering Information 16K x16 3.3V Synchronous Dual-Port SRAM Speed (ns) 6.5[1, 2] Ordering Code CY7C09269V-6AC Package Diagram 51-85048 CY7C09269V-6AXC 7.5[2] CY7C09269V-7AC CY7C09269V-9AC 51-85048 Commercial 100-Pin Thin Quad Flat Pack Commercial 100-Pin Thin Quad Flat Pack (Pb-Free) 51-85048 CY7C09269V-9AXC 12 100-Pin Thin Quad Flat Pack Operating Range 100-Pin Thin Quad Flat Pack (Pb-Free) CY7C09269V-7AXC 9 Package Type 100-Pin Thin Quad Flat Pack Commercial 100-Pin Thin Quad Flat Pack (Pb-Free) CY7C09269V-9AI 51-85048 100-Pin Thin Quad Flat Pack Industrial CY7C09269V-12AC 51-85048 100-Pin Thin Quad Flat Pack Commercial CY7C09269V-12AXC 100-Pin Thin Quad Flat Pack (Pb-Free) 32K x16 3.3V Synchronous Dual-Port SRAM Speed (ns) 6.5[1, 2] Ordering Code CY7C09279V-6AC Package Diagram 51-85048 CY7C09279V-6AXC 7.5 [2] CY7C09279V-7AC 12 100-Pin Thin Quad Flat Pack Operating Range Commercial 100-Pin Thin Quad Flat Pack (Pb-Free) 51-85048 CY7C09279V-7AXC 9 Package Type 100-Pin Thin Quad Flat Pack Commercial 100-Pin Thin Quad Flat Pack (Pb-Free) CY7C09279V-9AC 51-85048 100-Pin Thin Quad Flat Pack Commercial CY7C09279V-9AI 51-85048 100-Pin Thin Quad Flat Pack Industrial CY7C09279V-12AC 51-85048 100-Pin Thin Quad Flat Pack Commercial CY7C09279V-12AXC 100-Pin Thin Quad Flat Pack (Pb-Free) 64K x16 3.3V Synchronous Dual-Port SRAM Speed (ns) 6.5[1, 2] Ordering Code CY7C09289V-6AC Package Diagram 51-85048 CY7C09289V-6AXC 7.5 [2] CY7C09289V-7AC CY7C09289V-9AC 51-85048 CY7C09289V-12AC CY7C09289V-12AXC Document #: 38-06056 Rev. *C 100-Pin Thin Quad Flat Pack Commercial 100-Pin Thin Quad Flat Pack Commercial 100-Pin Thin Quad Flat Pack (Pb-Free) 51-85048 CY7C09289V-9AXI 12 Commercial 100-Pin Thin Quad Flat Pack (Pb-Free) 51-85048 CY7C09289V-9AXC CY7C09289V-9AI 100-Pin Thin Quad Flat Pack Operating Range 100-Pin Thin Quad Flat Pack (Pb-Free) CY7C09289V-7AXC 9 Package Type 100-Pin Thin Quad Flat Pack Industrial 100-Pin Thin Quad Flat Pack (Pb-Free) 51-85048 100-Pin Thin Quad Flat Pack Commercial 100-Pin Thin Quad Flat Pack (Pb-Free) Page 16 of 19 [+] Feedback CY7C09269V/79V/89V CY7C09369V/79V/89V Ordering Information (Continued) 16K x18 3.3V Synchronous Dual-Port SRAM Speed (ns) 6.5[1, 2] Ordering Code CY7C09369V-6AC Package Diagram 51-85048 CY7C09369V-6AXC 7.5[2] CY7C09369V-7AC 51-85048 Commercial 100-Pin Thin Quad Flat Pack Commercial 100-Pin Thin Quad Flat Pack (Pb-Free) CY7C09369V-7AI 51-85048 100-Pin Thin Quad Flat Pack Industrial CY7C09369V-9AC 51-85048 100-Pin Thin Quad Flat Pack Commercial CY7C09369V-9AXC 12 100-Pin Thin Quad Flat Pack Operating Range 100-Pin Thin Quad Flat Pack (Pb-Free) CY7C09369V-7AXC 9 Package Type 100-Pin Thin Quad Flat Pack (Pb-Free) CY7C09369V-9AI 51-85048 100-Pin Thin Quad Flat Pack Industrial CY7C09369V-12AC 51-85048 100-Pin Thin Quad Flat Pack Commercial CY7C09369V-12AXC 100-Pin Thin Quad Flat Pack (Pb-Free) 32K x18 3.3V Synchronous Dual-Port SRAM Speed (ns) 6.5[1, 2] Ordering Code CY7C09379V-6AC Package Diagram Package Type 51-85048 100-Pin Thin Quad Flat Pack CY7C09379V-6AXC Operating Range Commercial 100-Pin Thin Quad Flat Pack (Pb-Free) 7.5[2] CY7C09379V-7AC 51-85048 100-Pin Thin Quad Flat Pack Commercial 9 CY7C09379V-9AC 51-85048 100-Pin Thin Quad Flat Pack Commercial CY7C09379V-9AI 51-85048 100-Pin Thin Quad Flat Pack Industrial CY7C09379V-12AC 51-85048 100-Pin Thin Quad Flat Pack Commercial 12 CY7C09379V-12AXC 100-Pin Thin Quad Flat Pack (Pb-Free) CY7C09379V-12AXCT 100-Pin Thin Quad Flat Pack (Pb-Free) 64K x18 3.3V Synchronous Dual-Port SRAM Speed (ns) 6.5[1, 2] Ordering Code CY7C09389V-6AC Package Diagram Package Type 51-85048 100-Pin Thin Quad Flat Pack CY7C09389V-6AXC 7.5 [2] CY7C09389V-7AC CY7C09389V-9AC 51-85048 51-85048 CY7C09389V-12AC CY7C09389V-12AXC Document #: 38-06056 Rev. *C Commercial 100-Pin Thin Quad Flat Pack Commercial 100-Pin Thin Quad Flat Pack (Pb-Free) 51-85048 CY7C09389V-9AXI 12 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack (Pb-Free) CY7C09389V-9AXC CY7C09389V-9AI Commercial 100-Pin Thin Quad Flat Pack (Pb-Free) CY7C09389V-7AXC 9 Operating Range 100-Pin Thin Quad Flat Pack Industrial 100-Pin Thin Quad Flat Pack (Pb-Free) 51-85048 100-Pin Thin Quad Flat Pack Commercial 100-Pin Thin Quad Flat Pack (Pb-Free) Page 17 of 19 [+] Feedback CY7C09269V/79V/89V CY7C09369V/79V/89V Package Diagrams Figure 17. 100-Pin Thin Plastic Quad Flat Pack (TQFP), 51-85048 51-85048 *C Document #: 38-06056 Rev. *C Page 18 of 19 [+] Feedback CY7C09269V/79V/89V CY7C09369V/79V/89V Document History Page Document Title: CY7C09269V/79V/89V CY7C09369V/79V/89V 3.3V 16K/32K/64K x 16/18 Synchronous Dual-Port Static RAM Document Number: 38-06056 Revision ECN Submission Date Orig. of Change ** 110215 12/18/01 SZV Change from Spec number: 38-00668 to 38-06056 *A 122306 12/27/02 RBI Power up requirements added to Maximum Ratings Information PCX Added Pb-Free Part Ordering Information *B 344354 See ECN *C 2678221 03/25/2009 Description of Change VKN/AESA Added CY7C09379V-12AXCT part. Updated 51-85048 to *C. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers PSoC Solutions psoc.cypress.com clocks.cypress.com General Low Power/Low Voltage psoc.cypress.com/solutions psoc.cypress.com/low-power Wireless wireless.cypress.com Precision Analog Memories memory.cypress.com LCD Drive psoc.cypress.com/lcd-drive image.cypress.com CAN 2.0b psoc.cypress.com/can USB psoc.cypress.com/usb Image Sensors psoc.cypress.com/precision-analog © Cypress Semiconductor Corporation, 2001-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. 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Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-06056 Rev. *C Revised March 25, 2009 Page 19 of 19 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback