CY7C09569V CY7C09579V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3 V 16 K / 32 K × 36 FLEx36®
Synchronous Dual-Port Static RAM
CY7C09569V
CY7C09579V
®
3.3 V 16 K / 32 K × 36 FLEx36
Synchronous Dual-Port Static RAM
3.3 V 16 K / 32 K × 36 FLEx36® Synchronous Dual-Port Static RAM
Features
Functional Description
■
True dual-ported memory cells which allow simultaneous
access of the same memory location
■
Two flow-through/pipelined devices
❐ 16 K × 36 organization (CY7C09569V)
❐ 32 K × 36 organization (CY7C09579V)
■
0.25-micron CMOS for optimum speed/power
■
Three modes
❐ Flow-through
❐ Pipelined
❐ Burst
■
Bus-matching capabilities on right port (× 36 to × 18 or × 9)
■
Byte-select capabilities on left port
■
100-MHz pipelined operation
■
High-speed clock to data access 5/6 ns
■
3.3 V low operating power
❐ Active = 250 mA (typical)
❐ Standby = 10 A (typical)
The CY7C09569V and CY7C09579V are high-speed 3.3 V
synchronous CMOS 16 K and 32 K × 36 dual-port static RAMs.
Two ports are provided, permitting independent, simultaneous
access for reads and writes to any location in memory. Registers
on control, address, and data lines allow for minimal set-up and
hold times. In pipelined output mode, data is registered for
decreased cycle time. Clock to data valid tCD2 = 5 ns (pipelined).
Flow-through mode can also be used to bypass the pipelined
output register to eliminate access latency. In flow-through mode
data will be available tCD1 = 12.5 ns after the address is clocked
into the device. Pipelined output or flow-through mode is
selected via the FT/Pipe pin.
Each port contains a burst counter on the input address register.
The internal write pulse width is independent of the external R/W
LOW duration. The internal write pulse is self-timed to allow the
shortest possible cycle times.
A HIGH on CE for one clock cycle will power down the internal
circuitry to reduce the static power consumption. In the pipelined
mode, one cycle is required with CE LOW to reactivate the
outputs.
■
Fully synchronous interface for ease of use
■
Burst counters increment addresses internally
❐ Shorten cycle times
❐ Minimize bus noise
❐ Supported in flow-through and pipelined modes
■
Counter address read back via I/O lines
■
Single chip enable
■
Automatic power-down
■
Commercial and industrial temperature ranges
■
Compact package
❐ 144-pin TQFP (20 × 20 × 1.4 mm)
❐ 144-pin Pb-free TQFP (20 × 20 × 1.4 mm)
❐ 172-ball BGA (1.0-mm pitch) (15 × 15 × 0.51 mm)
Counter Enable Inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS). When the port’s Count Enable (CNTEN) is asserted, the
address counter will increment on each LOW-to-HIGH transition
of that port’s clock signal. This will read/write one word from/into
each successive address location until CNTEN is deasserted.
The counter can address the entire memory array and will loop
back to the start. Counter Reset (CNTRST) is used to reset the
burst counter.
Parts are available in 144-pin Thin Quad Plastic Flatpack
(TQFP), 144-pin Pb-free Thin Quad Plastic Flatpack (TQFP) and
172-ball Ball Grid Array (BGA) packages.
Selection Guide
CY7C09569V / CY7C09579V
Description
fMAX2 (pipelined)
Maximum access time (clock to data, pipelined)
-100
-83
100
83
Unit
MHz
5
6
ns
Typical operating current ICC
250
240
mA
Typical standby current for ISB1 (both ports TTL level)
30
25
mA
Typical standby current for ISB3 (both ports CMOS level)
10
10
A
Cypress Semiconductor Corporation
Document Number: 38-06054 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 20, 2012
CY7C09569V
CY7C09579V
Logic Block Diagram
R/WL
R/WR
OEL
Left
Port
Control
Logic
B0–B3
CEL
OER
Right
Port
Control
Logic
FT/PipeL
CER
FT/PipeR
BE
9
I/O0L–I/O8L
9
I/O9L–I/O17L
9
I/O18L–I/O26L
I/O
Control
9
I/O
Control
9
I/O27L–I/O35L
A0–A13/14L[1]
CLKL
ADSL
CNTENL
CNTRSTL
9
9
Bus
Match
9/18/36
9
BM
SIZE
14/15
14/15
Counter/
Address
Register
Decode
I/OR
True Dual-Ported
RAM Array
Counter/
Address
Register
Decode
[1]
A0–A13/14R
CLKR
ADSR
CNTENR
CNTRSTR
Note
1. A0–A13 for 16K; A0–A14 for 32 K devices.
Document Number: 38-06054 Rev. *G
Page 2 of 33
CY7C09569V
CY7C09579V
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 6
Maximum Ratings ............................................................. 7
Operating Range ............................................................... 7
Electrical Characteristics ................................................. 7
Capacitance ...................................................................... 7
AC Test Load and Waveforms ......................................... 8
Switching Characteristics ................................................ 9
Switching Waveforms .................................................... 11
Read/Write and Enable Operation ................................. 24
Address Counter Control Operation ............................. 24
Right Port Configuration ................................................ 25
Right Port Operation ...................................................... 25
Readout of Internal Address Counter ........................... 25
Left Port Operation ......................................................... 25
Counter Operation .......................................................... 26
Document Number: 38-06054 Rev. *G
Bus Match Operation ..................................................... 26
Long-Word (36-bit) Operation ................................... 26
Word (18-bit) Operation ............................................. 27
Byte (9-bit) Operation ................................................ 27
Ordering Information ...................................................... 28
16 K × 36 3.3 V Synchronous Dual-Port SRAM ........ 28
32K × 36 3.3 V Synchronous Dual-Port SRAM ......... 28
Ordering Code Definitions ......................................... 28
Package Diagrams .......................................................... 29
Acronyms ........................................................................ 31
Document Conventions ................................................. 31
Units of Measure ....................................................... 31
Document History Page ................................................. 32
Sales, Solutions, and Legal Information ...................... 33
Worldwide Sales and Design Support ....................... 33
Products .................................................................... 33
PSoC Solutions ......................................................... 33
Page 3 of 33
CY7C09569V
CY7C09579V
Pin Configurations
I/O33L
I/O34L
I/O35L
A0L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
B0
B1
B2
B3
OEL
R/WL
VDD
VSS
VSS
CEL
CLKL
ADSL
CNTRSTL
CNTENL
FT/PIPEL
A8L
CY7C09569V (16 K × 36)
CY7C09579V (32 K × 36)
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
I/O33R
I/O34R
I/O35R
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
BM
SIZE
BE
vss
OER
R/WR
VDD
VSS
VSS
CER
CLKR
ADSR
CNTRSTR
CNTENR
FT/PIPER
A8R
A9R
A10R
A11R
A12R
A13R
NC[3]
I/O26R
I/O25R
I/O24R
I/O8R
VDD
I/O18R
I/O19R
I/O20R
I/O21R
VSS
I/O22R
I/O23R
I/O5R
I/O6R
I/O7R
I/O0L
I/O0R
I/O1R
I/O2R
I/O3R
I/O4R
VSS
I/O5L
VSS
I/O4L
I/O3L
I/O2L
I/O1L
I/O19L
I/O18L
VDD
I/O8L
I/O7L
I/O6L
I/O21L
I/O20L
I/O23L
I/O22L
VSS
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
A9L
A10L
A11L
A12L
A13L
NC [2]
I/O26L
I/O25L
I/O24L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
I/O32L
I/O31L
VSS
I/O30L
I/O29L
I/O28L
I/O27L
VDD
I/O17L
I/O16L
I/O15L
I/O14L
VSS
I/O13L
I/O12L
I/O11L
I/O10L
I/O9L
I/O9R
I/O10R
I/O11R
I/O12R
I/O13R
VSS
I/O14R
I/O15R
I/O16R
I/O17R
VDD
I/O27R
I/O28R
I/O29R
I/O30R
VSS
I/O31R
I/O32R
Figure 1. 144-pin TQFP (20 × 20 × 1.4 mm) pinout (Top View)
Notes
2. This pin is A14L for CY7C09579V.
3. This pin is A14R for CY7C09579V.
Document Number: 38-06054 Rev. *G
Page 4 of 33
CY7C09569V
CY7C09579V
Pin Configurations
Figure 2. 172-ball BGA (15 × 15 × 1.25 mm) pinout (Top View)
1
2
3
4
5
6
A
I/O32L
I/O30L
NC
VSS
I/O13L
VDD
B
A0L
I/O33L
I/O29
I/O17L
C
NC
A1L
I/O31L
I/O27L
D
A2L
A3L
I/O35L
I/O34L
E
A4L
A5L
NC
B0L
NC
NC
I/O14L I/O12L
NC
F
VDD
A6L
A7L
B1L
OEL
B2L
B3L
CEL
H
VSS
R/WL
A8L
CLKL
J
A9L
A10L
VSS
ADSL
K
A11L
A12L
NC
CNTRSTL
L
FT/PIPEL
A13L
CNTENL
I/O26L
M
NC
NC[4]
I/O22L
I/O18L
NC
N
I/O24L
I/O20L
I/O8L
I/O6L
P
I/O23L
I/O21L
NC
VSS
8
I/O9L
9
10
11
12
13
14
VDD
I/O13R
VSS
NC
I/O30R
I/O32R
I/O17R
I/O29R
I/O33R
A0R
I/O27R
I/O31R
A1R
NC
I/O9R I/O12R I/O14R
I/O15L I/O10L I/O10R I/O15R
I/O28L I/O16L
G
7
I/O11L I/O11R
VSS
VSS
NC
I/O16R I/O28R
NC
NC
NC
NC
I/O25L I/O19L
NC
NC
I/O34R
I/O35R
A3R
A2R
NC
BM
NC
A5R
A4R
NC
SIZE
A7R
A6R
VDD
CER
VSS
BE
OER
CLKR
A8R
R/WR
VSS
NC
ADSR
VSS
A10R
A9R
NC
A12R
A11R
CNTRSTR
NC
I/O19R I/O25R
I/O26R
CNTENR
I/O2R
I/O7R
NC
I/O18R
I/O22R
NC[5]
NC
I/O0L
I/O0R
I/3R
I/O5R
I/O6R
I/O8R
I/O20R
I/O24R
I/O1L
I/O1R
VDD
I/O4R
VSS
NC
I/O21R
I/O23R
VSS
VSS
I/O7L
I/O2L
I/O5L
I/O3L
I/O4L
VDD
A13R FT/PIPER
Notes
4. This pin is A14L for CY7C09579V.
5. This pin is A14R for CY7C09579V.
Document Number: 38-06054 Rev. *G
Page 5 of 33
CY7C09569V
CY7C09579V
Pin Definitions
Left Port
Right Port
A0L–A13/14L
A0R–A13/14R
Address Inputs (A0–A13 for 16 K, A0–A14 for 32 K devices).
Description
ADSL
ADSR
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to assert
the part using the externally supplied address on Address Pins. To load this address into the Burst
Address Counter both ADS and CNTEN have to be LOW. ADS is disabled if CNTRST is asserted
LOW.
CEL
CER
Chip Enable Input.
CLKL
CLKR
Clock Signal. This input can be free-running or strobed. Maximum clock input rate is fMAX.
CNTENL
CNTENR
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if CNTRST is asserted LOW.
CNTRSTL
CNTRSTR
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective
port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
I/O0L–I/O35L
I/O0R–I/O35R Data Bus Input/Output
OEL
OER
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read
operations.
R/WL
R/WR
Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For
read operations, assert this pin HIGH.
FT/PIPEL
FT/PIPER
Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW. For
pipelined mode operation, assert this pin HIGH.
B0L–B3L
–
Byte Select Inputs. Asserting these signals enable read and write operations to the corresponding
bytes of the memory array.
–
BM, SIZE
Select Pins for Bus Matching. See Bus Matching for details.
–
BE
Big Endian Pin. See Bus Matching for details.
VSS
Ground Input.
VDD
Power Input.
Document Number: 38-06054 Rev. *G
Page 6 of 33
CY7C09569V
CY7C09579V
DC input voltage .............................. –0.5 V to VDD + 0.5 V[7]
Maximum Ratings
Exceeding maximum ratings[6] may shorten the useful life of the
device. User guidelines are not tested.
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage .......................................... > 2001 V
Storage temperature ................................ –65 °C to +150 °C
Latch-up current .................................................... > 200 mA
Ambient temperature with
power applied .......................................... –55 °C to +125 °C
Operating Range
Range
Supply voltage to ground potential ..............–0.5 V to +4.6 V
Ambient Temperature
VDD
0 °C to +70 °C
3.3 V 165 mV
Commercial
DC voltage applied to
outputs in High Z state ........................ –0.5 V to VDD + 0.5 V
Electrical Characteristics
Over the Operating Range
CY7C09569V / CY7C09579V
Parameter
Description
-100
-83
Unit
Min
Typ
Max
Min
Typ
Max
VOH
Output HIGH Voltage
(VDD = Min., IOH = –4.0 mA)
2.4
–
–
2.4
–
–
V
VOL
Output LOW Voltage
(VDD = Min., IOL= +4.0 mA)
–
–
0.4
–
–
0.4
V
VIH
Input HIGH Voltage
2.0
–
–
2.0
–
–
V
VIL
Input LOW Voltage
–
–
0.8
–
–
0.8
V
IOZ
Output Leakage Current
–10
–
10
–10
–
10
A
ICC
Operating Current
(VDD = Max., IOUT = 0 mA)
Outputs Disabled
–
250
385
–
240
360
mA
ISB1
Standby Current (Both Ports TTL Level)
CEL & CER VIH, f = fMAX
–
30
75
–
25
70
mA
ISB2
Standby Current (One Port TTL Level)
CEL | CER VIH, f = fMAX
–
170
220
–
160
210
mA
ISB3
Standby Current
(Both Ports CMOS Level)
CEL & CER VDD – 0.2 V, f = 0
–
0.01
1
–
0.01
1
mA
ISB4
Standby Current
(One Port CMOS Level)
CEL | CER VIH, f = fMAX
–
150
200
–
140
190
mA
Capacitance
Parameter
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VDD = 3.3 V
Max
Unit
10
pF
10
pF
Notes
6. The voltage on any input or I/O pin can not exceed the power pin during power-up.
7. Pulse width < 20 ns.
Document Number: 38-06054 Rev. *G
Page 7 of 33
CY7C09569V
CY7C09579V
AC Test Load and Waveforms
Figure 3. AC Test Load and Waveforms
Output
3.3 V
Z0 = 50 R = 50
R1 = 590
C [8]
Output
VTH = 1.5 V
C = 5 pF
(b) Three-State Delay (Load 2)
(a) Normal Load (Load 1)
3.0 V
10%
VSS
All Input Pulses
R2 = 435
90%
10%
90%
3 ns
3 ns
7
6
for tCD2 (ns)
5
4
3
2
1
20[9] 30
60
80 100
200
Capacitance (pF)
(b) Load Derating Curve
Notes
8. External AC Test Load Capacitance = 10 pF.
9. (Internal I/O pad Capacitance = 10 pF + AC Test Load.
Document Number: 38-06054 Rev. *G
Page 8 of 33
CY7C09569V
CY7C09579V
Switching Characteristics
Over the Operating Range
CY7C09569V/CY7C09579V
Parameter
Description
-100
-83
Unit
Min
Max
Min
Max
–
67
–
45
MHz
fMax Pipelined
–
100
–
83
MHz
Clock Cycle Time – Flow-Through
15
–
22
–
ns
Clock Cycle Time – Pipelined
10
–
12
–
ns
Clock HIGH Time – Flow-Through
6.5
–
7.5
–
ns
tCL1
Clock LOW Time – Flow-Through
6.5
–
7.5
–
ns
tCH2
Clock HIGH Time – Pipelined
4
–
5
–
ns
tCL2
Clock LOW Time – Pipelined
4
–
5
–
ns
tR
Clock Rise Time
–
3
–
3
ns
tF
Clock Fall Time
–
3
–
3
ns
tSA
Address Set-Up Time
3.5
–
4
–
ns
tHA
Address Hold Time
0.5
–
0.5
–
ns
tSB
Byte Select Set-Up Time
3.5
–
4
–
ns
tHB
Byte Select Hold Time
0.5
–
0.5
–
ns
tSC
Chip Enable Set-Up Time
3.5
–
4
–
ns
tHC
Chip Enable Hold Time
0.5
–
0.5
–
ns
tSW
R/W Set-Up Time
3.5
–
4
–
ns
tHW
R/W Hold Time
0.5
–
0.5
–
ns
tSD
Input Data Set-Up Time
3.5
–
4
–
ns
tHD
Input Data Hold Time
0.5
–
0.5
–
ns
tSAD
ADS Set-Up Time
3.5
–
4
–
ns
tHAD
ADS Hold Time
0.5
–
0.5
–
ns
tSCN
CNTEN Set-Up Time
3.5
–
4
–
ns
tHCN
CNTEN Hold Time
0.5
–
0.5
–
ns
tSRST
CNTRST Set-Up Time
3.5
–
4
–
ns
tHRST
CNTRST Hold Time
0.5
–
0.5
–
ns
tOE
Output Enable to Data Valid
–
8
–
9
ns
fMAX1
fMax Flow-Through
fMAX2
tCYC1
tCYC2
tCH1
[10, 11]
OE to Low Z
2
–
2
–
ns
tOHZ[10, 11]
OE to High Z
1
7
1
7
ns
tCD1
Clock to Data Valid – Flow-Through
–
12.5
–
18
ns
tCD2
Clock to Data Valid – Pipelined
–
5
–
6
ns
tCA1
Clock to Counter Address Valid – Flow-Through
–
12.5
–
18
ns
tCA2
Clock to Counter Address Valid – Pipelined
–
9
–
10
ns
tDC
Data Output Hold After Clock HIGH
2
–
2
–
ns
tCKHZ[10, 11]
Clock HIGH to Output High Z
2
6
2
7
ns
tCKLZ[10, 11]
Clock HIGH to Output Low Z
2
–
2
–
ns
tOLZ
Notes
10. This parameter is guaranteed by design, but it is not production tested.
11. Test conditions used are Load 2.
Document Number: 38-06054 Rev. *G
Page 9 of 33
CY7C09569V
CY7C09579V
Switching Characteristics (continued)
Over the Operating Range
CY7C09569V/CY7C09579V
Parameter
Description
-100
-83
Unit
Min
Max
Min
Max
Port to Port Delays
tCWDD
Write Port Clock HIGH to Read Data Delay
–
30
–
35
ns
tCCS
Clock to Clock Set-Up Time
–
9
–
10
ns
Document Number: 38-06054 Rev. *G
Page 10 of 33
CY7C09569V
CY7C09579V
Switching Waveforms
Figure 4. Read Cycle for Flow-Through Output (FT/PIPE = VIL) [12, 13, 14, 15]
tCH1
tCYC1
tCL1
CLK
CE
tSC
tHC
tSW
tSA
tHW
tHA
tSB
tSC
tHB
tHC
B0-3
R/W
An
Address
An+1
An+2
An+3
tCKHZ
tDC
tCD1
DataOUT
Qn
Qn+1
tCKLZ
Qn+2
tDC
tOHZ
tOLZ
OE
tOE
Figure 5. Read Cycle for Pipelined Operation (FT/PIPE = VIH) [12, 13, 14, 15]
tCH2
tCYC2
tCL2
CLK
CE
tSC
tHC
tSW
tSA
tHW
tHA
tSB
tSC
tHB
tHC
B0-3
R/W
Address
DataOUT
An
An+1
1 Latency
An+2
tDC
tCD2
Qn
tCKLZ
An+3
Qn+1
tOHZ
Qn+2
tOLZ
OE
tOE
Notes
12. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
13. ADS = VIL, CNTEN = VIL and CNTRST = VIH.
14. The output is disabled (high-impedance state) by CE=VIH following the next rising edge of the clock.
15. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
Document Number: 38-06054 Rev. *G
Page 11 of 33
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Figure 6. Bus Match Read Cycle for Flow-Through Output (FT/PIPE = VIL) [16, 17, 18, 19, 20]
tCYC1
tCH1
tCL1
CLK
CE
tSC
tHC
tSW
tSA
tHW
tHA
ADS
R/W
An
Address
An
An+1
tDC
tCD1
DataOUT
Qn
Qn
1st
Cycle
tCKLZ
OE
An+1
2nd
Cycle
Qn+1
Qn+1
1st
Cycle
2nd
Cycle
tDC
LOW
Figure 7. Bus Match Read Cycle for Pipelined Operation (FT/PIPE = VIH) [16, 17, 18, 19, 20]
tCYC2
tCH2
tCL2
CLK
CE
tHC
tSC
R/W
tSW tHW
ADS
Address
An+1
An
An
tSA tHA
tCD2
tCD2
tCD2
tCLKZ
DataOUT
Qn
Qn
1 Latency
OE
An+1
LOW
tDC
1st Cycle
Qn+1
tDC
2nd Cycle
tDC
1st Cycle
Notes
16. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
17. The output is disabled (high-impedance state) by CE=VIH following the next rising edge of the clock.
18. Timing shown is for x18 bus matching; x9 bus matching is similar with 4 cycles between address inputs.
19. See table “Right Port Operation“ for data output on first and subsequent cycles.
20. CNTEN = VIL. In x9 and x18 Bus Matching Burst Mode operations (Write or Read), ADS can toggle on the rising edge of every clock cycle or it can be at VIH level all
the time except when loading the initial external address (i.e. ADS = VIL only required when reading or writing the first Byte or Word).
Document Number: 38-06054 Rev. *G
Page 12 of 33
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Figure 8. Bank Select Pipelined Read [21, 22]
tCH2
tCYC2
tCL2
CLKL
tHA
tSA
Address(B1)
A0
A1
A3
A2
A4
A5
tHC
tSC
CE(B1)
tCD2
tHC
tSC
tCD2
tHA
tSA
tDC
A0
Address(B2)
A1
tDC
tSC
tCKLZ
A3
A2
tCKHZ
Q3
Q1
Q0
DataOUT(B1)
tCD2
tCKHZ
A4
A5
tHC
CE(B2)
tSC
tCD2
tHC
DataOUT(B2)
tCKHZ
Q4
Q2
tCKLZ
Figure 9. Left Port Write to Flow-Through Right Port Read
CLKL
tCD2
tSW
tHW
tSA
tHA
tCKLZ
[22, 23, 24, 25, 26]
R/WL
AddressL
No
Match
Match
tHD
tSD
DataINL
Valid
tCCS
CLKR
R/WR
AddressR
tCD1
tSW
tSA
tHW
tHA
No
Match
Match
tCWDD
DataOUTR
tCD1
Valid
tDC
Valid
tDC
Notes
21. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this data sheet.
ADDRESS(B1) = ADDRESS(B2).
22. B0 = B1 = B2 = B3 = BM = SIZE = ADS = CNTEN = VIL, CNTRST = VIH.
23. The same waveforms apply for a right port write to flow-through left port read.
24. CE = B0 = B1 = B2 = B3 = ADS = CNTEN=VIL; CNTRST= VIH.
25. OE = VIL for the right port, which is being read from. OE = VIH for the left port, which is being written to.
26. If tCCS maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS > maximum specified, then data is not valid
until tCCS + tCD1 (tCWDD does not apply in this case).
Document Number: 38-06054 Rev. *G
Page 13 of 33
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Figure 10. Pipelined Read-to-Write-to-Read (OE = VIL) [27, 28, 29, 30]
tCH2
tCYC2
tCL2
CLK
CE
tSC
tHC
tSW
tHW
R/W
tSW
tHW
An
Address
tSA
An+1
An+2
An+2
tHA
DataIN
An+3
An+4
tSD tHD
tCD2
tCKHZ
Dn+2
tCD2
tCKLZ
Qn
DataOUT
Read
Qn+3
No Operation
Write
Read
Notes
27. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
28. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals.
29. CE = ADS = CNTEN = VIL; CNTRST = VIH.
30. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
Document Number: 38-06054 Rev. *G
Page 14 of 33
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Figure 11. Pipelined Read-to-Write-to-Read (OE Controlled) [31, 32, 33, 34]
tCH2
tCYC2
tCL2
CLK
CE
tSC
tHC
tSW tHW
R/W
Address
tSW
tHW
An
tSA
An+1
An+2
tHA
An+3
An+4
An+5
tSD tHD
Dn+2
DataIN
Dn+3
tCD2
DataOUT
tCKLZ
tCD2
Qn
Qn+4
tOHZ
OE
Read
Write
Read
Notes
31. Test conditions used are Load 2.
32. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals.
33. CE = ADS = CNTEN = VIL; CNTRST = VIH.
34. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
Document Number: 38-06054 Rev. *G
Page 15 of 33
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Figure 12. Bus Match Pipelined Read-to-Write-to-Read (OE = VIL) [35, 36, 37, 38, 39, 40, 41]
tCYC2
CLK
tCH2 tCL2
CE
tSC
tHC
tSW
tHW
R/W
Address
tSA
An+1
An
An
An+2
An+1
An+3
An+2
An+4
An+3
An+4
tHA
ADS
1st Word
Qn
Qn
DataOUT
tCD2
tCKLZ
2nd Word
tCD2
Read
1st Cycle
Read
2nd Cycle
2nd Word
Qn+3
Qn+3
tCKHZ
1st Word
2nd Word
Dn+2
Dn+2
DataIN
Read
1st Word
tSD
tHD
No
Operation
1st Cycle
Write
Write
2nd Cycle
tCD2
Read
Read
1st Cycle
tDC
Read
2nd Cycle
Notes
35. Test conditions used are Load 2.
36. Timing shown is for x18 bus matching; x9 bus matching is similar with 4 cycles between address inputs.
37. See table “Right Port Operation“ for data output on first and subsequent cycles.
38. CNTEN = VIL. In x9 and x18 Bus Matching Burst Mode operations (Write or Read), ADS can toggle on the rising edge of every clock cycle or it can be at VIH level all
the time except when loading the initial external address (i.e. ADS = VIL only required when reading or writing the first Byte or Word).
39. CE = ADS = CNTEN = VIL; CNTRST = VIH.
40. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
41. BM, SIZE, and BE must be reconfigured 1 cycle before operation is guaranteed. BM, SIZE, and BE should remain static for any particular port configuration.
Document Number: 38-06054 Rev. *G
Page 16 of 33
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Figure 13. Flow-Through Read-to-Write-to-Read (OE = VIL) [42, 43, 44, 45, 46, 47]
tCH1
tCYC1
tCL1
CLK
CE
tSW
tHW
R/W
tSW
tHW
An
Address
An+1
tSA
DataIN
An+2
An+2
tSD
tHA
An+3
tHD
Dn+2
tCD1
tCD1
DataOUT
An+4
tCD1
Qn
tCD1
Qn+1
tDC
tCKHZ
Read
Qn+3
tCKLZ
No
Operation
Write
tDC
Read
Figure 14. Flow-Through Read-to-Write-to-Read (OE Controlled) [42, 43, 46, 47, 48]
tCH1
tCYC1
tCL1
CLK
CE
tSW
tHW
R/W
tSW
tHW
An
Address
tSA
DataIN
An+1
tSD
tHA
An+3
An+4
An+5
tHD
Dn+2
tDC
tCD1
DataOUT
An+2
Dn+3
tOE
tCD1
Qn
tCD1
Qn+4
tOHZ
tCKLZ
tDC
OE
Read
Write
Read
Notes
42. ADS = VIL, CNTEN = VIL and CNTRST = VIH.
43. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
44. Timing shown is for x18 bus matching; x9 bus matching is similar with 4 cycles between address inputs.
45. See table “Right Port Operation“ for data output on first and subsequent cycles.
46. CE = ADS = CNTEN = VIL; CNTRST = VIH.
47. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
48. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals.
Document Number: 38-06054 Rev. *G
Page 17 of 33
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Figure 15. Bus Match Flow-Through Read-to-Write-to-Read (OE = VIL) [49, 50, 51, 52, 53, 54, 55]
tCYC1
tCH1 tCL1
CLK
tSC
tHC
CE
tSW tHW
tSW tHW
R/W
tSA
Address
tHA
An
An
An+1
An+1
An+1
An+1
An+2
An+1
ADS
tSD
DataIN
DataOUT
Dn+1
tCD1
tCKHZ
tDC
tCD1
Qn
Dn+1
1st Word
2nd Word
tCD1
2nd Word
Read
2nd Cycle
tCD1
Qn+1
Qn+1
Qn
1st Word
Read
1st Cycle
tHD
No
Operation
Write
1st Cycle
Write
2nd Cycle
tCKLZ
tDC
Read
1st Cycle
Read
2nd Cycle
Notes
49. Test conditions used are Load 2.
50. Timing shown is for x 18 bus matching; x 9 bus matching is similar with 4 cycles between address inputs.
51. See table “Right Port Operation“ for data output on first and subsequent cycles.
52. CNTEN = VIL. In x9 and x18 Bus Matching Burst Mode operations (Write or Read), ADS can toggle on the rising edge of every clock cycle or it can be at VIH level
all the time except when loading the initial external address (i.e. ADS = VIL only required when reading or writing the first Byte or Word).
53. CE = ADS = CNTEN = VIL; CNTRST = VIH.
54. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
55. BM, SIZE, and BE must be reconfigured 1 cycle before operation is guaranteed. BM, SIZE, and BE should remain static for any particular port configuration.
Document Number: 38-06054 Rev. *G
Page 18 of 33
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Figure 16. Pipelined Read with Address Counter Advance [56]
tCH2
tCYC2
tCL2
CLK
tSA
Address
tHA
An
tSAD
tHAD
ADS
tSAD
tHAD
tSCN
tHCN
CNTEN
tSCN
DataOUT
tHCN
Qx–1
tCD2
Qx
Read
External
Address
tDC
Qn
Read with Counter
Qn+1
Qn+2
Counter Hold
Qn+3
Read with Counter
Figure 17. Flow-Through Read with Address Counter Advance [56]
tCH1
tCYC1
tCL1
CLK
tSA
tHA
An
Address
tSAD
tHAD
ADS
tSAD
tHAD
tSCN
tHCN
CNTEN
tSCN
DataOUT
tHCN
tCD1
Qx
Qn
Qn+1
tDC
Read
External
Address
Qn+2
Counter Hold
Read with Counter
Qn+3
tDC
tCD1
Qn+4
Read tDC
with
tCD1
Counter
Note
56. CE = OE = VIL; R/W = CNTRST = VIH.
Document Number: 38-06054 Rev. *G
Page 19 of 33
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Figure 18. Write with Address Counter Advance (Flow-Through or Pipelined Outputs) [57, 58]
tCH2
tCYC2
tCL2
CLK
tSA
tHA
An
Address
Internal
Address
An
tSAD
tHAD
tSCN
tHCN
An+1
An+2
An+3
An+4
ADS
CNTEN
Dn
DataIN
tSD
Write External Address
Dn+1
Dn+1
Dn+2
Dn+3
Dn+4
tHD
Write with Counter
Write Counter Hold
Write with Counter
Notes
57. CE= B0 = B1 = B2 = B3 = R/W = VIL; CNTRST = VIH.
58. The “Internal Address” is equal to the “External Address” when ADS = CNTEN = VIL and CNTRST = VIH.
Document Number: 38-06054 Rev. *G
Page 20 of 33
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Figure 19. Counter Reset (Pipelined Outputs) [59, 60, 61, 62, 63]
tCYC2
tCH2 tCL2
CLK
tSA
Internal
Address
Ax
tSW
An
1
0
Ap
Am
An
Address
tHA
Ap
Am
tHW
R/W
ADS
CNTEN
tSRST tHRST
CNTRST
tSD tHD
DataIN
D0
tCD2
tCD2
[63]
DataOUT
Q0
Q1
Qn
tCKLZ
Counter Reset
Write Address 0 Read Address 0 Read Address 1
Read Address An
Read Address Am
Notes
59. Test conditions used are Load 2.
60. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals.
61. CE = B0 = B1 = B2 = B3 = VIL.
62. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset.
63. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals. Ideally, DATAOUT should be in the High-Impedance state during
a valid WRITE cycle.
Document Number: 38-06054 Rev. *G
Page 21 of 33
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Figure 20. Counter Reset (Flow-Through Outputs) [64, 65, 66, 67, 68]
tCH2
tCYC2
tCL2
CLK
tSA
An
Address
Internal
Address
tHA
AX
0
tSW
tHW
tSD
tHD
An+1
An
1
An+1
R/W
ADS
CNTEN
tSRST tHRST
CNTRST
D0
DataIN
tCD1
DataOUT
Q0
Counter Reset
Write Address 0
Read Address 0
Read Address 1
Q1
Qn
Read Address n
Notes
64. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals.
65. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
66. CE = B0 = B1 = B2 = B3 = VIL.
67. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset.
68. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals. Ideally, DATAOUT should be in the High-Impedance state during
a valid WRITE cycle.
Document Number: 38-06054 Rev. *G
Page 22 of 33
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Figure 21. Pipelined Read of State of Address Counter [69, 70, 71]
tCYC2
tCH2 tCL2
CLK
tSA tHA
Address
An
Internal
Address
An
An+2
An+1
tSAD tHAD
ADS
tSAD
tSCN tHCN
tHAD
CNTEN
tSCN tHCN
DataOUT
Qx-1
Qx-2
Load
External
Address
tSCN tHCN
tCA2
Qn
An
Qn+1
Read with
Counter
tDC
Read Counter Address
Counter
Hold
Figure 22. Flow-Through Read of State of Address Counter
Qn+2
Read With Counter
[69, 70, 72]
tCYC1
tCH1 tCL1
CLK
tSA tHA
Address
An
Internal
Address
An
An+1
An+3
An+2
tSAD tHAD
ADS
tSCN tHCN tSCN
tSAD
tHCN
tHAD
CNTEN
tCA1
DataOUT
Qn
Qx
Load
External
Address
tSCN
An
tDC
Read Counter Address
Qn+1
Read with
Counter
Qn+2
Counter
Hold
tHCN
Qn+3
Read with Counter
Notes
69. CE = OE = VIL; R/W = CNTRST = VIH.
70. When reading ADDRESSOUT in x 9 Bus Match mode, readout of AN is extended by 1 cycle.
71. For Pipelined address counter read, signals from address counter operation table from must be valid for 2 consecutive cycles for x 36 and x 18 mode and for 3
consecutive cycles for x 9 mode.
72. For flow-through address counter read, signals from address counter operation table must be valid for consecutive cycles for x 36.
Document Number: 38-06054 Rev. *G
Page 23 of 33
CY7C09569V
CY7C09579V
Read/Write and Enable Operation
The Read/Write and Enable Operation is described as follows. [73, 74, 75]
Inputs
OE
Operation
CE
R/W
I/O0–I/O35
X
H
X
High Z
X
L
L
DIN
L
L
H
DOUT
Read[76]
L
X
High Z
Outputs disabled
H
CLK
Outputs
X
Deselected [76]
Write
Address Counter Control Operation
The Address Counter Control Operation is described as follows. [73, 77]
Address
Previous
Address
X
CLK
OE
R/W
ADS
CNTEN
CNTRST
Mode
Operation
X
X
X
X
X
L
Reset
Counter reset
An
X
X
X
L
L
H
Load
Address load into counter
An
An
L
H
L
H
H
X
An
X
X
H
H
H
Hold
X
An
X
X
H
L
H
Increment
Hold + Read External address blocked –
counter address readout
External address blocked –
counter disabled
Counter increment
Notes
73. “X” = “Don’t Care,” “H” = VIH, “L” = VIL.
74. ADS, CNTEN, CNTRST = “Don’t Care.”
75. OE is an asynchronous input signal.
76. When CE changes state In the pipelined mode, deselection and read happen in the following clock cycle.
77. Counter operation is independent of CE.
Document Number: 38-06054 Rev. *G
Page 24 of 33
CY7C09569V
CY7C09579V
Right Port Configuration
The Right Port Configuration is described as follows. [78, 79]
BM
SIZE
Configuration
I/O Pins used
0
0
× 36
I/O0R–35R
1
0
× 18
I/O0R–17R
1
1
×9
I/O0R–8R
Right Port Operation
The Right Port Operation is described as follows. [80]
Configuration
BE
Data on 1st Cycle
Data on 2nd Cycle
Data on 3rd Cycle
Data on 4th Cycle
× 18
0
Q0R–17R
Q18R–35R
–
–
× 18
1
Q18R–35R
Q0R–17R
–
–
×9
0
Q0R–8R
Q9R–17R
Q18R–26R
Q27R–35R
×9
1
Q27R–35R
Q18R–26R
Q9R–17R
Q0R–8R
Readout of Internal Address Counter
The Readout of Internal Address Counter is described as follows. [81]
Configuration
Address on 1st Cycle
I/O Pins used on 1st Cycle
Address on 2nd Cycle I/O Pins used on 2nd Cycle
Left Port × 36
A0L–14L
I/O3L–17L
–
–
Right Port × 36
A0R–14R
I/O3R–17R
–
–
Right Port × 18
WA, A0R–14R
I/O2R–17R
–
–
Right Port × 9
A6R–14R
I/O0R–8R
BA, WA, A0R–5R
I/O1R–8R
Left Port Operation
The Left Port Operation is described as follows.
Control Pin
Effect
B0
I/O0–8 Byte Control
B1
I/O9–17 Byte Control
B2
I/O18–26 Byte Control
B3
I/O27–35 Byte Control
Notes
78. BM, SIZE, and BE must be reconfigured 1 cycle before operation is guaranteed. BM, SIZE, and BE should remain static for any particular port configuration.
79. In x36 mode, BE input is a “Don’t Care.”
80. DQ represents data output of the chip.
81. x18 and x9 configuration apply to right port only.
Document Number: 38-06054 Rev. *G
Page 25 of 33
CY7C09569V
CY7C09579V
The CY7C09569V/CY7C09579V Dual-Port RAM (DPRAM)
contains on-chip address counters (one for each port) for the
synchronous members of the product family. Besides the main
× 36 format, the right port allows bus matching (× 18 or × 9,
user-selectable). An internal sub-counter provides the extra
addresses required to sequence out the 36-bit word in 18-bit or
9-bit increments. The sub-counter counts up in the “Little Endian”
mode, and counts down if the user has chosen the “Big Endian”
mode. The address counter is required to be in increment mode
in order for the sub-counter to sequence out the second word (in
× 18 mode) or the remaining three bytes (in × 9 mode).
For a × 36 format (the only active format on the left port), each
address counter in the CY7C09579V uses addresses (A0–14).
For the right port (allowing for the bus-matching feature), a
maximum of two address bits (out of a 2-bit sub-counter) are
added.
1. ADSL/R (pin #23/86) is a port’s address strobe, allowing the
loading of that port's burst counters if the corresponding
CNTENL/R pin is active as well.
2. CNTENL/R (pin #25/84) is a port’s count enable, provided to
stall the operation of the address input and utilize the internal
address generated by the internal counter for fast interleaved
memory applications; when asserted, the address counter will
increment on each positive transition of that port's clock
signal.
3. CNTRSTL/R (pin #24/85) is a port's burst counter reset.
A new read-back (Hold+Read Mode) feature has been added,
which is different between the left and right port due to the bus
matching feature provided only for the right port. In read-back
mode the internal address of the counter will be read from the
data I/Os as shown in Figure 23.
Figure 23. Counter Operation Diagram
_______
ADS
______________
Address Read-Back
COUNTER
Address
CY7C09569V
CY7C09579V
RAM
ARRAY
CNTRST
____________
CNTEN
I/O’s
Bus Match Operation
long-word, 18-bit word, or 9-bit byte format for data I/O. The data
lines are divided into four lanes, each consisting of 9 bits
(byte-size data lines).
Figure 24. Bus Match Operation Diagram
BE
x36
/
CY7C09569V
CY7C09579V
16K/32Kx36
Dual Port
9
/
9
/
9
/
9
/
BUS MODE
Counter Operation
x9, x18, x36
/
BM SIZE
The Bus Match Select (BM) pin works with Bus Size Select
(SIZE) and Big Endian Select (BE) to select the bus width
(long-word, word, or byte) and data sequencing arrangement for
the right port of the dual-port device. A logic LOW applied to both
the Bus Match Select (BM) pin and to the Bus Size Select (SIZE)
pin will select long-word (36-bit) operation. A logic HIGH level
applied to the Bus Match Select (BM) pin will enable whether
byte or word bus width operation on the right port I/Os depending
on the logic level applied to the SIZE pin. The level of Bus Match
Select (BM) must be static throughout normal device operation.
The Bus Size Select (SIZE) pin selects either a byte or word data
arrangement on the right port when the Bus Match Select (BM)
pin is HIGH. A logic HIGH on the SIZE pin when the BM pin is
HIGH selects a byte bus (9-bit) data arrangement. A logic LOW
on the SIZE pin when the BM pin is HIGH selects a word bus
(18-bit) data arrangement. The level of the Bus Size Select
(SIZE) must also be static throughout normal device operation.
The Big Endian Select (BE) pin is a multiple-function pin during
word or byte bus selection (BM = 1). BE is used in Big Endian
Select mode to determine the order by which bytes (or words) of
data are transferred through the right data port. A logic LOW on
the BE pin will select Little Endian data sequencing arrangement
and a logic HIGH on the BE pin will select a Big Endian data
sequencing arrangement. Under these circumstances, the level
on the BE pin should be static throughout dual-port operation.
Long-Word (36-bit) Operation
Bus Match Select (BM) and Bus Size Select (SIZE) set to a logic
LOW will enable standard cycle long-word (36-bit) operation. In
this mode, the right port’s I/O operates essentially in an identical
fashion to the left port of the dual-port SRAM. However no Byte
Select control is available. All 36 bits of the long-word are shifted
into and out of the right port’s I/O buffer stages. All read and write
timing parameters may be identical with respect to the two data
ports. When the right port is configured for a long-word size, BigEndian Select (BE) pin has no application and their inputs are
“Don’t Care”[82] for the external user.
The
right
port
of
the
CY7C09569V/CY7C09579V
16 K / 32 K × 36 dual-port SRAM can be configured in a 36-bit
Note
82. Even though a logic level applied to a “Don’t Care” input will not change the logical operation of the dual-port, inputs that are temporarily a “Don’t Care” (along with
unused inputs) must not be allowed to float. They must be forced either HIGH or LOW.
Document Number: 38-06054 Rev. *G
Page 26 of 33
CY7C09569V
CY7C09579V
Word (18-bit) Operation
Byte (9-bit) Operation
Word (18-bit) bus sizing operation is enabled when Bus Match
Select (BM) is set to a logic HIGH and the Bus Size Select (SIZE)
pin is set to a logic LOW. In this mode, 18 bits of data are ported
through I/O0R–17R. The level applied to the Big Endian (BE) pin
determines the right port data I/O sequencing order (Big Endian
or Little Endian).
Byte (9-bit) bus sizing operation is enabled when Bus Match
Select (BM) is set to a logic HIGH and the Bus Size Select (SIZE)
pin is set to a logic HIGH. In this mode, 9 bits of data are ported
through I/O0R–8R.
During word (18-bit) bus size operation, a logic LOW applied to
the BE pin will select Little Endian operation. In this case, the
least significant data word is read from the right port first or
written to the right port first. A logic HIGH on the BE pin during
word (18-bit) bus size operation will select Big Endian operation
resulting in the most significant data word being transferred
through the right port first. Internally, the data will be stored in the
appropriate 36-bit LSB or MSB I/O memory location. Device
operation requires a minimum of two clock cycles to read or write
during word (18-bit) bus size operation. An internal sub-counter
automatically increments the right port multiplexer control when
Little or Big Endian operation is in effect.
Document Number: 38-06054 Rev. *G
Big Endian and Little Endian data sequencing is available for
dual-port operation. The level applied to the Big Endian pin (BE)
under these circumstances will determine the right port data I/O
sequencing order (Big or Little Endian). A logic LOW applied to
the BE pin during byte (9-bit) bus size operation will select Little
Endian operation. In this case, the least significant data byte is
read from the right port first or written to the right port first. A logic
HIGH on the BE pin during byte (9-bit) bus size operation will
select Big Endian operation resulting in the most significant data
word to be transferred through the right port first. Internally, the
data will be stored in the appropriate 36-bit LSB or MSB I/O
memory location. Device operation requires a minimum of four
clock cycles to read or write during byte (9-bit) bus size
operation. An internal sub-counter automatically increments the
right port multiplexer control when Little or Big Endian operation
is in effect. When transferring data in byte (9-bit) bus match
format, the unused I/O pins (I/O9R–35R) are three-stated.
Page 27 of 33
CY7C09569V
CY7C09579V
Ordering Information
16 K × 36 3.3 V Synchronous Dual-Port SRAM
Speed
(MHz)
100
Ordering Code
Package
Name
CY7C09569V-100AXC
A144
CY7C09569V-100BBC
BB172
Package Type
144-pin TQFP (Pb-free)
Operating
Range
Commercial
172-ball BGA
32K × 36 3.3 V Synchronous Dual-Port SRAM
Speed
(MHz)
100
83
Ordering Code
Package
Name
Package Type
CY7C09579V-100AC
A144
144-pin TQFP
CY7C09579V-100AXC
A144
144-pin TQFP (Pb-free)
CY7C09579V-100BBC
BB172
172-ball BGA
CY7C09579V-83AC
A144
144-pin TQFP
CY7C09579V-83AXC
A144
144-pin TQFP (Pb-free)
CY7C09579V-83BBC
BB172
Operating
Range
Commercial
Commercial
172-ball BGA
Ordering Code Definitions
CY 7
C
09
5
X9 V - XXX X X
X
Temperature Range:
C = Commercial
X = Pb-free (RoHS Compliant)
Package Type: X = A or BB
A = 144-pin TQFP
BB = 172-ball BGA
Speed Grade: XXX = 83 MHz or 100 MHz
V = 3.3 V
Depth: X9, where X = 6 or 7
6 = 16K; 7 = 32K
5 = Width: × 36
09 = Sync
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress Device
Document Number: 38-06054 Rev. *G
Page 28 of 33
CY7C09569V
CY7C09579V
Package Diagrams
Figure 25. 144-pin TQFP (20 × 20 × 1.4 mm) A144SA Package Outline, 51-85047
51-85047 *D
Document Number: 38-06054 Rev. *G
Page 29 of 33
CY7C09569V
CY7C09579V
Package Diagrams (continued)
Figure 26. 172-ball FBGA (15 × 15 × 1.25 mm) BB172 Package Outline, 51-85114
51-85114 *D
Document Number: 38-06054 Rev. *G
Page 30 of 33
CY7C09569V
CY7C09579V
Acronyms
Acronym
Document Conventions
Description
Units of Measure
ADS
address strobe
BGA
ball grid array
°C
degree Celsius
CE
chip enable
MHz
megahertz
CMOS
complementary metal oxide semiconductor
µA
microampere
CNTEN
count enable
mA
milliampere
CNTRST
counter reset
mm
millimeter
I/O
input/output
ns
nanosecond
LSB
least significant bit
pF
picofarad
MSB
most significant bit
V
volt
OE
output enable
W
watt
SRAM
static random access memory
TQFP
thin quad flat pack
TTL
transistor-transistor logic
Document Number: 38-06054 Rev. *G
Symbol
Unit of Measure
Page 31 of 33
CY7C09569V
CY7C09579V
Document History Page
Document Title: CY7C09569V/CY7C09579V, 3.3 V 16 K / 32 K × 36 FLEx36® Synchronous Dual-Port Static RAM
Document Number: 38-06054
Rev.
ECN
Orig. of
Change
Submission
Date
**
110213
SZV
12/16/01
Change from Spec number: 38-00743 to 38-06054
*A
122304
RBI
12/27/02
Updated Maximum Ratings (Added Power up requirements to Maximum
Ratings Information).
Description of Change
*B
349775
RUY
See ECN
Updated Ordering Information (Added Pb-free Information).
*C
2897215
RAME
03/22/10
Updated Ordering Information (Removed inactive parts).
Updated Package Diagrams.
*D
3110406
ADMU
12/14/10
Added Ordering Code Definitions.
Minor edits and updated in new template.
*E
3162642
ADMU
02/04/11
Updated Selection Guide (Removed speed bin -67 related information).
Updated Operating Range (Removed Industrial Temperature Range
information).
Updated Electrical Characteristics (Removed speed bin -67 related
information).
Updated Switching Characteristics (Removed speed bin -67 related
information).
Added Acronyms and Units of Measure.
*F
3352391
ADMU
08/23/11
Updated Package Diagrams (Spec 51-85047 (Changed revision from *C to
*D)).
*G
3702863
SMCH
08/20/2012
Document Number: 38-06054 Rev. *G
Updated Logic Block Diagram (Aligned all the objects correctly).
Updated Switching Waveforms (Updated Figure 18 (Aligned the naming of
objects correctly), updated Figure 19 (Aligned the naming of objects correctly),
updated Figure 20 (Aligned the naming of objects correctly)).
Updated Right Port Operation (Updated the columns Data on 1st Cycle, Data
on 2nd Cycle, Data on 3rd Cycle and Data on 4th Cycle).
Updated Bus Match Operation (Updated Byte (9-bit) Operation (description)).
Updated Package Diagrams (Spec 51-85114 (Changed revision from *C to
*D)).
Replaced Logic ‘0’ with Logic LOW and replaced Logic ‘1’ with Logic HIGH
across the document.
Page 32 of 33
CY7C09569V
CY7C09579V
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
cypress.com/go/memory
cypress.com/go/image
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/touch
USB Controllers
Wireless/RF
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2001-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-06054 Rev. *G
Revised August 20, 2012
Page 33 of 33
FLEx36 is a registered trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
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