CY7C1006D

CY7C106D CY7C1006D 1-Mbit (256K x 4) Static RAM Features • Pin- and function-compatible with CY7C106B/CY7C1006B • High speed — tAA = 10 ns • Low active power — ICC = 80 mA @ 10 ns • Low CMOS standby power — ISB2 = 3.0 mA • 2.0V Data Retention • Automatic power-down when deselected • CMOS for optimum speed/power • TTL-compatible inputs and outputs • CY7C106D available in Pb-free 28-pin 400-Mil wide Molded SOJ package. CY7C1006D available in Pb-free 28-pin 300-Mil wide Molded SOJ package Functional Description [1] The CY7C106D and CY7C1006D are high-performance CMOS static RAMs organized as 262,144 words by 4 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. These devices have an automatic power-down feature that reduces power consumption by more than 65% when the devices are deselected. The four input and output pins (IO0 through IO3) are placed in a high-impedance state when: • Deselected (CE HIGH) • Outputs are disabled (OE HIGH) • When the write operation is active (CE and WE LOW) Write to the device by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the four IO pins (IO0 through IO3) is then written into the location specified on the address pins (A0 through A17). Read from the device by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appears on the four IO pins. Logic Block Diagram INPUT BUFFER A1 A2 A3 A4 A5 A6 A7 A8 A9 CE WE OE ROW DECODER 256K x 4 ARRAY SENSE AMPS IO0 IO1 IO2 IO3 COLUMN DECODER POWER DOWN Note 1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com. A0 A10 A11 A12 A13 A14 A15 A16 A17 Cypress Semiconductor Corporation Document #: 38-05459 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised February 22, 2007 [+] [+] Feedback CY7C106D CY7C1006D Pin Configuration [2] SOJ Top View A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 CE OE GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A17 A16 A15 A14 A13 A12 A11 NC IO3 IO2 IO1 IO0 WE Selection Guide CY7C106D-10 CY7C1006D-10 Maximum Access Time Maximum Operating Current Maximum Standby Current 10 80 3 Unit ns mA mA Note 2. NC pins are not connected on the die. Document #: 38-05459 Rev. *E Page 2 of 11 [+] [+] Feedback CY7C106D CY7C1006D Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VCC Relative to GND [3] ... –0.5V to +6.0V DC Voltage Applied to Outputs in High-Z State [3] ...................................–0.5V to VCC + 0.5V DC Input Voltage [3] ............................... –0.5V to VCC + 0.5V Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage .......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current .................................................... > 200 mA Operating Range Range Industrial Ambient Temperature –40°C to +85°C VCC 5V ± 0.5V Speed 10 ns Electrical Characteristics (Over the Operating Range) Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage [3] Test Conditions IOH = – 4.0 mA IOL = 8.0 mA 7C106D-10 7C1006D-10 Min 2.4 0.4 2.2 –0.5 VCC + 0.5 0.8 +1 +1 80 72 58 37 10 3 Max Unit V V V V µA µA mA mA mA mA mA mA Input Leakage Current Output Leakage Current VCC Operating Supply Current GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Max, IOUT = 0 mA, f = fmax = 1/tRC 100 MHz 83 MHz 66 MHz 40 MHz –1 –1 ISB1 ISB2 Automatic CE Power-Down Current—TTL Inputs Automatic CE Power-Down Current—CMOS Inputs Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fmax Max VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V, f=0 Note 3. VIL (min) = –2.0V and VIH(max) = VCC + 1V for pulse durations of less than 5 ns. Document #: 38-05459 Rev. *E Page 3 of 11 [+] [+] Feedback CY7C106D CY7C1006D Capacitance [4] Parameter CIN: Addresses CIN: Controls COUT Output Capacitance Description Input Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max 7 10 10 Unit pF pF pF Thermal Resistance [4] Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 300-Mil Wide SOJ 59.16 40.84 400-Mil Wide SOJ 58.76 40.54 Unit °C/W °C/W AC Test Loads and Waveforms [5] Z = 50Ω OUTPUT 50 Ω * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 1.5V 3.0V ALL INPUT PULSES 90% 10% 90% 10% 30 pF* GND Rise Time: ≤ 3 ns (a) (b) Fall Time: ≤ 3 ns High-Z characteristics: 5V OUTPUT INCLUDING JIG AND SCOPE 5 pF R2 255Ω R1 480Ω (c) Notes 4. Tested initially and after any design or process changes that may affect these parameters. 5. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load shown in Figure (c). Document #: 38-05459 Rev. *E Page 4 of 11 [+] [+] Feedback CY7C106D CY7C1006D Switching Characteristics (Over the Operating Range) [6] Parameter Read Cycle tpower [7] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD [10] [10] Description Min VCC(typical) to the first access Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z CE LOW to Low Z CE HIGH to High Z [8, 9] [9] [8, 9] 7C106D-10 7C1006D-10 Max Unit 100 10 10 3 10 5 0 5 3 5 0 10 10 7 7 0 0 7 6 0 3 5 µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CE LOW to Power-Up CE HIGH to Power-Down [11, 12] Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z [9] WE LOW to High Z [8, 9] Notes 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 7. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 8. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of “AC Test Loads and Waveforms [5]” on page 4. Transition is measured when the outputs enter a high impedance state. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 10. This parameter is guaranteed by design and is not tested. 11. The internal write time of the memory is defined by the overlap of CE and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. Document #: 38-05459 Rev. *E Page 5 of 11 [+] [+] Feedback CY7C106D CY7C1006D Data Retention Characteristics (Over the Operating Range) Parameter VDR ICCDR tCDR [4] tR [13, 14] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Conditions VCC = VDR = 2.0V, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V Min 2.0 Max 3 Unit V mA ns ns 0 tRC Data Retention Waveform DATA RETENTION MODE VCC 4.5V tCDR VDR > 2V 4.5V tR CE Switching Waveforms Read Cycle No.1 (Address Transition Controlled) [15, 16] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Read Cycle No. 2 (OE Controlled) [16, 17] ADDRESS tRC CE tACE OE tDOE tLZOE HIGH IMPEDANCE DATA OUT VCC SUPPLY CURRENT tPU 50% tLZCE DATA VALID tPD 50% tHZOE tHZCE HIGH IMPEDANCE ICC ISB Notes 13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 µs or stable at VCC(min) > 50 µs. 14. tr < 3 ns for all speeds. 15. Device is continuously selected, OE and CE = VIL. 16. WE is HIGH for read cycle. Document #: 38-05459 Rev. *E Page 6 of 11 [+] [+] Feedback CY7C106D CY7C1006D Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled) [18, 19] tWC ADDRESS tSCE tSA tAW tPWE WE tSD DATA IO DATA VALID tHD tHA CE Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [18, 19] tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA OE tSD DATA IO tHZOE DATA VALID tHD Notes 18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 19. Data IO is high impedance if OE = VIH. Document #: 38-05459 Rev. *E Page 7 of 11 [+] [+] Feedback CY7C106D CY7C1006D Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) [12, 19] tWC ADDRESS tSCE CE tAW tSA WE tSD DATA IO tHZWE DATA VALID tPWE tHA tHD tLZWE Truth Table CE H L L L OE X L X H WE X H L H Input/Output High Z Data Out Data In High Z Power-Down Read Write Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 10 Ordering Code CY7C106D-10VXI CY7C1006D-10VXI Package Diagram 51-85032 51-85031 Package Type 28-pin (400-Mil) Molded SOJ (Pb-free) 28-pin (300-Mil) Molded SOJ (Pb-free) Operating Range Industrial Please contact your local Cypress sales representative for availability of these parts. Document #: 38-05459 Rev. *E Page 8 of 11 [+] [+] Feedback CY7C106D CY7C1006D Package Diagrams Figure 1. 28-pin (300-Mil) Molded SOJ, 51-85031 NOTE : 1. JEDEC STD REF MO088 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.006 in (0.152 mm) PER SIDE 3. DIMENSIONS IN INCHES MIN. MAX. PIN 1 ID 14 1 DETAIL A EXTERNAL LEAD DESIGN 0.291 0.300 0.330 0.350 0.013 0.019 OPTION 1 OPTION 2 0.026 0.032 0.014 0.020 15 28 0.697 0.713 0.120 0.140 0.050 TYP. SEATING PLANE 0.007 0.013 0.004 A 0.025 MIN. 0.262 0.272 51-85031-*C Document #: 38-05459 Rev. *E Page 9 of 11 [+] [+] Feedback CY7C106D CY7C1006D Package Diagrams Figure 2. 28-pin (400-Mil) Molded SOJ, 51-85032 PIN 1 I.D 14 1 .395 .405 .435 .445 DIMENSIONS IN INCHES MIN. MAX. 15 28 .720 .730 SEATING PLANE .128 .148 .026 .032 .015 .020 0.004 .007 .013 .360 .380 51-85032-*B .025 MIN. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05459 Rev. *E Page 10 of 11 © Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] [+] Feedback CY7C106D CY7C1006D Document History Page Document Title: CY7C106D/CY7C1006D, 1-Mbit (256K x 4) Static RAM Document Number: 38-05459 REV. ** *A *B *C *D ECN NO. Issue Date 201560 233693 262950 See ECN 560995 See ECN See ECN See ECN See ECN See ECN Orig. of Change SWI RKF RKF RKF VKN Description of Change Advance information data sheet for C9 IPP ICC,ISB1,ISB2 Specs are modified as per EROS (Spec # 01-2165) Pb-free offering in the ‘ordering information’ Added Tpower Spec in Switching Characteristics table Shaded ‘Ordering Information’ Reduced Speed bins to -10 and -12 ns Converted from Preliminary to Final Removed Commercial Operating range Removed 12 ns speed bin Added ICC values for the frequencies 83MHz, 66MHz and 40MHz Updated Thermal Resistance table Updated Ordering Information table Changed Overshoot spec from VCC+2V to VCC+1V in footnote #3 Changed ICC spec from 60 mA to 80 mA for 100MHz, 55 mA to 72 mA for 83MHz, 45 mA to 58 mA for 66MHz, 30 mA to 37 mA for 40MHz *E 802877 See ECN VKN Document #: 38-05459 Rev. *E Page 11 of 11 [+] [+] Feedback