CY7C1011CV33_10

CY7C1011CV33 2-Mbit (128K x 16) Static RAM Features ■ Functional Description The CY7C1011CV33 is a high performance complementary metal oxide semiconductor (CMOS) static RAM organized as 131,072 words by 16 bits. This device has an automatic power down feature that significantly reduces power consumption when deselected. To write to the device, take CE and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A16). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A16). To read from the device, take CE and OE LOW while forcing the Write Enable (WE) HIGH. If BLE is LOW, then data from the memory location specified by the address pins appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. For more information, see the “Truth Table” on page 10 for a complete description of Read and Write modes. The input and output pins (I/O0 through I/O15) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). For best practice recommendations, refer to the Cypress  application note AN1064, SRAM System Guidelines. Temperature ranges ❐ Industrial: –40 °C to 85 °C ❐ Automotive-A: –40 °C to 85 °C ❐ Automotive-E: –40 °C to 125 °C Pin and function compatible with CY7C1011BV33 High speed ❐ tAA = 10 ns (Industrial and Automotive-A) ❐ tAA = 12 ns (Automotive-E) Low active power ❐ 360 mW (max) (Industrial and Automotive-A) 2.0 V data retention Automatic power down when deselected Independent control of upper and lower bits Easy memory expansion with Chip Enable (CE) and Output Enable (OE) features Available in Pb-free 44-pin thin small outline package (TSOP) II, 44-pin thin quad flat package (TQFP), and non Pb-free 48-ball very fine ball grid array (VFBGA) packages ■ ■ ■ ■ ■ ■ ■ ■ Logic Block Diagram INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 ROW DECODER 128K x 16 RAM Array SENSE AMPS I/O0–I/O7 I/O8–I/O15 COLUMN DECODER BHE WE CE OE BLE A10 A11 A12 A14 A13 A16 A15 A9 Cypress Semiconductor Corporation Document Number: 38-05232 Rev. *K • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 18, 2010 [+] Feedback CY7C1011CV33 Contents Features .............................................................................. Functional Description....................................................... Logic Block Diagram.......................................................... Contents .............................................................................. Pin Configuration ............................................................... Selection Guide .................................................................. Maximum Ratings............................................................... Operating Range................................................................. Electrical Characteristics................................................... Capacitance ........................................................................ Thermal Resistance............................................................ Switching Characteristics.................................................. Switching Waveforms ........................................................ 1 1 1 2 3 4 5 5 5 6 6 7 8 Truth Table........................................................................ Ordering Information ....................................................... Ordering Code Definition............................................. Package Diagrams ........................................................... Acronyms.......................................................................... Document History Page................................................... Sales, Solutions, and Legal Information ........................ Worldwide Sales and Design Support......................... Products ...................................................................... PSoC Solutions ........................................................... 10 11 11 12 14 15 16 16 16 16 Document Number: 38-05232 Rev. *K Page 2 of 16 [+] Feedback CY7C1011CV33 Pin Configuration Figure 1. 44-Pin TSOP II [1] Figure 2. 48-Ball VFBGA Pinout [1] A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC 1 BLE I/O8 I/O9 2 OE BHE I/O10 3 A0 A3 A5 NC NC 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11 6 NC I/O0 I/O2 VCC VSS I/O6 I/O7 NC A B C D E F G H VSS I/O11 VCC I/O12 I/O14 I/O13 A14 I/O15 NC NC A8 A12 A9 Figure 3. 44-Pin TQFP BHE 35 BLE 34 33 32 31 30 29 28 27 26 25 24 23 21 12 13 14 16 17 18 15 19 20 22 A13 A15 A14 A11 A12 A10 38 A16 1 44 43 42 40 39 37 41 36 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 1 2 3 4 5 6 7 8 9 10 11 I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC WE A0 A1 A9 OE A6 NC A2 A5 A3 Note 1. NC pins are not connected on the die. Document Number: 38-05232 Rev. *K A4 A7 A8 Page 3 of 16 [+] Feedback CY7C1011CV33 Selection Guide Description Maximum access time Maximum operating current Industrial Automotive-A Automotive-E Maximum CMOS standby current Industrial Automotive-A Automotive-E 10 10 15 -10 10 100 100 120 10 -12 12 95 Unit ns mA mA mA mA mA mA Document Number: 38-05232 Rev. *K Page 4 of 16 [+] Feedback CY7C1011CV33 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –65 C to +150 C Ambient temperature with power applied ........................................... –55 C to +125 C Supply voltage on VCC relative to GND[2] ..... –0.5 V to +4.6 V DC voltage applied to outputs in High Z state[2] .................................... –0.5 V to VCC+0.5 V DC input voltage[2] ................................. –0.5 V to VCC+0.5 V Current into outputs (LOW) ......................................... 20 mA Static discharge voltage............................................ >2001 V (MIL-STD-883, method 3015) Latch up current ...................................................... >200 mA Operating Range Range Industrial Automotive-A Automotive -E Ambient Temperature (TA) –40 C to +85 C –40 C to +85 C –40 C to +125 C VCC 3.3 V  10% Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL IIX Description Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage[2] Input leakage current GND < VI < VCC Industrial Automotive-A Automotive -E IOZ Output leakage current GND < VI < VCC, Output disabled VCC = Max, IOUT = 0 mA, f = fMAX = 1/tRC Max VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Max VCC, CE > VCC – 0.3 V, VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0 Industrial Automotive-A Automotive -E ICC VCC operating supply current Industrial Automotive-A Automotive -E ISB1 Automatic CE power down current — TTL Inputs Industrial Automotive-A Automotive -E ISB2 Automatic CE power down current — CMOS inputs Industrial Automotive-A Automotive -E 10 10 15 40 40 45 10 mA 100 100 120 40 mA –1 –1 +1 +1 –20 +20 95 mA Test Conditions VCC = Min, IOH = –4.0 mA VCC = Min, IOL = 8.0 mA 2.0 –0.3 –1 –1 -10 Min 2.4 0.4 VCC + 0.3 0.8 +1 +1 –20 –1 +20 +1 A 2.0 –0.3 –1 Max 2.4 0.4 VCC + 0.3 0.8 +1 -12 Min Max Unit V V V V A Note 2. VIL (min) = –2.0 V for pulse durations of less than 20 ns. Document Number: 38-05232 Rev. *K Page 5 of 16 [+] Feedback CY7C1011CV33 Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter CIN COUT Description Input capacitance Output capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3 V Max 8 8 Unit pF pF Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter Description Thermal resistance (Junction to ambient) Thermal resistance (Junction to case) Test Conditions Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit board TSOP II 44.56 10.75 Figure 4. AC Test Loads and Waveforms [3] 10-ns devices: OUTPUT 50  * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 1.5 V 12-ns devices: 3.3 V R 317  TQFP 42.66 14.64 VFBGA 46.98 9.63 Unit C/W C/W JA JC Z = 50 30 pF* OUTPUT 30 pF* R2 351 (a) (b) High-Z characteristics: R 317  3.0 V0 V GND ALL INPUT PULSES 90% 10% 90% 10% 3.3 V OUTPUT 5 pF R2 351 Rise Time: 1 V/ns (c) Fall Time: 1 V/ns (d) Note 3. AC characteristics (except High-Z) for 10-ns parts are tested using the load conditions shown in Figure 4 (a). All other speeds are tested using the Thevenin load shown in Figure 4 (b). High-Z characteristics are tested for all speeds using the test load shown in Figure 4 (d). Document Number: 38-05232 Rev. *K Page 6 of 16 [+] Feedback CY7C1011CV33 Switching Characteristics Over the Operating Range [4] Parameter Read Cycle tpower[5] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW VCC (typical) to the first access Read cycle time Address to data valid Data hold from address change CE LOW to data valid OE LOW to data valid OE LOW to Low CE LOW to Low Z[6] Z[6] Z[6, 7] 0 10 Industrial/Automotive-A Automotive-E Byte enable to Low Z Byte disable to High Z [8, 9] Description -10 Min 1 10 10 3 10 Industrial/Automotive-A Automotive-E 0 5 3 5 0 3 0 5 3 Max Min 1 12 -12 Max Unit s ns 12 12 6 8 ns 6 6 12 6 8 ns ns ns ns ns ns ns 6 ns ns ns ns ns ns ns ns ns ns 6 ns ns ns ns ns ns OE HIGH to High Z[6, 7] CE HIGH to High CE LOW to power up CE HIGH to power down Byte enable to data valid 5 0 5 10 7 7 0 0 7 5 0 3 5 7 8 12 8 8 0 0 8 6 0 3 0 Write cycle time CE LOW to write end Address setup to write end Address hold from write end Address setup to write start WE pulse width Data setup to write end Data hold from write end WE HIGH to Low WE LOW to High Z[6] Z[6, 7] Byte enable to end of write Notes 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, and input pulse levels of 0 to 3.0 V. 5. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed. 6. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 7. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of “AC Test Loads and Waveforms [3]” on page 6. Transition is measured 500 mV from steady state voltage. 8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW, and BHE/BLE LOW. CE, WE, and BHE/BLE must be LOW to initiate a write. The transition of these signals terminate the write. The input data setup and hold timing is referenced to the leading edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 38-05232 Rev. *K Page 7 of 16 [+] Feedback CY7C1011CV33 Switching Waveforms Figure 5. Read Cycle No. 1 (Address Transition Controlled)[10, 11] tRC RC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Figure 6. Read Cycle No. 2 (OE Controlled)[11, 12] ADDRESS tRC CE tACE OE tDOE BHE, BLE tLZOE tDBE tLZBE DATA OUT VCC SUPPLY CURRENT HIGH IMPEDANCE tLZCE tPU 50% tHZCE tHZBE DATA VALID tPD 50% ICC ISB tHZOE HIGH IMPEDANCE Notes 10. Device is continuously selected. OE, CE, BHE, and/or BLE = VIL. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE transition LOW. Document Number: 38-05232 Rev. *K Page 8 of 16 [+] Feedback CY7C1011CV33 Switching Waveforms (continued) Figure 7. Write Cycle No. 1 (CE Controlled)[13, 14] tWC ADDRESS tSA CE tAW tSCE tHA tPWE WE tBW BHE, BLE tSD DATA IO tHD Figure 8. Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS tSA BHE, BLE tBW tAW tPWE WE tSCE CE tSD DATA I/O tHD tHA Notes 13. Data I/O is high impedance if OE, BHE, and/or BLE = VIH. 14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document Number: 38-05232 Rev. *K Page 9 of 16 [+] Feedback CY7C1011CV33 Switching Waveforms (continued) Figure 9. Write Cycle No. 3 (WE Controlled, LOW) tWC ADDRESS tSCE CE tAW tSA WE tBW BHE, BLE tPWE tHA tHZWE DATA I/O tSD tHD tLZWE Truth Table CE H L L L L L L L OE X L L L X X X H WE X H H H L L L H BLE X L L H L L H X BHE X L H L L H L X I/O0– I/O7 I/O8 – I/O15 High Z Data Out Data Out High Z Data In Data In High Z High Z High Z Data Out High Z Data Out Data In High Z Data In High Z Mode Power down Read – all bits Read – lower bits only Read – upper bits only Write – all bits Write – lower bits only Write – upper bits only Selected, outputs disabled Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Document Number: 38-05232 Rev. *K Page 10 of 16 [+] Feedback CY7C1011CV33 Ordering Information Speed (ns) 10 12 Ordering Code CY7C1011CV33-10ZSXA CY7C1011CV33-12AXI CY7C1011CV33-12ZSXE CY7C1011CV33-12BVXE Package Diagram 51-85064 44-pin TQFP (Pb-free) 51-85087 44-pin TSOP II (Pb-free) 51-85150 48-ball (6 x 8 x 1 mm) VFBGA Package Type Operating Range Automotive-A Industrial Automotive-E 51-85087 44-pin TSOP II (Pb-free) Ordering Code Definition CY 7 C 101 1 C V33 Voltage: 3.3 V Technology: 150 nm Bus Width: x16 Density: 2 Mbit Technology: CMOS Marketing Code: 7= SRAM Company ID : CY = Cypress Document Number: 38-05232 Rev. *K Page 11 of 16 [+] Feedback CY7C1011CV33 Package Diagrams Figure 10. 44-Pin Thin Small Outline Package Type II, 51-85087 51-85087 *C Document Number: 38-05232 Rev. *K Page 12 of 16 [+] Feedback CY7C1011CV33 Package Diagrams (continued) Figure 11. 44-Pin Thin Plastic Quad Flat Pack, 51-85064 51-85064 *D Document Number: 38-05232 Rev. *K Page 13 of 16 [+] Feedback CY7C1011CV33 Package Diagrams (continued) Figure 12. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150 51-85150 *F 51-85150 *E Acronyms Acronym BHE BLE CE CMOS I/O SRAM VFBGA TQFP TSOP WE Description Bye High Enable Byte Low Enable Chip Enable complementary metal oxide semiconductor input/output static random access memory very fine ball gird array thin quad flat pack thin small outline package Write Enable Document Number: 38-05232 Rev. *K Page 14 of 16 [+] Feedback CY7C1011CV33 Document History Page Document Title: CY7C1011CV33, 2-Mbit (128K x 16) Static RAM Document Number: 38-05232 Orig. of REV. ECN NO. Issue Date Description of Change Change ** 117132 07/31/02 HGK New Data Sheet *A 118057 08/19/02 HGK Pin configuration for 48-ball FBGA correction *B 119702 10/11/02 DFP Updated FBGA to VFBGA; updated package code on page 8 to BV48A. Updated address pinouts on page 1 to A0 to A16. Updated CMOS standby current on page 1 from 8 to 10 mA *C 386106 See ECN PCI Added lead-free parts in Ordering Information Table *D 498501 See ECN NXR Corrected typo in the Logic Block Diagram on page# 1 Included the Maximum Ratings for Static Discharge Voltage and Latch up Current on page# 3 Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Updated the Ordering Information Table *E 522620 See ECN VKN Added Thermal Resistance Table *F 1891366 See ECN VKN/AESA Added -10ZSXA part Updated Ordering Information table *G 2428606 See ECN VKN/PYRS Corrected typo in the 44-Pin TSOP and 48-Ball FBGA pinout Removed Commercial parts Removed 15 ns speed bin Removed inactive parts from the Ordering Information table *H 2664421 02/25/09 VKN/AESA Added Automotive-E specs for 12 ns speed Updated Ordering Information table *I 2898399 03/24/2010 KAO/AJU Updated Package Diagrams *J 2950666 06/11/2010 VKN Included “CY7C1011CV33-12BVXE” in Ordering Information Added Contents and Acronyms Updated Sales, Solutions, and Legal Information Added Ordering Code Definition. *K 3089939 11/13/2010 PRAS Removed inactive part from Ordering Information. Document Number: 38-05232 Rev. *K Page 15 of 16 [+] Feedback CY7C1011CV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2002-2010. The information contained herein is subject to change without notice. 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Document Number: 38-05232 Rev. *K Revised November 18, 2010 Page 16 of 16 All products and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback