CY7C1012AV25-12BGC

PRELIMINARY CY7C1012AV25 512K x 24 Static RAM Features • High speed — tAA = 8, 10, 12 ns • Low active power — 1080 mW (max.) • Operating voltages of 2.5 ± 0.2V • 1.5V data retention • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE0, CE1 and CE2 features Writing the data bytes into the SRAM is accomplished when the chip select controlling that byte is LOW and the write enable input (WE) input is LOW. Data on the respective input/output (I/O) pins is then written into the location specified on the address pins (A0–A16). Asserting all of the chip selects LOW and write enable LOW will write all 24 bits of data into the SRAM. Output enable (OE) is ignored while in WRITE mode. Data bytes can also be individually read from the device. Reading a byte is accomplished when the chip select controlling that byte is LOW and write enable (WE) HIGH while output enable (OE) remains LOW. Under these conditions, the contents of the memory location specified on the address pins will appear on the specified data input/output (I/O) pins. Asserting all the chip selects LOW will read all 24 bits of data from the SRAM. The 24 I/O pins (I/O0–I/O23) are placed in a high-impedance state when all the chip selects are HIGH or when the output enable (OE) is HIGH during a READ mode. For further details, refer to the truth table of this data sheet. The CY7C1012AV25 is available in a standard 119-ball BGA. Functional Description The CY7C1012AV25 is a high-performance CMOS static RAM organized as 512K words by 24 bits. Each data byte is separately controlled by the individual chip selects (CE0, CE1, CE2). CE0 controls the data on the I/O0–I/O7, while CE1 controls the data on I/O8–I/O15, and CE2 controls the data on the data pins I/O16–I/O23. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Functional Block Diagram INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER 512K x 24 ARRAY 4096 x 4096 SENSE AMPS I/O0–I/O7 I/O8–I/O15 I/O16–I/O23 COLUMN DECODER CONTROL LOGIC CE0, CE1, CE2 WE OE Selection Guide Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current -8 8 300 300 50 -10 10 275 275 50 -12 12 260 260 50 Unit ns mA mA A 10 A11 A 12 A 13 A 14 A 15 A 16 A 17 A18 Commercial Industrial Commercial/Industrial Cypress Semiconductor Corporation Document #: 38-05337 Rev. ** • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised January 27, 2003 PRELIMINARY Pin Configurations 119 BGA Top View CY7C1012AV25 1 A B C D E F G H J K L M N P R T U NC NC I/O12 I/O13 I/O14 I/O15 I/O16 I/O17 NC I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 NC NC 2 A A NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD A A A 3 A A CE1 VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS NC A A 4 A CE0 NC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC WE OE 5 A A CE2 VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS NC A A 6 A A NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD A A A 7 NC NC I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 DNU I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 NC NC Document #: 38-05337 Rev. ** Page 2 of 9 PRELIMINARY Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................–65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VCC to Relative GND[1] .... –0.5V to +3.6V DC Voltage Applied to Outputs in High-Z State[1] ....................................–0.5V to VCC + 0.5V CY7C1012AV25 DC Input Voltage[1] ................................ –0.5V to VCC + 0.5V Current into Outputs (LOW)......................................... 20 mA Operating Range Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 2.5V ± 0.2V DC Electrical Characteristics Over the Operating Range -8 Parameter VOH VOL VIH VIL[1] IIX IOZ ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current VCC Operating Supply Current Automatic CE Power-down Current —TTL Inputs Automatic CE Power-down Current —CMOS Inputs GND < VI < VCC VCC = Max., f = fMAX = 1/tRC Commercial Industrial Output Leakage Current GND < VOUT < VCC, Output Disabled Test Conditions[2] VCC = Min., IOH = –1.0 mA VCC = Min., IOL = 1.0 mA 2.0 –0.3 –1 –1 Min. 2.0 0.4 VCC + 0.3 0.8 +1 +1 300 300 100 2.0 –0.3 –1 –1 Max. 2.0 0.4 VCC + 0.3 0.8 +1 +1 275 275 100 2.0 –0.3 –1 –1 -10 Min. Max. 2.0 0.4 VCC + 0.3 0.8 +1 +1 260 260 100 -12 Min. Max. Unit V V V V µA µA mA mA mA Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Max. VCC, Commercial CE > VCC – 0.2V, /Industrial VIN > VCC – 0.2V, or VIN < 0.2V, f = 0 ISB2 50 50 50 mA Capacitance[3] Parameter CIN COUT Description Input Capacitance I/O Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 2.5V Max. 8 10 Unit pF pF Notes: 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 2. CE refers to a combination of CE0, CE1, and CE2. CE is active LOW when all three of these signals are active LOW at the same time. 3. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05337 Rev. ** Page 3 of 9 PRELIMINARY AC Test Loads and Waveforms[4] 50Ω OUTPUT Z0 = 50Ω VTH = VDD/2 30 pF* * Capacitive Load consists of all components of the test environment. ALL INPUT PULSES 2.5V 90% GND Rise time > 1 V/ns 10% 90% 10% Fall time: > 1 V/ns 2.5V OUTPUT CY7C1012AV25 R1 317 Ω 5 pF INCLUDING JIG AND SCOPE R2 351Ω (a) (b) (c) AC Switching Characteristics Over the Operating Range Parameter Read Cycle tpower[6] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write tWC tSCE Cycle[9, 10] Write Cycle Time CE1, CE2, and CE3 LOW to Write End VCC(typical) to the first access Read Cycle Time Address to Data Valid Data Hold from Address Change CE1, CE2, and CE3 LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z[7] Z[7] Description [5] -8 Min. 1 8 8 3 8 5 1 5 3 5 0 8 5 1 5 8 6 10 7 1 0 3 Z[7] 1 3 Max. Min. 1 10 -10 Max. Min. 1 12 10 3 10 5 1 5 3 5 0 10 5 1 5 12 8 -12 Max. Unit ms ns 12 12 6 6 6 12 6 6 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns OE HIGH to High CE1, CE2, and CE3 LOW to Low Z[7] CE1, CE2, or CE3 HIGH to High CE1, CE2, and CE3 LOW to CE1, CE2, or CE3 HIGH to Byte Enable to Data Valid Byte Enable to Low Z[7] Z[7] Byte Disable to High Power-up[8] Power-down[8] Notes: 4. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (2.3V). As soon as 1ms (Tpower) after reaching the minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 1.5V) voltage. 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.1V, input pulse levels of 0 to 2.3V, and output loading of the specified IOL/IOH and transmission line loads. Test conditions for the read cycle use output loading as shown in part a) of the AC test loads, unless specified otherwise. 6. This part has a voltage regulator which steps down the voltage from 3V to 2V internally. tpower time has to be provided initially before a read/write operation is started. 7. tHZOE, tHZCE , tHZWE, tHZBE, and t LZOE, t LZCE , tLZWE, tLZBE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage. 8. These parameters are guaranteed by design and are not tested. 9. The internal write time of the memory is defined by the overlap of CE1, CE2, and CE3 LOW and WE LOW. The chip enables must be active and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05337 Rev. ** Page 4 of 9 PRELIMINARY AC Switching Characteristics Over the Operating Range (continued)[5] -8 Parameter tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW Description Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z [7] [7] CY7C1012AV25 -10 Max. Min. 7 0 0 7 5.5 0 3 5 5 7 8 Max. Min. 8 0 0 8 6 0 3 -12 Max. Unit ns ns ns ns ns ns ns 6 ns ns Min. 6 0 0 6 5 0 3 6 WE LOW to High Z Byte Enable to End of Write Data Retention Waveform DATA RETENTION MODE VCC 2.3V tCDR CE VDR > 1.5V 2.3V tR Switching Waveforms Read Cycle No. 1[11, 12] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[2, 12, 13] ADDRESS tRC CE tACE OE tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZOE tHZCE DATA VALID tPD 50% ISB ICC HIGH IMPEDANCE DATA OUT Notes: 11. Device is continuously selected. OE, CE = VIL. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW. Document #: 38-05337 Rev. ** Page 5 of 9 PRELIMINARY Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[2, 14, 15] tWC ADDRESS tSCE CE tSA tAW tPWE WE tSD DATA I/O DATA VALID tHD tSCE tHA CY7C1012AV25 Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 15] tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA OE tSD DATA I/O NOTE 16 tHZOE DATAIN VALID tHD Write Cycle No. 3 (WE Controlled, OE LOW)[2, 15] tWC ADDRESS tSCE CE tAW tSA WE tSD DATA I/O NOTE 16 tHZWE Notes: 14. Data I/O is high impedance if OE = VIH. 15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 16. During this period the I/Os are in the output state and input signals should not be applied. tHA tPWE tHD DATA VALID tLZWE Document #: 38-05337 Rev. ** Page 6 of 9 PRELIMINARY Truth Table CE0 H L H H L L H H L L CE1 H H L H L H L H L L CE2 H H H L L H H L L L OE X L L L L X X X X H WE X H H H H L L L L H High-Z I/O0–I/O7 Data Out I/O8–I/O15 Data Out I/O16–I/O23 Data Out Full Data Out I/O0–I/O7 Data In I/O8–I/O15 Data In I/O16–I/O23 Data In Full Data In High-Z I/O0–I/O23 Power-down Read Read Read Read Write Write Write Write Mode CY7C1012AV25 Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Selected, Outputs Disabled Ordering Information Speed (ns) 8 10 12 Ordering Code CY7C1012AV25-8BGC CY7C1012AV25-8BGI CY7C1012AV25-10BGC CY7C1012AV25-10BGI CY7C1012AV25-12BGC CY7C1012AV25-12BGI Package Name BG119 Package Type 14 × 22 mm 119-ball BGA Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Document #: 38-05337 Rev. ** Page 7 of 9 PRELIMINARY Package Diagram 119-lead PBGA (14 x 22 x 2.4 mm) BG119 CY7C1012AV25 51-85115-*B All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05337 Rev. ** Page 8 of 9 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY Document History Page Document Title: CY7C1012AV25 512K x 24 Static RAM Document Number: 38-05337 REV. ** ECN NO. 119630 Issue Date 01/29/03 Orig. of Change DFP New Data Sheet CY7C1012AV25 Description of Change Document #: 38-05337 Rev. ** Page 9 of 9