CY7C1012AV33-10BGC

CY7C1012AV33 512K x 24 Static RAM Features power-down feature that significantly consumption when deselected. • High speed reduces power Writing the data bytes into the SRAM is accomplished when the chip select controlling that byte is LOW and the write enable input (WE) input is LOW. Data on the respective input/output (I/O) pins is then written into the location specified on the address pins (A0–A18). Asserting all of the chip selects LOW and write enable LOW will write all 24 bits of data into the SRAM. Output enable (OE) is ignored while in WRITE mode. — tAA = 8 ns • Low active power — 1080 mW (max.) • Operating voltages of 3.3 ± 0.3V • 2.0V data retention • Automatic power-down when deselected Data bytes can also be individually read from the device. Reading a byte is accomplished when the chip select controlling that byte is LOW and write enable (WE) HIGH while output enable (OE) remains LOW. Under these conditions, the contents of the memory location specified on the address pins will appear on the specified data input/output (I/O) pins. Asserting all the chip selects LOW will read all 24 bits of data from the SRAM. • TTL-compatible inputs and outputs • Easy memory expansion with CE0, CE1 and CE2 features • Available in non Pb-free 119 ball PBGA. Functional Description The 24 I/O pins (I/O0–I/O23) are placed in a high-impedance state when all the chip selects are HIGH or when the output enable (OE) is HIGH during a READ mode. For further details, refer to the truth table of this data sheet. The CY7C1012AV33 is a high-performance CMOS static RAM organized as 512K words by 24 bits. Each data byte is separately controlled by the individual chip selects (CE0, CE1, CE2). CE0 controls the data on the I/O0–I/O7, while CE1 controls the data on I/O8–I/O15, and CE2 controls the data on the data pins I/O16–I/O23. This device has an automatic The CY7C1012AV33 is available in a standard 119-ball PBGA. Functional Block Diagram I/O0–I/O7 SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER INPUT BUFFER 512K x 24 ARRAY COLUMN DECODER I/O8–I/O15 I/O16–I/O23 CE0, CE1, CE2 WE OE A10 A11 A 12 A 13 A 14 A15 A16 A17 A18 CONTROL LOGIC Selection Guide Maximum Access Time Maximum Operating Current Commercial Industrial Commercial/Industrial Maximum CMOS Standby Current Cypress Semiconductor Corporation Document #: 38-05254 Rev. *E • 198 Champion Court • –8 8 300 300 50 –10 10 275 275 50 Unit ns mA mA San Jose, CA 95134-1709 • 408-943-2600 Revised August 3, 2006 [+] Feedback CY7C1012AV33 Pin Configurations[1, 2] 119 PBGA Top View 1 2 3 4 5 6 7 A NC A A A A A NC B NC A A CE0 A A NC C I/O12 NC CE1 NC CE2 NC I/O0 D I/O13 VDD VSS VSS VSS VDD I/O1 E I/O14 VSS VDD VSS VDD VSS I/O2 F I/O15 VDD VSS VSS VSS VDD I/O3 G I/O16 VSS VDD VSS VDD VSS I/O4 H I/O17 VDD VSS VSS VSS VDD I/O5 J NC VSS VDD VSS VDD VSS DNU K I/O18 VDD VSS VSS VSS VDD I/O6 L I/O19 VSS VDD VSS VDD VSS I/O7 M I/O20 VDD VSS VSS VSS VDD I/O8 N I/O21 VSS VDD VSS VDD VSS I/O9 P I/O22 VDD VSS VSS VSS VDD I/O10 R I/O23 A NC NC NC A I/O11 T NC A A WE A A NC U NC A A OE A A NC Notes: 1. NC pins are not connected on the die. 2. DNU pins have to be left floating or tied to VSS to ensure proper application. Document #: 38-05254 Rev. *E Page 2 of 9 [+] Feedback CY7C1012AV33 Maximum Ratings DC Input Voltage[3] ................................ –0.5V to VCC + 0.5V (Above which the useful life may be impaired. For user guidelines, not tested.) Current into Outputs (LOW)......................................... 20 mA Storage Temperature ................................. –65°C to +150°C Operating Range Ambient Temperature with Power Applied............................................. –55°C to +125°C Range Supply Voltage on VCC to Relative GND[3] .... –0.5V to +4.6V Commercial DC Voltage Applied to Outputs in High-Z State[3] ....................................–0.5V to VCC + 0.5V Industrial Ambient Temperature VCC 0°C to +70°C 3.3V ± 0.3V –40°C to +85°C DC Electrical Characteristics Over the Operating Range –8 Parameter Description Test Conditions[4] Min. 2.4 VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA –10 Max. Min. Max. Unit 2.4 V 0.4 0.4 V VIH Input HIGH Voltage 2.0 VCC + 0.3 2.0 VCC + 0.3 V VIL[3] Input LOW Voltage –0.3 0.8 –0.3 0.8 V IIX Input Leakage Current GND < VI < VCC –1 +1 –1 +1 µA IOZ Output Leakage Current GND < VOUT < VCC, Output Disabled –1 +1 –1 +1 µA ICC VCC Operating Supply Current VCC = Max., f = fMAX = 1/tRC ISB1 Automatic CE Power-down Current —TTL Inputs Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX ISB2 Automatic CE Power-down Current —CMOS Inputs Max. VCC, Commercial CE > VCC – 0.3V, /Industrial VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 Commercial 300 275 mA Industrial 300 275 mA 100 100 mA 50 50 mA Capacitance[5] Parameter Description CIN Input Capacitance COUT I/O Capacitance Test Conditions Max. Unit TA = 25°C, f = 1 MHz, VCC = 3.3V 8 pF 10 pF AC Test Loads and Waveforms[6] 50Ω OUTPUT Z0 = 50Ω OUTPUT 30 pF* * Capacitive Load consists of all components of the test environment. (a) R1 317 Ω 3.3V VTH = 1.5V R2 351Ω 5 pF INCLUDING JIG AND SCOPE ALL INPUT PULSES (b) 3.3V 90% GND Rise time > 1 V/ns 90% 10% 10% Fall time: > 1 V/ns (c) Notes: 3. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 4. CE refers to a combination of CE0, CE1, and CE2. CE is active LOW when all three of these signals are active LOW at the same time. 5. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05254 Rev. *E Page 3 of 9 [+] Feedback CY7C1012AV33 AC Switching Characteristics Over the Operating Range[7] –8 Parameter Description Min. –10 Max. Min. Max. Unit Read Cycle tpower[8] VCC(typical) to the first access 1 tRC Read Cycle Time 8 tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE1, CE2, and CE3 LOW to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to Low-Z[9] tHZOE OE HIGH to tLZCE 8 CE1, CE2, or CE3 HIGH to CE1, CE2, and CE3 LOW to Power-up[10] tDBE Byte Enable to Data Valid Low-Z[9] tLZBE Byte Enable to tHZBE Byte Disable to High-Z[9] ns 5 ns ns 5 5 Power-down[10] 10 3 0 ns ns 1 3 High-Z[9] tPU CE1, CE2, or CE3 HIGH to 3 5 CE1, CE2, and CE3 LOW to ns 10 5 tHZCE Write 3 1 Low-Z[9] ms 10 8 High-Z[9] tPD 1 ns ns 5 0 ns ns 8 10 ns 5 5 ns 1 1 5 ns 5 ns Cycle[11, 12] tWC Write Cycle Time tSCE CE1, CE2, and CE3 LOW to Write End tAW Address Set-up to Write End tHA Address Hold from Write End tSA 10 ns 6 7 ns 6 7 ns 0 0 ns Address Set-up to Write Start 0 0 ns tPWE WE Pulse Width 6 7 ns tSD Data Set-up to Write End 5 5.5 ns tHD Data Hold from Write End 0 0 ns 3 3 ns WE HIGH to Low-Z[9] tHZWE WE LOW to High-Z[9] tBW Byte Enable to End of Write tLZWE 8 5 6 5 7 ns ns Notes: 6. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). As soon as 1 ms (Tpower) after reaching the minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage. 7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and transmission line loads. Test conditions for the read cycle use output loading as shown in part a) of the AC test loads, unless specified otherwise. 8. This part has a voltage regulator which steps down the voltage from 3V to 2V internally. tpower time has to be provided initially before a read/write operation is started. 9. tHZOE, tHZCE, tHZWE, tHZBE, and tLZOE, tLZCE, tLZWE, tLZBE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage. 10. These parameters are guaranteed by design and are not tested. Document #: 38-05254 Rev. *E Page 4 of 9 [+] Feedback CY7C1012AV33 Switching Waveforms Read Cycle No. 1[13, 14] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[4, 14, 15] ADDRESS tRC CE tACE OE tHZOE tDOE DATA OUT tHZCE tLZOE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU ICC 50% 50% ISB Write Cycle No. 1 (CE Controlled)[4, 16, 17] tWC ADDRESS tSCE CE tSA tSCE tAW tHA tPWE WE tSD DATA I/O tHD DATA VALID Notes: 11. The internal write time of the memory is defined by the overlap of CE1, CE2, and CE3 LOW and WE LOW. The chip enables must be active and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 12. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 13. Device is continuously selected. OE, CE = VIL. 14. WE is HIGH for read cycle. 15. Address valid prior to or coincident with CE transition LOW. Document #: 38-05254 Rev. *E Page 5 of 9 [+] Feedback CY7C1012AV33 Switching Waveforms (continued) Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[16, 17] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE OE tSD DATA I/O tHD DATAIN VALID NOTE 18 tHZOE Write Cycle No. 3 (WE Controlled, OE LOW)[4, 17] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA I/O NOTE 18 tHD DATA VALID tHZWE tLZWE Notes: 16. Data I/O is high impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 18. During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05254 Rev. *E Page 6 of 9 [+] Feedback CY7C1012AV33 Truth Table CE0 CE1 CE2 OE WE I/O0–I/O23 Mode Power H H H X X High-Z Power-down Standby (ISB) L H H L H I/O0–I/O7 Data Out Read Active (ICC) H L H L H I/O8–I/O15 Data Out Read Active (ICC) H H L L H I/O16–I/O23 Data Out Read Active (ICC) L L L L H Full Data Out Read Active (ICC) L H H X L I/O0–I/O7 Data In Write Active (ICC) H L H X L I/O8–I/O15 Data In Write Active (ICC) H H L X L I/O16–I/O23 Data In Write Active (ICC) L L L X L Full Data In Write Active (ICC) L L L H H High-Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) 8 Ordering Code CY7C1012AV33-8BGC CY7C1012AV33-8BGI 10 Package Diagram Package Type Operating Range 51-85115 119-ball (14 x 22 x 2.4 mm) PBGA Commercial Industrial CY7C1012AV33-10BGC Commercial CY7C1012AV33-10BGI Industrial Document #: 38-05254 Rev. *E Page 7 of 9 [+] Feedback CY7C1012AV33 Package Diagram 119-ball PBGA (14 x 22 x 2.4 mm) (51-85115) 51-85115-*B All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05254 Rev. *E Page 8 of 9 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C1012AV33 Document History Page Document Title: CY7C1012AV33 512K x 24 Static RAM Document Number: 38-05254 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 113711 03/11/02 NSL New Data Sheet *A 117057 07/31/02 DFP Removed 15-ns bin *B 117988 09/03/02 DFP Added 8-ns bin *C 118992 09/19/02 DFP Change Cin - input capacitance -from 6 pF to 8 pF Change Cout -output capacitance from 8 pF to 10 pF *D 120382 11/15/02 DFP Final data sheet. Added note 4 to “AC Test Loads and Waveforms” *E 492137 See ECN NXR Removed 12 ns speed bin from product offering Included note #1 and 2 on page #2 Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Updated Ordering Information Table Document #: 38-05254 Rev. *E Page 9 of 9 [+] Feedback