CY7C1012AV33

CY7C1012AV33 512 K × 24 Static RAM 512 K × 24 Static RAM Features ■ Functional Description The CY7C1012AV33 is a high-performance CMOS static RAM organized as 512 K words by 24 bits. Each data byte is separately controlled by the individual chip selects (CE0, CE1, CE2). CE0 controls the data on the I/O0–I/O7, while CE1 controls the data on I/O8–I/O15, and CE2 controls the data on the data pins I/O16–I/O23. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing the data bytes into the SRAM is accomplished when the chip select controlling that byte is LOW and the write enable input (WE) input is LOW. Data on the respective input/output (I/O) pins is then written into the location specified on the address pins (A0–A18). Asserting all of the chip selects LOW and write enable LOW will write all 24 bits of data into the SRAM. Output enable (OE) is ignored while in WRITE mode. Data bytes can also be individually read from the device. Reading a byte is accomplished when the chip select controlling that byte is LOW and write enable (WE) HIGH while output enable (OE) remains LOW. Under these conditions, the contents of the memory location specified on the address pins will appear on the specified data input/output (I/O) pins. Asserting all the chip selects LOW will read all 24 bits of data from the SRAM. The 24 I/O pins (I/O0–I/O23) are placed in a high-impedance state when all the chip selects are HIGH or when the output enable (OE) is HIGH during a READ mode. For further details, refer to the truth table of this data sheet. The CY7C1012AV33 is available in a standard 119-ball PBGA. High speed ❐ tAA = 8 ns Low active power ❐ 1080 mW (max) Operating voltages of 3.3 ± 0.3 V 2.0 V data retention Automatic power-down when deselected TTL-compatible inputs and outputs Easy memory expansion with CE0, CE1 and CE2 features Available in non Pb-free 119 ball PBGA. ■ ■ ■ ■ ■ ■ ■ Functional Block Diagram INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER 512K x 24 ARRAY SENSE AMPS I/O0–I/O7 I/O8–I/O15 I/O16–I/O23 COLUMN DECODER CONTROL LOGIC CE0, CE1, CE2 WE OE A10 A11 A 12 A 13 A 14 A15 A16 A17 A18 Cypress Semiconductor Corporation Document Number: 38-05254 Rev. *H • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 7, 2011 [+] Feedback CY7C1012AV33 Contents Selection Guide ................................................................ 3 Pin Configurations ........................................................... 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 DC Electrical Characteristics .......................................... 4 Capacitance ...................................................................... 4 AC Test Loads and Waveforms ....................................... 5 AC Switching Characteristics ......................................... 5 Switching Waveforms ...................................................... 7 Truth Table ........................................................................ 9 Ordering Information ........................................................ 9 Ordering Code Definitions ........................................... 9 Package Diagram ............................................................ 10 Acronyms ........................................................................ 11 Document Conventions ................................................. 11 Units of Measure ....................................................... 11 Document History Page ................................................. 12 Sales, Solutions, and Legal Information ...................... 13 Worldwide Sales and Design Support ....................... 13 Products .................................................................... 13 PSoC Solutions ......................................................... 13 Document Number: 38-05254 Rev. *H Page 2 of 13 [+] Feedback CY7C1012AV33 Selection Guide Description Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Commercial Industrial Commercial/Industrial -8 8 300 300 50 Unit ns mA mA Pin Configurations Figure 1. 119-ball PBGA (Top View) [1, 2] 1 A B C D E F G H J K L M N P R T U NC NC I/O12 I/O13 I/O14 I/O15 I/O16 I/O17 NC I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 NC NC 2 A A NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD A A A 3 A A CE1 VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS NC A A 4 A CE0 NC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC WE OE 5 A A CE2 VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS NC A A 6 A A NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD A A A 7 NC NC I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 DNU I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 NC NC Notes 1. NC pins are not connected on the die. 2. DNU pins have to be left floating or tied to VSS to ensure proper application. Document Number: 38-05254 Rev. *H Page 3 of 13 [+] Feedback CY7C1012AV33 Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage Temperature ............................... –65 C to +150 C Ambient Temperature with Power Applied ......................................... –55 C to +125 C Supply Voltage on VCC to Relative GND[3] ................................–0.5 V to +4.6 V DC Voltage Applied to Outputs in high Z State[3] ................................. –0.5 V to VCC + 0.5 V DC Input Voltage[3] ............................. –0.5 V to VCC + 0.5 V Current into Outputs (LOW) ........................................ 20 mA Operating Range Range Commercial Industrial Ambient Temperature 0 C to +70 C –40 C to +85 C VCC 3.3 V  0.3 V DC Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL[3] IIX IOZ ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-down Current — TTL Inputs Automatic CE Power-down Current — CMOS Inputs GND < VI < VCC GND < VOUT < VCC, Output Disabled VCC = Max, f = fMAX = 1/tRC Commercial Industrial Test Conditions[4] VCC = Min, IOH = –4.0 mA VCC = Min, IOL = 8.0 mA -8 Min 2.4 – 2.0 –0.3 –1 –1 – – – – Max – 0.4 VCC + 0.3 0.8 +1 +1 300 300 100 50 Unit V V V V A A mA mA mA mA Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX Max VCC, CE > VCC – 0.3 V, VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0 Commercial / Industrial Capacitance Parameter [5] CIN COUT Description Input Capacitance I/O Capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 3.3 V Max 8 10 Unit pF pF Notes 3. VIL (min) = –2.0 V for pulse durations of less than 20 ns. 4. CE refers to a combination of CE0, CE1, and CE2. CE is active LOW when all three of these signals are active LOW at the same time. 5. Tested initially and after any design or process changes that may affect these parameters. Document Number: 38-05254 Rev. *H Page 4 of 13 [+] Feedback CY7C1012AV33 AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms[6] 50  OUTPUT Z0 = 50  VTH = 1.5 V 30 pF* * Capacitive Load consists of all components of the test environment. ALL INPUT PULSES 90% 10% 90% 10% 3.3 V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 351 R1 317  (a) 3.3 V GND Rise time > 1 V/ns (b) (c) Fall time: > 1 V/ns AC Switching Characteristics Over the Operating Range Parameter[7] Read Cycle tpower[8] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE VCC(typical) to the first access Read Cycle Time Address to Data Valid Data Hold from Address Change CE1, CE2, and CE3 LOW to Data Valid OE LOW to Data Valid OE LOW to low Z[9] Z[9] Z[9] OE HIGH to high Z[9] CE1, CE2, and CE3 LOW to low CE1, CE2, or CE3 HIGH to high CE1, CE2, and CE3 LOW to Byte Enable to Data Valid Byte Enable to low Z[9] Z[9] Byte Disable to high 1 8 – 3 – – 1 – 3 – 0 – – 1 – – – 8 – 8 5 – 5 – 5 – 8 5 – 5 ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description -8 Min Max Unit power-up[10] CE1, CE2, or CE3 HIGH to power-down[10] Notes 6. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0 V). As soon as 1 ms (Tpower) after reaching the minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0 V) voltage. 7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH and transmission line loads. Test conditions for the read cycle use output loading as shown in part (a) of the Figure 2, unless specified otherwise. 8. This part has a voltage regulator which steps down the voltage from 3 V to 2 V internally. tpower time has to be provided initially before a read/write operation is started. 9. tHZOE, tHZCE, tHZWE, tHZBE, and tLZOE, tLZCE, tLZWE, tLZBE are specified with a load capacitance of 5 pF as in part (b) of Figure 2. Transition is measured 200 mV from steady-state voltage. 10. These parameters are guaranteed by design and are not tested. Document Number: 38-05254 Rev. *H Page 5 of 13 [+] Feedback CY7C1012AV33 AC Switching Characteristics (continued) Over the Operating Range Parameter[7] Write Cycle[11, 12] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW Write Cycle Time CE1, CE2, and CE3 LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE HIGH to low Z[13] WE LOW to high Z[13] Byte Enable to End of Write 8 6 6 0 0 6 5 0 3 – 6 – – – – – – – – – 5 – ns ns ns ns ns ns ns ns ns ns ns Description -8 Min Max Unit Notes 11. The internal write time of the memory is defined by the overlap of CE1, CE2, and CE3 LOW and WE LOW. The chip enables must be active and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 12. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 13. tHZOE, tHZCE, tHZWE, tHZBE, and tLZOE, tLZCE, tLZWE, tLZBE are specified with a load capacitance of 5 pF as in part (b) of Figure 2 on page 5. Transition is measured 200 mV from steady-state voltage. Document Number: 38-05254 Rev. *H Page 6 of 13 [+] Feedback CY7C1012AV33 Switching Waveforms Figure 3. Read Cycle No. 1 [14, 15] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Figure 4. Read Cycle No. 2 (OE Controlled) [15, 16, 17] ADDRESS tRC CE tACE OE tDOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tPU 50% DATA VALID tPD 50% tHZOE tHZCE HIGH IMPEDANCE ICC ISB Figure 5. Write Cycle No. 1 (CE Controlled) [17, 18, 19] tWC ADDRESS tSCE CE tSA tAW tPWE WE tSD DATA I/O DATA VALID tHD tSCE tHA Notes 14. Device is continuously selected. OE, CE = VIL. 15. WE is HIGH for read cycle. 16. Address valid prior to or coincident with CE transition LOW. 17. CE refers to a combination of CE0, CE1, and CE2. CE is active LOW when all three of these signals are active LOW at the same time. 18. Data I/O is high impedance if OE = VIH. 19. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document Number: 38-05254 Rev. *H Page 7 of 13 [+] Feedback CY7C1012AV33 Switching Waveforms (continued) Figure 6. Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [20, 21] tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA OE tSD DATA I/O NOTE 22 tHZOE DATAIN VALID tHD Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW) [21, 23] tWC ADDRESS tSCE CE tAW tSA WE tSD DATA I/O NOTE 22 tHZWE DATA VALID tLZWE tHD tPWE tHA Notes 20. Data I/O is high impedance if OE = VIH. 21. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 22. During this period the I/Os are in the output state and input signals should not be applied. 23. CE refers to a combination of CE0, CE1, and CE2. CE is active LOW when all three of these signals are active LOW at the same time. Document Number: 38-05254 Rev. *H Page 8 of 13 [+] Feedback CY7C1012AV33 Truth Table CE0 H L H H L L H H L L CE1 H H L H L H L H L L CE2 H H H L L H H L L L OE X L L L L X X X X H WE X H H H H L L L L H High Z I/O0–I/O7 Data Out I/O8–I/O15 Data Out I/O16–I/O23 Data Out Full Data Out I/O0–I/O7 Data In I/O8–I/O15 Data In I/O16–I/O23 Data In Full Data In High Z I/O0–I/O23 Power-down Read Read Read Read Write Write Write Write Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 8 Ordering Code CY7C1012AV33-8BGC Package Diagram 51-85115 Package Type 119-ball (14 × 22 × 2.4 mm) PBGA Operating Range Commercial Ordering Code Definitions CY 7 C 1012 A V33 - 8 BG C Temperature range: C = Commercial BG = 119-ball PBGA 8 = Speed grade V33 = 3.3 V Process Technology  90 nm Part Identifier Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 38-05254 Rev. *H Page 9 of 13 [+] Feedback CY7C1012AV33 Package Diagram Figure 8. 119-ball PBGA (14 × 22 × 2.4 mm) BG119, 51-85115 51-85115 *C Document Number: 38-05254 Rev. *H Page 10 of 13 [+] Feedback CY7C1012AV33 Acronyms Acronym CMOS CE I/O OE PBGA SRAM TTL WE chip enable input/output output enable plastic ball grid array static random access memory transistor-transistor logic write enable Description complementary metal oxide semiconductor Document Conventions Units of Measure Symbol °C MHz µA mA mm ms mV mW ns % pF V W degree Celcius Mega Hertz micro Amperes milli Amperes milli meter milli seconds milli Volts milli Watts nano seconds percent pico Farad Volts Watts Unit of Measure Document Number: 38-05254 Rev. *H Page 11 of 13 [+] Feedback CY7C1012AV33 Document History Page Document Title: CY7C1012AV33, 512 K × 24 Static RAM Document Number: 38-05254 REV. ** *A *B *C *D *E ECN NO. 113711 117057 117988 118992 120382 492137 Issue Date 03/11/02 07/31/02 09/03/02 09/19/02 11/15/02 See ECN Orig. of Change NSL DFP DFP DFP DFP NXR New Data Sheet Removed 15-ns bin Added 8-ns bin Change Cin - input capacitance -from 6 pF to 8 pF Change Cout -output capacitance from 8 pF to 10 pF Final data sheet. Added note 4 to “AC Test Loads and Waveforms” Removed 12 ns speed bin from product offering Included note #1 and 2 on page #2 Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Updated Ordering Information Table Updated Ordering Information Table Updated Package Diagram Added Sales, Solutions, and Legal Information Added Ordering Code Definitions. Added Acronyms and Units of Measure. Minor edits. Updated Selection Guide (Removed -10 column). Updated DC Electrical Characteristics (Removed -10 column). Updated AC Switching Characteristics (Removed -10 column). Updated in new template. Description of Change *F 2896044 03/19/2010 AJU *G 3097955 11/30/2010 PRAS *H 3086499 06/07/2011 AJU Document Number: 38-05254 Rev. *H Page 12 of 13 [+] Feedback CY7C1012AV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2002-2011. 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Document Number: 38-05254 Rev. *H Revised June 7, 2011 Page 13 of 13 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback