CY7C1018CV33

CY7C1018CV33 128K x 8 Static RAM Features • Pin- and function-compatible with CY7C1018BV33 • High speed — tAA = 10 ns • CMOS for optimum speed/power • Center power/ground pinout • Data retention at 2.0V • Automatic power-down when deselected • Easy memory expansion with CE and OE options • Available in Pb-free and non Pb-free 300-mil-wide 32-pin SOJ device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1018CV33 is available in a standard 300-mil-wide SOJ. Functional Description[1] The CY7C1018CV33 is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. This Logic Block Diagram Pin Configurations SOJ Top View A0 A1 A2 A3 CE I/O0 I/O1 VCC V SS I/O2 I/O3 WE A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 OE I/O7 I/O6 VSS VCC I/O5 I/O4 A12 A11 A10 A9 A8 I/O0 INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 I/O1 ROW DECODER I/O2 SENSE AMPS 128K x 8 ARRAY I/O3 I/O4 I/O5 I/O6 I/O7 CE WE OE COLUMN DECODER POWER DOWN Note: 1. For guidelines on SRAM system designs, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com. A9 A 10 A 11 A 12 A 13 A 14 A 15 A 16 Cypress Semiconductor Corporation Document #: 38-05131 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 3, 2006 [+] [+] Feedback CY7C1018CV33 Selection Guide -10 Maximum Access Time Maximum Operating Current Maximum Standby Current Comm’l Ind’l 5 10 90 -12 12 85 85 5 5 -15 15 80 Unit ns mA mA mA Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VCC Relative to GND[2] ... –0.5V to + 4.6V DC Voltage Applied to Outputs[6] in High-Z State .......................................–0.5V to VCC + 0.5V DC Input Voltage[2] .................................–0.5V to VCC + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA Operating Range Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 3.3V ± 10% 3.3V ± 10% Electrical Characteristics Over the Operating Range –10 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Test Conditions Min. 2.4 0.4 2.0 –0.3 GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Comm’l Ind’l 15 –1 –1 VCC + 0.3 0.8 +1 +1 90 2.0 –0.3 –1 –1 Max. Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 85 85 15 15 5 5 5 5 15 2.0 –0.3 –1 –1 Output HIGH Voltage VCC = Min., IOH = – 4.0 mA Output LOW Voltage VCC = Min., IOL = 8.0 mA Input HIGH Voltage Input LOW Voltage[2] Input Leakage Current Output Leakage Current VCC Operating Supply Current –12 Max. Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 80 –15 Max. Unit V V V V µA µA mA mA mA mA mA mA ISB1 ISB2 Automatic CE Max. VCC, CE > VIH Comm’l Power-down Current VIN > VIH or Ind’l VIN < VIL, f = fMAX —TTL Inputs Automatic CE Max. VCC, Comm’l Power-down Current CE > VCC – 0.3V, Ind’l —CMOS Inputs VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 Capacitance[3] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max. 8 8 Unit pF pF Notes: 2. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 3. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05131 Rev. *D Page 2 of 7 [+] [+] Feedback CY7C1018CV33 AC Test Loads and Waveforms[4] R 317 Ω 3.3V OUTPUT 30 pF R2 351Ω GND 3.0V 10% ALL INPUT PULSES 90% 90% 10% (a) High-Z characteristics: 3.3V OUTPUT 5 pF R2 351Ω R 317 Ω Rise Time: 1 V/ns (b) Fall Time: 1 V/ns (c) Switching Characteristics Over the Operating Range[5] -10 Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU[8] tPD[8] Write tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z OE HIGH to High-Z[6, 7] CE LOW to CE HIGH to Low-Z[7] High-Z[6, 7] 0 10 10 8 8 0 0 7 5 0 3 5 12 9 9 0 0 8 6 0 3 6 3 5 0 12 15 10 10 0 0 10 8 0 3 7 0 5 3 6 0 15 3 10 5 0 6 3 7 10 10 3 12 6 0 7 12 12 3 15 7 15 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Min. -12 Max. Min. -15 Max. Unit CE LOW to Power-up CE HIGH to Power-down Cycle[9, 10] Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE HIGH to WE LOW to Low-Z[7] High-Z[6, 7] Notes: 4. AC characteristics (except High-Z) for all speeds are tested using the Thèvenin load shown in Figure (a). High-Z characteristics are tested for all speeds using the test load shown in Figure (c). 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. 6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (d) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. This parameter is guaranteed by design and is not tested. 9. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. 10. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05131 Rev. *D Page 3 of 7 [+] [+] Feedback CY7C1018CV33 Switching Waveforms Read Cycle No. 1[11, 12] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[12, 13] ADDRESS tRC CE tACE OE tDOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tPU 50% tHZOE tHZCE DATA VALID tPD 50% ISB ICC HIGH IMPEDANCE Write Cycle No. 1 (CE Controlled)[14, 15] tWC ADDRESS tSCE CE tSA tSCE tAW tPWE WE tSD DATA I/O DATA VALID tHD tHA Notes: 11. Device is continuously selected. OE, CE = VIL. 12. WE is HIGH for Read cycle. 13. Address valid prior to or coincident with CE transition LOW. 14. Data I/O is high impedance if OE = VIH. 15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05131 Rev. *D Page 4 of 7 [+] [+] Feedback CY7C1018CV33 Switching Waveforms (continued) Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 15] tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA OE tSD DATA I/O NOTE 16 tHZOE DATAIN VALID tHD Write Cycle No. 3 (WE Controlled, OE LOW)[10, 15] tWC ADDRESS tSCE CE tAW tSA WE tSD DATA I/O NOTE 16 tHZWE DATA VALID tLZWE tHD tPWE tHA Truth Table CE H L L L OE X L X H WE X H L H High-Z Data Out Data In High-Z I/O0–I/O7 Power-down Read Write Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Note: 16. During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05131 Rev. *D Page 5 of 7 [+] [+] Feedback CY7C1018CV33 Ordering Information Speed (ns) 10 12 15 Ordering Code CY7C1018CV33-10VC CY7C1018CV33-12VC CY7C1018CV33-12VXI CY7C1018CV33-15VXC Package Diagram 51-85041 Package Type 32-lead 300-mil Molded SOJ 32-lead 300-mil Molded SOJ 32-lead 300-mil Molded SOJ (Pb-Free) 32-lead 300-mil Molded SOJ (Pb-Free) Operating Range Commercial Commercial Industrial Commercial Package Diagram 32-lead (300-mil) Molded SOJ (51-85041) 51-85041-*A All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05131 Rev. *D Page 6 of 7 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] [+] Feedback CY7C1018CV33 Document History Page Document Title: CY7C1018CV33 128K x 8 Static RAM Document Number: 38-05131 REV. ** *A *B *C *D ECN NO. 109426 113432 115046 116476 493543 Issue Date 12/14/01 04/10/02 05/30/02 09/16/02 See ECN Orig. of Change HGK NSL HGK CEA NXR New Data Sheet AC Test Loads split based on speed ICC and ISB1 modified Add applications foot note on data sheet, pg 1 Added Industrial Operating Range Removed 8 ns speed bin from Product offering Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Removed IOS parameter from DC Electrical Characteristics table Updated the Ordering Information Table Description of Change Document #: 38-05131 Rev. *D Page 7 of 7 [+] [+] Feedback