CY7C1019D

CY7C1019D 1-Mbit (128K x 8) Static RAM Features • Pin- and function-compatible with CY7C1019B • High speed — tAA = 10 ns • Low active power — ICC = 80 mA @ 10 ns • Low CMOS standby power — ISB2 = 3 mA • 2.0V Data retention • Automatic power-down when deselected • CMOS for optimum speed/power • Center power/ground pinout • Easy memory expansion with CE and OE options • Functionally equivalent to CY7C1019B • Available in Pb-free 32-pin 400-Mil wide Molded SOJ and 32-pin TSOP II packages Functional Description [1] The CY7C1019D is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. This device has an automatic power-down feature that significantly reduces power consumption when deselected. The eight input and output pins (IO0 through IO7) are placed in a high-impedance state when: • Deselected (CE HIGH) • Outputs are disabled (OE HIGH) • When the write operation is active (CE LOW, and WE LOW). Write to the device by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight IO pins (IO0 through IO7) is then written into the location specified on the address pins (A0 through A16). Read from the device by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appears on the IO pins. Logic Block Diagram INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 CE WE OE IO0 IO1 ROW DECODER 128K x 8 ARRAY SENSE AMPS IO2 IO3 IO4 IO5 IO6 COLUMN DECODER POWER DOWN IO7 Note 1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com. A9 A10 A11 A12 A13 A14 A15 A16 Cypress Semiconductor Corporation Document #: 38-05464 Rev. *F • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised December 14, 2010 [+] Feedback CY7C1019D Pin Configuration SOJ/TSOPII Top View A0 A1 A2 A3 CE IO 0 IO 1 VCC V SS IO 2 IO 3 WE A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 OE IO 7 IO 6 VSS VCC IO 5 IO 4 A12 A11 A10 A9 A8 Selection Guide –10 (Industrial) Maximum Access Time Maximum Operating Current Maximum Standby Current 10 80 3 Unit ns mA mA Document #: 38-05464 Rev. *F Page 2 of 13 [+] Feedback CY7C1019D Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. –65C to +150C Ambient Temperature with Power Applied............................................. –55C to +125C Supply Voltage on VCC to Relative GND [2] ... –0.5V to +6.0V DC Voltage Applied to Outputs in High-Z State [2] ...................................–0.5V to VCC + 0.5V DC Input Voltage [2]................................–0.5V to VCC + 0.5V Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current .................................................... > 200 mA Operating Range Range Industrial Ambient Temperature –40C to +85C VCC 5V  0.5V Speed 10 ns Electrical Characteristics (Over the Operating Range) Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage [2] Test Conditions IOH = –4.0 mA IOL = 8.0 mA –10 (Industrial) Min 2.4 0.4 2.2 –0.5 VCC + 0.5 0.8 +1 +1 80 72 58 37 10 3 Max Unit V V V V A A mA mA mA mA mA mA Input Leakage Current Output Leakage Current VCC Operating Supply Current GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Max, IOUT = 0 mA, f = fmax = 1/tRC 100 MHz 83 MHz 66 MHz 40 MHz –1 –1 ISB1 ISB2 Automatic CE Power-Down Current—TTL Inputs Automatic CE Power-Down Current—CMOS Inputs Max VCC, CE > VIH VIN > VIH or VIN < VIL, f = fmax Max VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 Note 2. VIL (min) = –2.0V and VIH(max) = VCC + 1V for pulse durations of less than 5 ns. Document #: 38-05464 Rev. *F Page 3 of 13 [+] Feedback CY7C1019D Capacitance [3] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max 6 8 Unit pF pF Thermal Resistance [3] Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 400-Mil Wide SOJ 56.29 38.14 TSOP II 62.22 21.43 Unit C/W C/W AC Test Loads and Waveforms [4] ALL INPUT PULSES 90% 10% 90% 10% Z = 50 OUTPUT 50  * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 1.5V 3.0V 30 pF* GND Rise Time: 3 ns (a) (b) Fall Time: 3 ns High-Z characteristics: 5V OUTPUT INCLUDING JIG AND SCOPE 5 pF R2 255 R1 480 (c) Notes 3. Tested initially and after any design or process changes that may affect these parameters. 4. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load shown in Figure (c). Document #: 38-05464 Rev. *F Page 4 of 13 [+] Feedback CY7C1019D Switching Characteristics (Over the Operating Range) [5] Parameter Read Cycle tpower [6] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD [9] [9] Description –10 (Industrial) Min 100 10 10 3 10 5 0 5 3 5 0 10 10 7 7 0 0 7 6 0 3 5 Max Unit VCC(typical) to the first access Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z CE LOW to Low Z CE HIGH to High Z [7, 8] [8] [7, 8] s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CE LOW to Power-Up CE HIGH to Power-Down Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High Z [8] [7, 8] Write Cycle [10, 11] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Notes 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (c) of “AC Test Loads and Waveforms [4]” on page 4. Transition is measured when the outputs enter a high impedance state. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 9. This parameter is guaranteed by design and is not tested. 10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 11. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05464 Rev. *F Page 5 of 13 [+] Feedback CY7C1019D Data Retention Characteristics (Over the Operating Range) Parameter VDR ICCDR tCDR [3] tR [12] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Conditions VCC = VDR = 2.0V, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V Min 2.0 Max 3 Unit V mA ns ns 0 tRC Data Retention Waveform DATA RETENTION MODE VCC CE 4.5V tCDR VDR > 2V 4.5V tR Switching Waveforms Read Cycle No. 1 (Address Transition Controlled) [13, 14] tRC RC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Read Cycle No. 2 (OE Controlled) [14, 15] ADDRESS tRC CE tACE OE tDOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tPU 50% tHZOE tHZCE DATA VALID tPD 50% ISB HIGH IMPEDANCE ICC Notes 12. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s. 13. Device is continuously selected. OE, CE = VIL. 14. WE is HIGH for Read cycle. 15. Address valid prior to or coincident with CE transition LOW. Document #: 38-05464 Rev. *F Page 6 of 13 [+] Feedback CY7C1019D Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled) [16, 17] tWC ADDRESS tSCE CE tSA tAW tPWE WE tSD DATA IO DATA VALID tHD tSCE tHA Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [16, 17] tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA OE tSD DATA IO NOTE 18 tHZOE DATAIN VALID tHD Notes 16. Data IO is high impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 18. During this period the IOs are in the output state and input signals should not be applied. Document #: 38-05464 Rev. *F Page 7 of 13 [+] Feedback CY7C1019D Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) [11, 17] tWC ADDRESS tSCE CE tAW tSA WE tSD DATA IO NOTE 18 tHZWE DATA VALID tLZWE tHD tPWE tHA Truth Table CE H L L L OE X L X H WE X H L H High Z Data Out Data In High Z IO0–IO7 Power-Down Read Write Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Document #: 38-05464 Rev. *F Page 8 of 13 [+] Feedback CY7C1019D Ordering Information Speed (ns) 10 Ordering Code CY7C1019D-10VXI CY7C1019D-10ZSXI Package Diagram 51-85033 51-85095 Package Type 32-pin (400-Mil) Molded SOJ (Pb-free) 32-pin TSOP Type II (Pb-free) Operating Range Industrial Ordering Code Definitions CY 7 C 1 01 9 D - 10 XXX I Temperature Range: I = Industrial Package Type: XXX = VX or ZSX VX = 32-pin Molded SOJ (Pb-free) ZSX = 32-pin TSOP Type II (Pb-free) Speed: 10 ns D = C9, 90 nm Technology 9 = Data width × 8-bits 01 = 1-Mbit density 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS 7 = SRAM CY = Cypress Please contact your local Cypress sales representative for availability of these parts. Document #: 38-05464 Rev. *F Page 9 of 13 [+] Feedback CY7C1019D Package Diagrams Figure 1. 32-pin (400-Mil) Molded SOJ (51-85033) 51-85033 *C Document #: 38-05464 Rev. *F Page 10 of 13 [+] Feedback CY7C1019D Package Diagrams (continued) Figure 2. 32-pin Thin Small Outline Package Type II (51-85095) 51-85095 *A All product or company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05464 Rev. *F Page 11 of 13 [+] Feedback CY7C1019D Document History Page Document Title: CY7C1019D, 1-Mbit (128K x 8) Static RAM Document Number: 38-05464 REV. ** *A *B ECN NO. 201560 233715 262950 Issue Date See ECN See ECN See ECN Orig. of Change SWI RKF RKF Description of Change Advance Information data sheet for C9 IPP DC parameters are modified as per EROS (Spec # 01-2165) Pb-free offering in the Ordering Information Added Tpower Spec in Switching Characteristics table Added Data Retention Characteristics table and waveforms Shaded Ordering Information Reduced Speed bins to -10 and -12 ns Converted from Preliminary to Final Removed Commercial Operating range Removed 12 ns speed bin Added ICC values for the frequencies 83MHz, 66MHz and 40MHz Updated Thermal Resistance table Updated Ordering Information Table Changed Overshoot spec from VCC+2V to VCC+1V in footnote #2 Changed ICC spec from 60 mA to 80 mA for 100MHz, 55 mA to 72 mA for 83MHz, 45 mA to 58 mA for 66MHz, 30 mA to 37 mA for 40MHz Added Ordering Code Definitions. Updated Package Diagrams. *C *D 307598 520647 See ECN See ECN RKF VKN *E *F 802877 3110052 See ECN 12/14/2010 VKN AJU Document #: 38-05464 Rev. *F Page 12 of 13 [+] Feedback CY7C1019D Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 Document #: 38-05464 Rev. *F Page 13 of 13 © Cypress Semiconductor Corporation, 2004-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback