CY7C1020D-10VXIT

CY7C1020D 512-Kbit (32 K × 16) Static RAM 512-Kbit (32 K × 16) Static RAM Features ■ Deselected (CE HIGH) ■ Pin- and function-compatible with CY7C1020B ■ Outputs are disabled (OE HIGH) ■ High speed ■ BHE and BLE are disabled (BHE, BLE HIGH) ❐ tAA ■ When the write operation is active (CE LOW, and WE LOW) ■ Write to the device by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7), is written into the location specified on the address pins (A0 through A14). If Byte High Enable (BHE) is LOW, then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A14). Low active power ❐ ICC ■ = 10 ns = 80 mA @ 10 ns Low complementary metal oxide semiconductor (CMOS) standby power ❐ ISB2 = 3 mA ■ 2.0 V data retention ■ Automatic power-down when deselected ■ CMOS for optimum speed/power ■ Independent control of upper and lower bits ■ Available in Pb-free 44-pin 400-Mil wide Molded SOJ and 44-pin thin small outline package (TSOP) II packages Reading from the device by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from memory appears on IO8 to IO15. See the “Truth Table” on page 11 for a complete description of read and write modes. The CY7C1020D device is suitable for interfacing with processors that have TTL I/P levels. It is not suitable for processors that require CMOS I/P levels. Please see Electrical Characteristics on page 4 for more details and suggested alternatives. Functional Description The CY7C1020D [1] is a high-performance CMOS static RAM organized as 32,768 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected.The input and output pins (IO0 through IO15) are placed in a high-impedance state when: Logic Block Diagram SENSE AMPS DATA IN DRIVERS ROW DECODER A7 A6 A5 A4 A3 A2 A1 A0 For a complete list of related documentation, click here. 32K x 16 RAM Array IO0–IO7 IO8–IO15 BHE WE CE OE BLE A14 A12 A13 A8 A9 A10 A11 COLUMN DECODER Note 1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com. Cypress Semiconductor Corporation Document Number: 38-05463 Rev. *J • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 28, 2014 CY7C1020D Contents Pin Configurations ........................................................... 3 Selection Guide ................................................................ 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 Switching Characteristics ................................................ 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 11 Document Number: 38-05463 Rev. *J Ordering Information ...................................................... 12 Ordering Code Definitions ......................................... 12 Package Diagrams .......................................................... 13 Acronyms ........................................................................ 15 Document Conventions ................................................. 15 Units of Measure ....................................................... 15 Document History Page ................................................. 16 Sales, Solutions, and Legal Information ...................... 17 Worldwide Sales and Design Support ....................... 17 Products .................................................................... 17 PSoC® Solutions ...................................................... 17 Cypress Developer Community ................................. 17 Technical Support ..................................................... 17 Page 2 of 17 CY7C1020D Pin Configurations Figure 1. 44-pin SOJ/TSOP II pinout (Top View) [2] NC A3 A2 A1 A0 CE IO0 IO1 IO2 IO3 VCC VSS IO4 IO5 IO6 IO7 WE A4 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE IO15 IO14 IO13 IO12 VSS VCC IO11 IO10 IO9 IO8 NC A8 A9 A10 A11 NC Selection Guide Description -10 (Industrial) Unit Maximum access time 10 ns Maximum operating current 80 mA Maximum CMOS standby current 3 mA Note 2. NC pins are not connected on the die. Document Number: 38-05463 Rev. *J Page 3 of 17 CY7C1020D DC input voltage [3] ............................. –0.5 V to VCC + 0.5 V Maximum Ratings Current into outputs (LOW) ........................................ 20 mA Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Static discharge voltage (per MIL-STD-883, Method 3015) ........................... >2001 V Storage temperature ................................ –65 C to +150 C Latch-up current ..................................................... >200 mA Ambient temperature with power applied .......................................... –55 C to +125 C Operating Range Supply voltage on VCC to Relative GND [3] ...............................–0.5 V to +6.0 V DC voltage applied to outputs in High Z State [3] ................................ –0.5 V to VCC + 0.5 V Range Ambient Temperature VCC Speed Industrial –40 °C to +85 °C 5 V  0.5 V 10 ns Electrical Characteristics Over the Operating Range Parameter VOH Description Output HIGH voltage -10 (Industrial) Test Conditions IOH = –4.0 mA IOH = –0.1 mA Min Max 2.4 – – 3.4 Unit V [4] VOL Output LOW voltage IOL = 8.0 mA – 0.4 V VIH Input HIGH voltage – 2.2 VCC + 0.5 V VIL Input LOW voltage [3] – –0.5 0.8 V IIX Input load current GND < VI < VCC –1 +1 A IOZ Output leakage current GND < VI < VCC, output disabled ICC VCC operating supply current VCC = Max, IOUT = 0 mA, f = fmax = 1/tRC –1 +1 A 100 MHz – 80 mA 83 MHz – 72 mA 66 MHz – 58 mA 40 MHz – 37 mA ISB1 Automatic CE power-down current – TTL inputs Max VCC, CE > VIH VIN > VIH or VIN < VIL, f = fmax – 10 mA ISB2 Automatic CE Power-Down current – CMOS inputs Max VCC, CE > VCC – 0.3 V, VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0 – 3 mA Note 3. VIL (min) = –2.0 V and VIH(max) = VCC + 1 V for pulse durations of less than 5 ns. 4. Please note that the maximum VOH limit does not exceed minimum CMOS VIH of 3.5V. If you are interfacing this SRAM with 5V legacy processors that require a minimum VIH of 3.5V, please refer to Application Note AN6081 for technical details and options you may consider. Document Number: 38-05463 Rev. *J Page 4 of 17 CY7C1020D Capacitance Parameter [5] Description CIN Input capacitance COUT Output capacitance Test Conditions Max Unit 8 pF 8 pF SOJ TSOP II Unit 59.52 53.91 C/W 36.75 21.24 C/W TA = 25 C, f = 1 MHz, VCC = 5.0 V Thermal Resistance Parameter [5] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms [6] ALL INPUT PULSES 3.0V Z = 50 90% OUTPUT 50  * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 30 pF* 90% 10% 10% GND 1.5V Rise Time: 3 ns (a) (b) Fall Time: 3 ns High-Z characteristics: R1 480 5V OUTPUT INCLUDING JIG AND SCOPE R2 255 5 pF (c) Notes 5. Tested initially and after any design or process changes that may affect these parameters. 6. AC characteristics (except High-Z) are tested using the load conditions shown in Figure 2 (a). High-Z characteristics are tested for all speeds using the test load shown in Figure 2 (c). Document Number: 38-05463 Rev. *J Page 5 of 17 CY7C1020D Data Retention Characteristics Over the Operating Range Parameter Description Conditions Min Max Unit 2.0  V VDR VCC for data retention – ICCDR Data retention current VCC = VDR = 2.0 V, CE > VCC – 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V  3 mA tCDR [7] Chip deselect to data retention time – 0  ns tR [8] Operation recovery time – tRC  ns Data Retention Waveform Figure 3. Data Retention Waveform DATA RETENTION MODE VCC 4.5V VDR > 2V tCDR 4.5V tR CE Notes 7. Tested initially and after any design or process changes that may affect these parameters. 8. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s. Document Number: 38-05463 Rev. *J Page 6 of 17 CY7C1020D Switching Characteristics Over the Operating Range Parameter [9] Description -10 (Industrial) Min Max Unit Read Cycle tpower [10] VCC(typical) to the first access 100  s tRC Read cycle time 10  ns tAA Address to data valid  10 ns tOHA Data hold from address change 3  ns tACE CE LOW to data valid  10 ns tDOE OE LOW to data valid  5 ns [12] 0 tLZOE OE LOW to Low Z [11, 12] tHZOE OE HIGH to High Z tLZCE CE LOW to Low Z [12] tHZCE CE HIGH to High Z [11, 12] ns  5 ns 3  ns  5 ns tPU [13] CE LOW to power-up 0  ns tPD [13] CE HIGH to power-down  10 ns 5 ns tDBE Byte enable to data valid tLZBE Byte enable to Low Z 0  ns Byte disable to High Z  5 ns tHZBE Write Cycle [14, 15] tWC Write cycle time 10  ns tSCE CE LOW to write end 7  ns tAW Address set-up to write end 7  ns tHA Address hold from write end 0  ns tSA Address set-up to write start 0  ns tPWE WE pulse width 7  ns tSD Data set-up to write end 6  ns tHD Data hold from write end 0  ns tLZWE WE HIGH to Low Z [12] 3  ns  5 ns 7  ns [11, 12] tHZWE WE LOW to High Z tBW Byte enable to end of write Notes 9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 10. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 11. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of Figure 2 on page 5. Transition is measured when the outputs enter a high impedance state. 12. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 13. This parameter is guaranteed by design and is not tested. 14. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a write and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 15. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) should be equal to the sum of tHZWE and tSD. Document Number: 38-05463 Rev. *J Page 7 of 17 CY7C1020D Switching Waveforms Figure 4. Read Cycle No.1 (Address Transition Controlled) [16, 17] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 5. Read Cycle No.2 (OE Controlled) [17, 18] ADDRESS tRC CE tACE OE tHZOE tDOE BHE, BLE tLZOE tHZCE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZBE DATA VALID HIGH IMPEDANCE tPD tPU 50% 50% ICC ISB Notes 16. Device is continuously selected. OE, CE, BHE and/or BLE = VIL. 17. WE is HIGH for read cycle. 18. Address valid prior to or coincident with CE transition LOW. Document Number: 38-05463 Rev. *J Page 8 of 17 CY7C1020D Switching Waveforms(continued) Figure 6. Write Cycle No. 1 (CE Controlled) [19, 20] tWC ADDRESS CE tSA tSCE tAW tHA tPWE WE tBW BHE, BLE tSD tHD DATA IO Figure 7. Write Cycle No. 2 (BLE or BHE Controlled) [19, 20] tWC ADDRESS BHE, BLE tSA tBW tAW tHA tPWE WE tSCE CE tSD tHD DATA IO Notes 19. Data IO is high impedance if OE or BHE and/or BLE= VIH. 20. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document Number: 38-05463 Rev. *J Page 9 of 17 CY7C1020D Switching Waveforms(continued) Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [21, 22] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD DATA IO tLZWE Notes 21. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) should be equal to the sum of tHZWE and tSD. 22. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document Number: 38-05463 Rev. *J Page 10 of 17 CY7C1020D Truth Table CE OE WE H X X X X High Z High Z Power-down Standby (ISB) L L H L L Data out Data out Read – All bits Active (ICC) L H Data out High Z Read – Lower bits only Active (ICC) H L High Z Data out Read – Upper bits only Active (ICC) L L Data in Data in Write – All bits Active (ICC) L H Data in High Z Write – Lower bits only Active (ICC) H L High Z Data in Write – Upper bits only Active (ICC) L X L BLE BHE IO0–IO7 IO8–IO15 Mode Power L H H X X High Z High Z Selected, outputs disabled Active (ICC) L X X H H High Z High Z selected, outputs disabled Active (ICC) Document Number: 38-05463 Rev. *J Page 11 of 17 CY7C1020D Ordering Information Speed (ns) 10 Package Diagram Ordering Code Package Type CY7C1020D-10VXI 51-85082 44-pin SOJ (400 Mils) Pb-free CY7C1020D-10ZSXI 51-85087 44-pin TSOP (Type II) Pb-free Operating Range Industrial Please contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions CY 7 C 1 02 0 D - 10 XX X I Temperature Range: I = Industrial Pb-free Package Type: XX = V or ZS V = 44-pin Molded SOJ ZS = 44-pin TSOP Type II Speed: 10 ns Process Technology: D = C9, 90 nm Technology Data width: 0 = × 16-bits Density: 02 = 512-Kbit density Family Code: 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 38-05463 Rev. *J Page 12 of 17 CY7C1020D Package Diagrams Figure 9. 44-pin SOJ (400 Mils) V44.4 Package Outline, 51-85082 51-85082 *E Document Number: 38-05463 Rev. *J Page 13 of 17 CY7C1020D Package Diagrams(continued) Figure 10. 44-pin TSOP Z44-II Package Outline, 51-85087 51-85087 *E Document Number: 38-05463 Rev. *J Page 14 of 17 CY7C1020D Acronyms Acronym Document Conventions Description Units of Measure BGA Ball Grid Array CMOS Complementary Metal Oxide Semiconductor °C degree Celsius FBGA Fine-Pitch Ball Gird Array MHz megahertz I/O Input/Output A microampere SRAM Static Random Access Memory mA milliampere TSOP Thin Small Outline Package ns nanosecond TTL Transistor-Transistor Logic  ohm pF picofarad V volt W watt Document Number: 38-05463 Rev. *J Symbol Unit of Measure Page 15 of 17 CY7C1020D Document History Page Document Title: CY7C1020D, 512-Kbit (32 K × 16) Static RAM Document Number: 38-05463 Rev. ECN No. Issue Date Orig. of Change ** 201560 See ECN SWI Advance Data sheet for C9 IPP *A 233695 See ECN RKF 1) DC parameters modified as per EROS (Spec # 01-0216) 2) Pb-free Offering in the ‘Ordering Information’ *B 263769 See ECN RKF 1) Corrected pin #18 on SOJ/TSOPII Pinout (Page #1) from A15 to A4 2) Changed IO1 - IO16 to IO0 - IO15 on the Pin-out diagram 3) Added Tpower Spec in Switching Characteristics Table 4) Added Data Retention Characteristics Table and Waveforms 5) Shaded ‘Ordering Information’ *C 307594 See ECN RKF Reduced Speed bins to –10, –12 and –15 ns *D 560995 See ECN VKN Converted from Preliminary to Final Removed Commercial Operating range Removed 12 ns speed bin Added ICC values for the frequencies 83MHz, 66MHz and 40MHz Updated Thermal Resistance table Updated Ordering Information Table Changed Overshoot spec from VCC+2V to VCC+1V in footnote #3 *E 802877 See ECN VKN Changed ICC specs from 60 mA to 80 mA for 100MHz, 55 mA to 72 mA for 83MHz, 45 mA to 58 mA for 66MHz, 30 mA to 37 mA for 40MHz *F 3109992 12/14/2010 AJU Added Ordering Code Definitions. Updated Package Diagrams. *G 3219056 04/07/2011 PRAS Added TOC Added Acronyms and Units of Measure table. Updated Datasheet as per template. *H 4033925 06/19/2013 MEMJ Updated Functional Description. Updated Electrical Characteristics: Added one more Test Condition “IOH = –0.1mA” for VOH parameter and added maximum value corresponding to that Test Condition. Added Note 4 and referred the same note in maximum value for VOH parameter corresponding to Test Condition “IOH = –0.1mA”. Updated Package Diagrams: spec 51-85082 – Changed revision from *C to *E. spec 51-85087 – Changed revision from *C to *E. *I 4385769 05/21/2014 MEMJ No technical updates. Completing Sunset Review. *J 4576526 11/21/2014 MEMJ Added related documentation hyperlink in page 1. Document Number: 38-05463 Rev. *J Description of Change Page 16 of 17 CY7C1020D Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. PSoC® Solutions Products Automotive cypress.com/go/automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2010-2014. 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Document Number: 38-05463 Rev. *J Revised November 28, 2014 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 17 of 17