CY7C1020DV33-10ZSXIT

CY7C1020DV33 512 K (32 K x 16) Static RAM Features ■ Pin-and function-compatible with CY7C1020CV33 ■ High speed ❐ tAA = 10 ns ■ Low active power ❐ ICC = 60 mA @ 10 ns Writing to the device is accomplished by taking chip enable (CE) and write enable (WE) inputs LOW. If byte low enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A14). If byte high enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A14). Reading from the device is accomplished by taking chip enable (CE) and output enable (OE) LOW while forcing the write enable (WE) HIGH. If byte low enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If byte high enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. ■ Low CMOS standby power ❐ ISB2 = 3 mA ■ 2.0 V Data retention ■ Automatic power-down when deselected ■ CMOS for optimum speed/power ■ Independent control of upper and lower bits ■ Available in Pb-free 44-pin 400-Mil wide Molded SOJ and 44-pin TSOP II packages Functional Description The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1020DV33 is available in Pb-free 44-pin 400-Mil wide Molded SOJ and 44-pin TSOP II packages. The CY7C1020DV33 is a high-performance CMOS static RAM organized as 32,768 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. For a complete list of related documentation, click here. Logic Block Diagram Pin Configuration[1] SOJ/TSOP II Top View SENSE AMPS A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS 32K x 16 RAM Array I/O0–I/O7 I/O8–I/O15 BHE WE CE OE BLE A14 A12 A13 A8 A9 A10 A11 COLUMN DECODER NC A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A4 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC Notes 1. NC pins are not connected on the die. Cypress Semiconductor Corporation Document Number: 38-05461 Rev. *I • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 19, 2014 CY7C1020DV33 Selection Guide –10 (Industrial) Unit Maximum access time 10 ns Maximum operating current 60 mA Maximum CMOS standby current 3 mA DC input voltage[2] ............................... –0.5 V to VCC + 0.5 V Maximum Ratings Current into outputs (LOW) ......................................... 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static discharge voltage........................................... > 2001 V (per MIL-STD-883, Method 3015) Storage temperature ................................ –65 C to +150 C Latch-up current ..................................................... > 200 mA Ambient temperature with power applied ........................................... –55 C to +125 C Operating Range Supply voltage on VCC to Relative GND[2] ...–0.5 V to +4.6 V DC voltage applied to outputs in High-Z State[2] .................................. –0.5 V to VCC + 0.5 V Range Ambient Temperature VCC Speed Industrial –40 °C to +85 °C 3.3 V  0.3 V 10 ns Electrical Characteristics Over the Operating Range Parameter Description –10 (Industrial) Test Conditions VOH Output HIGH voltage VCC = Min., IOH = –4.0 mA VOL Output LOW voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH voltage Min. Unit Max. 2.4 V 0.4 V 2.0 VCC + 0.3 V VIL Input LOW 0.3 0.8 V IIX Input Load current GND < VI < VCC 1 +1 A IOZ Output leakage current GND < VI < VCC, Output Disabled 1 +1 A ICC VCC operating supply current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC 100 MHz 60 mA 83 MHz 55 mA 66 MHz 45 mA 40 MHz 30 mA voltage[2] ISB1 Automatic CE Power-down Current—TTL Inputs Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX 10 mA ISB2 Automatic CE Power-down Current—CMOS Inputs Max. VCC, CE > VCC – 0.3 V, VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0 3 mA Notes 2. VIL (min.) = –2.0 V and VIH(max) = VCC + 1 V for pulse durations of less than 5 ns. Document Number: 38-05461 Rev. *I Page 2 of 13 CY7C1020DV33 Capacitance[3] Parameter Description CIN Input capacitance COUT Output capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3 V Max. Unit 8 pF 8 pF Thermal Resistance[3] Parameter Description JA Thermal resistance (Junction to Ambient) JC Thermal resistance (Junction to Case) Test Conditions Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit board SOJ TSOP II Unit 59.52 53.91 C/W 36.75 21.24 C/W AC Test Loads and Waveforms[4] ALL INPUT PULSES 3.0 V Z = 50 90% OUTPUT 50  * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT GND 30 pF* 90% 10% 10% 1.5 V Rise Time: 1 V/ns (a) (b) Fall Time: 1 V/ns High-Z characteristics: R 317 3.3 V OUTPUT R2 351 5 pF (c) Notes 3. Tested initially and after any design or process changes that may affect these parameters. 4. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load shown in Figure (c). Document Number: 38-05461 Rev. *I Page 3 of 13 CY7C1020DV33 Switching Characteristics Over the Operating Range [5] Parameter Description –10 (Industrial) Min. Max. Unit Read Cycle tpower[6] VCC(typical) to the first access 100 s tRC Read cycle time 10 ns tAA Address to data valid tOHA Data Hold from Address Change 10 3 ns ns tACE CE LOW to data valid 10 ns tDOE OE LOW to data valid 5 ns tLZOE OE LOW to Low-Z[7] tHZOE OE HIGH to CE LOW to Low-Z[7] tHZCE CE HIGH to High-Z[7, 8] tPU[9] tPD[9] CE LOW to Power-up tDBE Byte enable to data valid tLZBE Byte enable to low-Z tLZCE ns 5 3 0 ns ns 10 5 0 Byte disable to high-Z ns ns 5 CE HIGH to Power-down tHZBE Write Cycle 0 High-Z[7, 8] ns ns ns 5 ns [10, 11] tWC Write cycle time 10 ns tSCE CE LOW to write end 8 ns tAW Address set-up to write end 8 ns tHA Address hold from write end 0 ns tSA Address set-up to write start 0 ns tPWE WE pulse width 7 ns tSD Data set-up to write end 5 ns tHD Data hold from write end 0 ns 3 ns tLZWE WE HIGH to Low-Z [7] High-Z[7, 8] tHZWE WE LOW to tBW Byte enable to end of write 5 7 ns ns Notes 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V. 6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed 7. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (c) of AC Test Loads. Transition is measured when the outputs enter a high impedance state. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 9. This parameter is guaranteed by design and is not tested. 10. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. 11. The minimum write cycle time for Write Cycle 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 38-05461 Rev. *I Page 4 of 13 CY7C1020DV33 Data Retention Characteristics (Over the Operating Range) Parameter Description Conditions VDR VCC ICCDR Data retention current tCDR [3] Chip deselect to data retention time tR[12] Operation recovery time Min. Max. Unit 2.0 V VCC = VDR = 2.0 V, CE > VCC – 0.3 V, Industrial VIN > VCC – 0.3 V or VIN < 0.3 V 3 mA 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE 3.0 V VCC VDR > 2 V tCDR 3.0 V tR CE Switching Waveforms Read Cycle No. 1 (Address Transition Controlled)[13, 14] tRC RC ADDRESS tAA tOHA DATA I/O PREVIOUS DATA VALID DATA OUT VALID Read Cycle No. 2 (OE Controlled)[14, 15] ADDRESS tRC CE tACE OE tHZOE tDOE tLZOE BHE, BLE tHZCE tDBE tLZBE DATA I/O HIGH IMPEDANCE tHZBE DATA OUT VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU 50% ICC 50% ISB Notes: 12. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s. 13. Device is continuously selected. OE, CE, BHE and/or BLE = VIL. 14. WE is HIGH for Read cycle. 15. Address valid prior to or coincident with CE transition LOW. Document Number: 38-05461 Rev. *I Page 5 of 13 CY7C1020DV33 Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[16, 17] tWC ADDRESS tSA tSCE CE tAW tHA tPWE WE tBW BHE, BLE tSD tHD DATA IN VALID DATA I/O Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS tSA tBW BHE, BLE tAW tHA tPWE WE tSCE CE tSD DATA I/O tHD DATA IN VALID Notes: 16. Data I/O is high impedance if OE or BHE and/or BLE = VIH. 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document Number: 38-05461 Rev. *I Page 6 of 13 CY7C1020DV33 Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD DATA IN VALID DATA I/O tLZWE Truth Table CE OE WE H X X X X High-Z High-Z Power-down Standby (ISB) L L H L L Data Out Data Out Read—All bits Active (ICC) L H Data Out High-Z Read—Lower bits only Active (ICC) H L High-Z Data Out Read—Upper bits only Active (ICC) L L Data In Data In Write—All bits Active (ICC) L H Data In High-Z Write—Lower bits only Active (ICC) H L High-Z Data In Write—Upper bits only Active (ICC) L X L BLE BHE I/O0–I/O7 I/O8–I/O15 Mode Power L H H X X High-Z High-Z Selected, Outputs Disabled Active (ICC) L X X H H High-Z High-Z Selected, Outputs Disabled Active (ICC) Document Number: 38-05461 Rev. *I Page 7 of 13 CY7C1020DV33 Ordering Information Speed (ns) 10 Ordering Code Package Name CY7C1020DV33-10ZSXI 51-85087 Package Type 44-pin TSOP Type II (Pb-free) Operating Range Industrial Ordering Code Definitions CY 7 C 1 02 0 D V33 - XX XX X Temperature Range: X = I or E I = Industrial; E = Automotive Package Type: XX = VX or ZSX VX = 44-pin Molded SOJ (Pb-free) ZSX = 44-pin TSOP Type II (Pb-free) Speed: XX = 10 ns or 12 ns V33 = Voltage range (3 V to 3.6 V) D = C9, 90 nm Technology 0 = Data width × 16-bits 02 = 512-Kbit density 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS 7 = SRAM CY = Cypress Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Document Number: 38-05461 Rev. *I Page 8 of 13 CY7C1020DV33 Package Diagrams Figure 1. 44-pin (400-Mil) Molded SOJ (51-85082) 51-85082 *E Document Number: 38-05461 Rev. *I Page 9 of 13 CY7C1020DV33 Package Diagrams (continued) Figure 2. 44-Pin Thin Small Outline Package Type II (51-85087) 51-85087 *E Document Number: 38-05461 Rev. *I Page 10 of 13 CY7C1020DV33 Acronyms Acronym Description BHE byte high enable BLE byte low enable CE chip enable CMOS complementary metal oxide semiconductor I/O input/output OE output enable SRAM static random access memory TSOP thin small outline package WE write enable Document Conventions Units of Measure Symbol Unit of Measure °C degrees Celsius A microamperes mA milliamperes MHz megahertz ns nanoseconds pF picofarads V volts  ohms W watts Document Number: 38-05461 Rev. *I Page 11 of 13 CY7C1020DV33 Document History Page Document Title: CY7C1020DV33, 512 K (32 K x 16) Static RAM Document Number: 38-05461 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 201560 See ECN SWI Advance Information data sheet for C9 IPP *A 233695 See ECN RKF DC parameters modified as per EROS (Spec # 01-02165) Pb-free Offering in Ordering Information *B 262950 See ECN RKF Changed I/O1 – I/O16 to I/O0 – I/O15 Added Data Retention Characteristics table Added Tpower spec in Switching Characteristics table Added 44-SOJ package diagram Shaded Ordering Information *C 307596 See ECN RKF Reduced Speed bins to –8 and –10 ns *D 560995 See ECN VKN Converted from Preliminary to Final Removed Commercial operating range Removed 8 ns speed bin Added Automotive information Added ICC values for the frequencies 83MHz, 66MHz and 40MHz Updated Thermal Resistance table Updated Ordering Information table Changed Overshoot spec from VCC+2 V to VCC+1 V in footnote #4 *E 2898399 03/24/2010 AJU Updated Package Diagrams *F 3109992 12/14/2010 AJU Added Ordering Code Definitions. *G 3424450 10/28/2011 TAVA Updated footnotes Updated Selection Guide, Operating Range, Electrical Characteristics Over the Operating Range, Switching Characteristics Over the Operating Range [5], Data Retention Characteristics (Over the Operating Range), Switching Waveforms, and Ordering Information. Updated Package Diagrams Added Acronyms, and Document Conventions *H 3861347 01/08/2013 TAVA Updated Ordering Information (Updated part numbers). Updated Package Diagrams: spec 51-85082 – Changed revision from *D to *E. spec 51-85087 – Changed revision from *D to *E. *I 4574311 11/19/2014 TAVA Added related documentation hyperlink in page 1. Added note 11 in Switching Characteristics Over the Operating Range [5]. Added note reference in the Switching Characteristics table. Document Number: 38-05461 Rev. *I Page 12 of 13 CY7C1020DV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products Automotive Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive Clocks & Buffers cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory cypress.com/go/memory Optical & Image Sensing cypress.com/go/image PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2008-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. 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Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05461 Rev. *I Revised November 19, 2014 All product and company names mentioned in this document may be the trademarks of their respective holders. Page 13 of 13