CY7C1021CV33-10ZI

CY7C1021CV33 1-Mbit (64K x 16) Static RAM Features • Temperature Ranges — Commercial: 0°C to 70°C — Industrial: –40°C to 85°C — Automotive-A: –40°C to 85°C — Automotive-E: –40°C to 125°C • Pin- and function-compatible with CY7C1021BV33 • High speed — tAA = 8 ns (Commercial & Industrial) — tAA = 12 ns (Automotive) • CMOS for optimum speed/power • Low active power: 345 mW (max.) • Automatic power-down when deselected • Independent control of upper and lower bits • Available in Pb-free and non Pb-free 44-pin 400-Mil SOJ 44-pin TSOP II and 48-ball FBGA packages Functional Description[1] The CY7C1021CV33 is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A15). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O9 to I/O16. See the truth table at the end of this data sheet for a complete description of Read and Write modes. The input/output pins (I/O1 through I/O16) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a Write operation (CE LOW, and WE LOW). The CY7C1021CV33 is available in 44-pin 400-Mil wide SOJ, 44-pin TSOP II and 48-ball FBGA packages. Logic Block Diagram DATA IN DRIVERS A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER 64K x 16 RAM Array SENSE AMPS I/O1–I/O8 I/O9–I/O16 COLUMN DECODER BHE WE CE OE BLE Note: 1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. A8 A9 A10 A11 A12 A13 A14 A15 Cypress Semiconductor Corporation Document #: 38-05132 Rev. *G • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 6, 2006 [+] [+] Feedback CY7C1021CV33 Selection Guide -8 Maximum Access Time Maximum Operating Current Comm’l/Ind’l Automotive-A Automotive-E Maximum CMOS Standby Current Comm’l/Ind’l Automotive-A Automotive-E 10 5 5 90 5 5 5 8 95 -10 10 90 -12 12 85 -15 15 80 80 Unit ns mA mA mA mA mA mA Pin Configurations[2] SOJ/TSOP II Top View A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 NC 1 BLE I/O8 I/O9 VSS VCC I/O14 I/O15 NC 2 OE 48-ball FBGA Top View 3 A0 A3 A5 NC NC A14 A12 A9 4 A1 A4 A6 A7 NC A15 A13 A10 5 A2 CE I/O2 I/O3 I/O4 I/O5 WE A11 6 NC I/O0 I/O1 VCC VSS I/O6 I/O7 NC A B C D E F G H BHE I/O 10 I/O 11 I/O12 I/O13 NC A8 Note: 2. NC pins are not connected on the die. Document #: 38-05132 Rev. *G Page 2 of 13 [+] [+] Feedback CY7C1021CV33 Pin Definitions Pin Name A0–A15 SOJ, TSOP Pin Number BGA Pin Number I/O Type Input Description Address Inputs used to select one of the address locations. 1–5, 18–21, A3, A4, A5, 24–27, 42–44 B3, B4, C3, C4, D4, H2, H3, H4, H5, G3, G4, F3, F4 I/O0–I/O15[3] 7–10, 13–16, B6, C6, C5, Input/Output Bidirectional Data I/O lines. Used as input or output lines 29–32, 35–38 D5, E5, F5, depending on operation. F6, G6, B1, C1, C2, D2, E2, F2, F1, G1 22, 23, 28 A6, D3, E3, E4, G2, H1, H6 G5 B5 B2, A1 A2 No Connect No Connects. Not connected to the die. NC WE CE BHE, BLE OE 17 6 40, 39 41 Input/Control Write Enable Input, active LOW. When selected LOW, a Write is conducted. When deselected HIGH, a Read is conducted. Input/Control Chip Enable Input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Input/Control Byte Write Select Inputs, active LOW. BHE controls I/O16–I/O9, BLE controls I/O8–I/O1. Input/Control Output Enable, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. Ground Ground for the device. Should be connected to ground of the system. VSS VCC 12,34 11,33 D1, E6 D6, E1 Power Supply Power Supply inputs to the device. Note: 3. I/O1–I/O16 for SOJ/TSOP and I/O0–I/O15 for BGA packages. Document #: 38-05132 Rev. *G Page 3 of 13 [+] [+] Feedback CY7C1021CV33 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VCC Relative to GND[4] .... –0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[4] ......................................–0.5V to VCC+0.5V DC Input Voltage[4] ...................................–0.5V to VCC+0.5V Current into Outputs (LOW) .........................................20 mA Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-up Current...................................................... >200 mA Operating Range Range Commercial Industrial Automotive-A Automotive -E Ambient Temperature (TA) 0°C to +70°C –40°C to +85°C –40°C to +85°C –40°C to +125°C VCC 3.3V ± 10% Electrical Characteristics Over the Operating Range -8 Parameter VOH VOL VIH VIL IIX Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[4] Input Leakage Current GND < VI < VCC Com’l/Ind’l Auto-A Auto-E IOZ Output Leakage Current GND < VI < VCC, Com’l/Ind’l Output Disabled Auto-A Auto-E ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Com’l/Ind’l Auto-A Auto-E Com’l/Ind’l Auto-A Auto-E 5 5 20 5 10 5 5 mA 15 15 90 15 15 15 mA 95 90 −1 +1 −1 +1 –12 –1 –12 +12 +1 +12 85 80 80 mA mA –1 –1 +1 +1 µA Test Conditions VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA 2.0 –0.3 −1 Min. 2.4 0.4 VCC + 0.3 0.8 +1 2.0 −0.3 −1 Max. 2.4 0.4 VCC + 0.3 0.8 +1 2.0 –0.3 –1 -10 Min. Max. 2.4 0.4 VCC + 0.3 0.8 +1 2.0 –0.3 –1 –1 -12 Min. Max. 2.4 0.4 VCC + 0.3 0.8 +1 +1 -15 Min. Max. Unit V V V V µA ISB1 Automatic CE Power-Down Current —TTL Inputs Automatic CE Power-Down Current —CMOS Inputs ISB2 Max. VCC, Com’l/Ind’l CE > VCC – 0.3V, Auto-A VIN > VCC – 0.3V, Auto-E or VIN < 0.3V, f=0 Note: 4. VIL (min.) = –2.0V and VIH(max) = VCC + 0.5V for pulse durations of less than 20 ns. Document #: 38-05132 Rev. *G Page 4 of 13 [+] [+] Feedback CY7C1021CV33 Capacitance[5] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max. 8 8 Unit pF pF Thermal Resistance[5] Parameter Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 SOJ 65.06 34.21 TSOP II 76.92 15.86 FBGA 95.32 10.68 Unit °C/W °C/W ΘJA ΘJC AC Test Loads and Waveforms[6] 8-ns devices: OUTPUT Z = 50Ω 50 Ω 10-, 12-, 15-ns devices: 3.3V R 317 Ω 30 pF* OUTPUT * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 1.5V 30 pF* R2 351Ω (a) (b) High-Z characteristics: R 317 Ω 3.0V 90% GND 10% ALL INPUT PULSES 90% 10% 3.3V OUTPUT 5 pF R2 351Ω Rise Time: 1 V/ns (c) Fall Time: 1 V/ns (d) Notes: 5. Tested initially and after any design or process changes that may affect these parameters. 6. AC characteristics (except High-Z) for all 8-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thevenin load shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d). Document #: 38-05132 Rev. *G Page 5 of 13 [+] [+] Feedback CY7C1021CV33 Switching Characteristics Over the Operating Range[7] -8 Parameter Read Cycle tpower[8] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU[11] tPD[11] tDBE tLZBE tHZBE Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW VCC(typical) to the first access Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z [9] [9, 10] -10 Max. Min. 100 10 8 10 3 8 5 10 5 0 4 5 3 4 5 0 8 5 10 5 0 4 5 10 8 8 0 0 7 5 0 3 4 5 7 8 12 9 9 0 0 8 6 0 3 0 0 3 0 3 Max. Min. 100 12 -12 Max. Min. 100 15 12 3 12 6 0 6 3 6 0 12 6 0 6 15 10 10 0 0 10 8 0 3 6 9 -15 Max. Unit µs ns 15 15 7 7 7 15 7 7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7 ns ns Description Min. 100 8 3 0 3 0 OE HIGH to High-Z CE HIGH to CE LOW to Low-Z[9] High-Z[9, 10] CE LOW to Power-Up CE HIGH to Power-Down Byte Enable to Data Valid Byte Enable to Low-Z Byte Disable to High-Z [12] 0 Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE HIGH to Low-Z[9] WE LOW to High-Z[9, 10] Byte Enable to End of Write 8 7 7 0 0 6 5 0 3 6 Notes: 7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. 8. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access is performed. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 10. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 11. This parameter is guaranteed by design and is not tested. 12. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write, and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. Document #: 38-05132 Rev. *G Page 6 of 13 [+] [+] Feedback CY7C1021CV33 Switching Waveforms Read Cycle No. 1 (Address Transition Controlled)[13, 14] tRC RC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[14, 15] ADDRESS tRC CE tACE OE tDOE BHE, BLE tLZOE tDBE tLZBE DATA OUT VCC SUPPLY CURRENT HIGH IMPEDANCE tLZCE tPU 50% tHZCE tHZBE DATA VALID tPD 50% ICC ISB tHZOE HIGH IMPEDANCE Notes: 13. Device is continuously selected. OE, CE, BHE and/or BLE = VIL. 14. WE is HIGH for Read cycle. 15. Address valid prior to or coincident with CE transition LOW. Document #: 38-05132 Rev. *G Page 7 of 13 [+] [+] Feedback CY7C1021CV33 Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[16, 17] tWC ADDRESS tSA CE tAW tSCE tHA tPWE WE tBW BHE, BLE tSD DATA I/O tHD Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS tSA BHE, BLE tBW tAW tPWE WE tSCE CE tSD DATA I/O tHD tHA Notes: 16. Data I/O is high impedance if OE or BHE and/or BLE= VIH. 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05132 Rev. *G Page 8 of 13 [+] [+] Feedback CY7C1021CV33 Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, LOW) tWC ADDRESS tSCE CE tAW tSA WE tBW BHE, BLE tPWE tHA tHZWE DATA I/O tSD tHD tLZWE Truth Table CE H L OE X L WE X H BLE X L L H L X L L L H L L H X H X X H BHE X L H L L H L X H I/O1–I/O8[3] High-Z Data Out Data Out High-Z Data In Data In High-Z High-Z High-Z I/O9–I/O16[3] High-Z Data Out High-Z Data Out Data In High-Z Data In High-Z High-Z Power-down Read – All bits Read – Lower bits only Read – Upper bits only Write – All bits Write – Lower bits only Write – Upper bits only Selected, Outputs Disabled Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Document #: 38-05132 Rev. *G Page 9 of 13 [+] [+] Feedback CY7C1021CV33 Ordering Information Speed (ns) 8 Ordering Code CY7C1021CV33-8VXC CY7C1021CV33-8ZXC CY7C1021CV33-8BAXC 10 CY7C1021CV33-10VC CY7C1021CV33-10VXC CY7C1021CV33-10ZXC CY7C1021CV33-10ZI CY7C1021CV33-10ZXI CY7C1021CV33-10BAXI 12 CY7C1021CV33-12VC CY7C1021CV33-12VXC CY7C1021CV33-12VI CY7C1021CV33-12VXI CY7C1021CV33-12ZXC CY7C1021CV33-12ZXI CY7C1021CV33-12BAI CY7C1021CV33-12BAXI CY7C1021CV33-12ZSE CY7C1021CV33-12ZSXE CY7C1021CV33-12VE CY7C1021CV33-12VXE CY7C1021CV33-12BAE 15 CY7C1021CV33-15VXC CY7C1021CV33-15ZXC CY7C1021CV33-15ZI CY7C1021CV33-15ZXI CY7C1021CV33-15BAXI CY7C1021CV33-15ZSXA 51-85096 51-85087 51-85096 51-85082 51-85087 51-85082 51-85087 51-85096 51-85087 51-85096 51-85082 51-85087 51-85096 51-85082 Package Diagram 51-85082 Package Type 44-pin (400-Mil) Molded SOJ (Pb-free) 44-pin TSOP Type II (Pb-free) 48-ball FBGA (Pb-free) 44-pin (400-Mil) Molded SOJ 44-pin (400-Mil) Molded SOJ (Pb-free) 44-pin TSOP Type II (Pb-free) 44-pin TSOP Type II 44-pin TSOP Type II (Pb-free) 48-ball FBGA (Pb-free) 44-pin (400-Mil) Molded SOJ 44-pin (400-Mil) Molded SOJ (Pb-free) 44-pin (400-Mil) Molded SOJ 44-pin (400-Mil) Molded SOJ (Pb-free) 44-pin TSOP Type II (Pb-free) 44-pin TSOP Type II (Pb-free) 48-ball FBGA 48-ball FBGA (Pb-free) 44-pin TSOP Type II 44-pin TSOP Type II (Pb-free) 44-pin (400-Mil) Molded SOJ 44-pin (400-Mil) Molded SOJ (Pb-free) 48-ball FBGA 44-pin (400-Mil) Molded SOJ (Pb-free) 44-pin TSOP Type II (Pb-free) 44-pin TSOP Type II 44-pin TSOP Type II (Pb-free) 48-ball FBGA (Pb-free) 44-pin TSOP Type II (Pb-free) Automotive-A Commercial Commercial Industrial Automotive-E Commercial Industrial Industrial Industrial Commercial Industrial Commercial Operating Range Commercial Please contact local sales representative regarding availability of these parts Document #: 38-05132 Rev. *G Page 10 of 13 [+] [+] Feedback CY7C1021CV33 Package Diagrams 44-pin (400-Mil) Molded SOJ (51-85082) 51-85082-*B 44-pin Thin Small Outline Package Type II (51-85087) 51-85087-*A Document #: 38-05132 Rev. *G Page 11 of 13 [+] [+] Feedback CY7C1021CV33 Package Diagrams (continued) 48-ball FBGA (7 x 7 x 1.2 mm) (51-85096) TOP VIEW BOTTOM VIEW PIN 1 CORNER Ø0.05 M C Ø0.25 M C A B Ø0.30±0.05(48X) PIN 1 CORNER (LASER MARK) 12 A B C 7.00±0.10 5.25 D E F G H 7.00±0.10 0.75 3 4 5 6 6 5 4 3 2 1 A B C D E 2.625 F G H A A 1.875 0.75 B 7.00±0.10 3.75 B 7.00±0.10 0.53±0.05 0.25 C 0.15(4X) 0.21±0.05 0.10 C 51-85096-*F SEATING PLANE 0.36 C 1.20 MAX. All products and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05132 Rev. *G Page 12 of 13 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] [+] Feedback CY7C1021CV33 Document History Page Document Title: CY7C1021CV33, 1-Mbit (64K x 16) Static RAM Document Number: 38-05132 REV. ** *A *B *C *D *E *F ECN NO. 109472 115044 115808 120413 238454 334398 493565 Issue Date 12/06/01 05/08/02 06/25/02 10/31/02 See ECN See ECN See ECN Orig. of Change HGK HGK HGK DFP RKF SYT NXR New Data Sheet Ram7 version C4K x 16 Async Remove “Preliminary” ISB1 and ICC values changed Updated BGA pin E4 to NC 1) Added Automotive Specs to Data sheet 2) Added Pb-free devices in the Ordering Information Added Pb-free on page# 9 and 10 Added Automotive-A operating range Corrected typo in the Pin Definition table Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Removed IOS parameter from DC Electrical Characteristics table Updated the ordering information table Added tPOWER spec in the AC Switching Characteristics table Added footnote #8 Description of Change *G 563963 See ECN VKN Document #: 38-05132 Rev. *G Page 13 of 13 [+] [+] Feedback