CY7C1021CV33-15VXIT

CY7C1021CV33 1-Mbit (64K x 16) Static RAM Functional Description[1] Features • Temperature Ranges The CY7C1021CV33 is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. — Commercial: 0°C to 70°C — Industrial: –40°C to 85°C — Automotive: –40°C to 125°C • Pin- and function-compatible with CY7C1021BV33 • High speed — tAA = 8 ns (Commercial & Industrial) — tAA = 12 ns (Automotive) • CMOS for optimum speed/power • Low active power: 360 mW (max.) • Automatic power-down when deselected • Independent control of upper and lower bits • Available in 44-pin TSOP II, 400-mil SOJ, 48-ball FBGA • Also available in Lead-Free 44-pin TSOP II, 400-mil SOJ packages Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A15). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O9 to I/O16. See the truth table at the end of this data sheet for a complete description of Read and Write modes. The input/output pins (I/O1 through I/O16) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a Write operation (CE LOW, and WE LOW). The CY7C1021CV33 is available in standard 44-pin TSOP Type II, 400-mil-wide SOJ packages, as well as a 48-ball FBGA. Logic Block Diagram 64K x 16 RAM Array 512 X 2048 SENSE AMPS ROW DECODER A7 A6 A5 A4 A3 A2 A1 A0 DATA IN DRIVERS I/O1–I/O8 I/O9–I/O16 COLUMN DECODER A8 A9 A10 A11 A12 A13 A14 A15 BHE WE CE OE BLE Note: 1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05132 Rev. *E • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised March 7, 2005 CY7C1021CV33 Selection Guide CY7C1021CV33 CY7C1021CV33- CY7C1021CV33- CY7C1021CV33-8 10 12 15 Unit Maximum Access Time 8 10 12 15 ns Maximum Operating Current 95 90 85 80 mA Automotive Maximum CMOS Standby Current Automotive - - 90 - mA 5 5 5 5 mA - - 10 - mA Pin Configurations SOJ / TSOP II Top View A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A15 A14 A13 A12 NC 1 44 2 3 43 42 4 41 40 39 38 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A5 A6 A7 OE BHE BLE I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 NC 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 48-ball FBGA Document #: 38-05132 Rev. *E (Top View) 4 3 1 2 BLE OE A0 I/O8 BHE I/O9 5 6 A1 A2 NC A A3 A4 CE I/O0 B I/O10 A5 A6 I/O2 I/O1 C VSS I/O11 NC A7 I/O3 VCC D VCC I/O12 NC NC I/O4 VSS E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 NC A12 A13 WE I/O7 G NC A8 A9 A10 A11 NC H Page 2 of 13 CY7C1021CV33 Pin Definitions Pin Name A0–A15 I/O0–I/O15[2] SOJ, TSOP Pin Number BGA Pin Number 1–5, 18–21, A3, A4, A5, 24–27, 42–44 B3, B4, C3, C4, D4, H2, H3, H4, H5, G3, G4, F3, F4 7–10, 13–16, B6, C6, 29–32, 35–38 D5, E5, F6, G6, C1, C2, E2, F2, G1 I/O Type Input Description Address Inputs used to select one of the address locations. C5, Input/Output Bidirectional Data I/O lines. Used as input or output lines F5, depending on operation. B1, D2, F1, A6, D3, E3, No Connect No Connects. Not connected to the die. E4, G2, H1, H6 NC 22, 23, 28 WE 17 G5 Input/Control Write Enable Input, active LOW. When selected LOW, a Write is conducted. When deselected HIGH, a Read is conducted. CE 6 B5 Input/Control Chip Enable Input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip. BHE, BLE 39, 40 A1, B2 Input/Control Byte Write Select Inputs, active LOW. BLE controls I/O8–I/O1, BHE controls I/O16–I/O9. OE 41 A2 Input/Control Output Enable, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. VSS 12,34 D1, E6 VCC 11,33 D6, E1 Ground Ground for the device. Should be connected to ground of the system. Power Supply Power Supply inputs to the device. Note: 2. I/O1–I/O16 for SOJ/TSOP and I/O0–I/O15 for BGA packages. Document #: 38-05132 Rev. *E Page 3 of 13 CY7C1021CV33 Maximum Ratings Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Latch-up Current...................................................... >200 mA Ambient Temperature with Power Applied............................................. –55°C to +125°C Operating Range Ambient Temperature (TA) VCC 0°C to +70°C 3.3V ± 10% Industrial –40°C to +85°C 3.3V ± 10% Automotive –40°C to +125°C 3.3V ± 10% Range Supply Voltage on VCC to Relative GND[3] .... –0.5V to +4.6V Commercial DC Voltage Applied to Outputs in High-Z State[3] ......................................–0.5V to VCC+0.5V [3] DC Input Voltage ...................................–0.5V to VCC+0.5V Current into Outputs (LOW) .........................................20 mA Electrical Characteristics Over the Operating Range 1021CV33-8 1021CV33-10 1021CV33-12 1021CV33-15 Parameter Description Test Conditions Min. Max. Min. Max. Min. Max. VOH Output HIGH VCC = Min., Voltage IOH = –4.0 mA VOL Output LOW Voltage VIH Input HIGH Voltage 2.0 VCC + 0.3 2.0 VCC + 0.3 2.0 VCC + 0.3 VIL Input LOW Voltage[3] –0.3 0.8 −0.3 0.8 –0.3 IIX Input Load Current GND < VI < VCC −1 +1 −1 +1 Output Leakage Current GND < VI < VCC, Output Disabled IOS Output Short Circuit Current[4] VCC = Max., VOUT = GND ICC VCC Operating Supply Current IOZ ISB1 ISB2 2.4 VCC = Min., IOL = 8.0 mA 2.4 0.4 Com’l / Ind’l 2.4 0.4 Automotive Min. Max. 2.4 0.4 Unit V 0.4 V 2.0 VCC + 0.3 V 0.8 –0.3 0.8 V –1 +1 –1 +1 µA –12 +12 µA Com’l / Ind’l −1 +1 −1 +1 –1 +1 –1 +1 µA Automotive - - - - –12 +12 - - µA -300 −300 –300 –300 mA VCC = Max., Com’l / Ind’l IOUT = 0 mA, Automotive f = fMAX = 1/tRC 95 90 85 80 mA - - 90 - mA Automatic CE Power-Down Current —TTL Inputs Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Com’l / Ind’l 15 15 15 15 mA Automotive - - 20 - mA Automatic CE Power-Down Current —CMOS Inputs Max. VCC, Com’l / Ind’l CE > VCC – Automotive 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f=0 5 5 5 5 mA - - 10 - mA Notes: 3. VIL (min.) = –2.0V and VIH(max) = VCC + 0.5V for pulse durations of less than 20 ns. 4. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. Document #: 38-05132 Rev. *E Page 4 of 13 CY7C1021CV33 Thermal Resistance[5] Parameter ΘJA Description Test Conditions 48-ball FBGA 44-lead SOJ 44-lead TSOP-II Unit 95.32 65.06 76.92 °C/W 10.68 34.21 15.86 °C/W Thermal Resistance Test conditions follow standard test (Junction to Ambient) methods and procedures for Thermal Resistance measuring thermal impedance, per EIA / JESD51. (Junction to Case) ΘJC Capacitance[5] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max. Unit 8 pF 8 pF AC Test Loads and Waveforms[6] 8-ns devices: 10-, 12-, 15-ns devices: Z = 50Ω 50 Ω * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT R 317Ω 3.3V OUTPUT 30 pF* OUTPUT R2 351Ω 30 pF* 1.5V (b) (a) High-Z characteristics: R 317Ω 90% GND 3.3V ALL INPUT PULSES 3.0V 90% 10% 10% Rise Time: 1 V/ns (c) Fall Time: 1 V/ns OUTPUT R2 351Ω 5 pF (d) Note: 5. Tested initially and after any design or process changes that may affect these parameters. 6. AC characteristics (except High-Z) for all 8-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thevenin load shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d). Document #: 38-05132 Rev. *E Page 5 of 13 CY7C1021CV33 Switching Characteristics Over the Operating Range[7] Parameter Description 1021CV33-8 1021CV33-10 1021CV33-12 1021CV33-15 Min. Min. Min. Min. Max. Max. Max. Max. Unit Read Cycle tRC Read Cycle Time 8 tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 8 10 12 15 ns tDOE OE LOW to Data Valid 5 5 6 7 ns 7 ns [8] tLZOE OE LOW to Low-Z tHZOE OE HIGH to High-Z[8, 9] tLZCE CE LOW to Low-Z[8] 10 8 3 10 3 0 3 CE HIGH to tPU[10] tPD[10] CE LOW to Power-Up CE HIGH to Power-Down 8 5 10 tDBE Byte Enable to Data Valid 5 5 tLZBE Byte Enable to Low-Z tHZBE Byte Disable to High-Z 0 0 4 ns 7 ns 12 15 ns 6 7 ns 0 0 5 ns 3 6 ns ns 0 0 0 15 6 3 tHZCE ns 3 0 3 0 12 5 4 15 3 0 4 High-Z[8, 9] 12 ns 0 6 ns 7 ns Write Cycle[11] tWC Write Cycle Time 8 10 12 15 ns tSCE CE LOW to Write End 7 8 9 10 ns tAW Address Set-up to Write End 7 8 9 10 ns tHA Address Hold from Write End 0 0 0 0 ns tSA Address Set-up to Write Start 0 0 0 0 ns tPWE WE Pulse Width 6 7 8 10 ns tSD Data Set-up to Write End 5 5 6 8 ns tHD Data Hold from Write End 0 0 0 0 ns tLZWE WE HIGH to Low-Z[8] 3 3 3 3 ns High-Z[8, 9] tHZWE WE LOW to tBW Byte Enable to End of Write 4 6 5 7 6 8 7 9 ns ns Notes: 7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 9. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 10. This parameter is guaranteed by design and is not tested. 11. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write, and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. Document #: 38-05132 Rev. *E Page 6 of 13 CY7C1021CV33 Switching Waveforms Read Cycle No. 1[12, 13] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[13, 14] ADDRESS tRC CE tACE OE tHZOE tDOE BHE, BLE tLZOE tHZCE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZBE HIGH IMPEDANCE DATA VALID tPD tPU 50% IICC CC 50% IISB SB Notes: 12. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. 13. WE is HIGH for Read cycle. 14. Address valid prior to or coincident with CE transition LOW. Document #: 38-05132 Rev. *E Page 7 of 13 CY7C1021CV33 Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[15, 16] tWC ADDRESS CE tSA tSCE tAW tHA tPWE WE tBW BHE, BLE tSD tHD DATA I/O Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tHA tPWE WE tSCE CE tSD tHD DATA I/O Notes: 15. Data I/O is high impedance if OE or BHE and/or BLE= VIH. 16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05132 Rev. *E Page 8 of 13 CY7C1021CV33 Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, LOW) tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD DATA I/O tLZWE Truth Table CE OE H X X X X High-Z High-Z Power-down Standby (ISB) L L H L L Data Out Data Out Read – All bits Active (ICC) L H Data Out High-Z Read – Lower bits only Active (ICC) H L High-Z Data Out Read – Upper bits only Active (ICC) L L Data In Data In Write – All bits Active (ICC) L H Data In High-Z Write – Lower bits only Active (ICC) H L High-Z Data In Write – Upper bits only Active (ICC) L X WE L BLE BHE I/O1–I/O8 I/O9–I/O16 Mode Power L H H X X High-Z High-Z Selected, Outputs Disabled Active (ICC) L X X H H High-Z High-Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) 8 10 Ordering Code Package Name Package Type CY7C1021CV33-8VC V34 44-lead (400-Mil) Molded SOJ CY7C1021CV33-8ZC Z44 44-lead TSOP Type II Operating Range Commercial CY7C1021CV33-8BAC BA48A CY7C1021CV33-10VC V34 44-lead (400-Mil) Molded SOJ CY7C1021CV33-10VI V34 44-lead (400-Mil) Molded SOJ Commercial Industrial CY7C1021CV33-10ZC Z44 44-lead TSOP Type II Commercial 44-lead TSOP Type II Industrial Commercial CY7C1021CV33-10ZI CY7C1021CV33-10BAC CY7C1021CV33-10BAI Document #: 38-05132 Rev. *E BA48A 48-ball FBGA 48-ball FBGA Industrial Page 9 of 13 CY7C1021CV33 Ordering Information Speed (ns) 12 Ordering Code CY7C1021CV33-12VC Package Name V34 Package Type 44-pin (400-Mil) Molded SOJ CY7C1021CV33-12VI Automotive Z44 44-pin TSOP Type II Industrial CY7C1021CV33-12ZSE Automotive BA48A 48-ball FBGA CY7C1021CV33-12BAI CY7C1021CV33-15VC Automotive V34 44-pin (400-Mil) Molded SOJ Z44 44-pin TSOP Type II Commercial 48-ball FBGA Industrial Commercial CY7C1021CV33-15VI CY7C1021CV33-15ZC BA48A CY7C1021CV33-15BAI CY7C1021CV33-8VXC CY7C1021CV33-8ZXC 10 Industrial V34 Z44 44-lead (400-Mil) Molded SOJ (Pb-Free) 44-lead TSOP Type II (Pb-Free) Commercial Commercial V34 44-lead (400-Mil) Molded SOJ (Pb-Free) V34 44-lead (400-Mil) Molded SOJ (Pb-Free) Commercial Industrial CY7C1021CV33-10ZXC Z44 44-lead TSOP Type II (Pb-Free) Commercial CY7C1021CV33-10ZXI Z44 44-lead TSOP Type II (Pb-Free) Industrial 48-ball FBGA (Pb-Free) Commercial BA48A CY7C1021CV33-10VXC CY7C1021CV33-10VXI BA48A CY7C1021CV33-10BAXI 15 Commercial 48-ball FBGA (Pb-Free) CY7C1021CV33-8BAXC CY7C1021CV33-10BAXC 12 Commercial Industrial CY7C1021CV33-15ZI CY7C1021CV33-15BAC Commercial Industrial CY7C1021CV33-12BAE 8 Commercial CY7C1021CV33-12ZI CY7C1021CV33-12BAC 15 Commercial Industrial CY7C1021CV33-12VE CY7C1021CV33-12ZC Operating Range Industrial CY7C1021CV33-12VXC V34 44-pin (400-Mil) Molded SOJ (Pb-Free) Commercial CY7C1021CV33-12VXI V34 44-pin (400-Mil) Molded SOJ (Pb-Free) Industrial CY7C1021CV33-12VXE V34 44-pin (400-Mil) Molded SOJ (Pb-Free) Automotive CY7C1021CV33-12ZXC Z44 44-lead TSOP Type II (Pb-Free) Commercial CY7C1021CV33-12ZXI Z44 44-lead TSOP Type II (Pb-Free) Industrial CY7C1021CV33-12ZSXE Z44 44-pin TSOP Type II (Pb-Free) Automotive CY7C1021CV33-12BAXC BA48A 48-ball FBGA (Pb-Free) Commercial CY7C1021CV33-12BAXI BA48A 48-ball FBGA (Pb-Free) Industrial CY7C1021CV33-12BAXE BA48A 48-ball FBGA (Pb-Free) Automotive CY7C1021CV33-15VXC V34 44-pin (400-Mil) Molded SOJ (Pb-Free) CY7C1021CV33-15VXI V34 44-pin (400-Mil) Molded SOJ (Pb-Free) Commercial Industrial CY7C1021CV33-15ZXC Z44 44-lead TSOP Type II (Pb-Free) CY7C1021CV33-15ZXI CY7C1021CV33-15BAXC Z44 BA48A 44-lead TSOP Type II (Pb-Free) Commercial Industrial 48-ball FBGA (Pb-Free) Commercial CY7C1021CV33-15BAXI Industrial Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Document #: 38-05132 Rev. *E Page 10 of 13 CY7C1021CV33 Package Diagrams 48-Ball (7.00 mm x 7.00 mm x 1.2 mm) FBGA BA48A 51-85096-*E Document #: 38-05132 Rev. *E Page 11 of 13 CY7C1021CV33 Package Diagrams (continued) 44-Lead (400-Mil) Molded SOJ V34 51-85082-*B 44-pin TSOP II Z44 51-85087-*A All products and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05132 Rev. *E Page 12 of 13 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C1021CV33 Document History Page Document Title: CY7C1021CV33 1-Mbit (64K x 16) Static RAM Document Number: 38-05132 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 109472 12/06/01 HGK New Data Sheet *A 115044 05/08/02 HGK Ram7 version C4K x 16 Async. Remove “Preliminary” *B 115808 06/25/02 HGK ISB1 and ICC values changed *C 120413 10/31/02 DFP Updated BGA pin E4 to NC. *D 238454 See ECN RKF 1) Added Automotive Specs to Datasheet 2) Added Pb-Free devices in the Ordering information *E 334398 See ECN SYT Added Pb-Free on page# 9 and 10 Document #: 38-05132 Rev. *E Page 13 of 13