CY7C1021CV33-8ZXC

CY7C1021CV33 1-Mbit (64K x 16) Static RAM Features ■ Functional Description Temperature ranges ❐ Commercial: 0°C to 70°C ❐ Industrial: –40°C to 85°C ❐ Automotive-A: –40°C to 85°C ❐ Automotive-E: –40°C to 125°C The CY7C1021CV33 is a high performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power down feature that significantly reduces power consumption when deselected. ■ Pin and function compatible with CY7C1021BV33 ■ High speed ❐ tAA = 8 ns (Commercial & Industrial) ❐ tAA = 12 ns (Automotive-E) ■ CMOS for optimum speed and power ■ Low active power: 325 mW (max) ■ Automatic power down when deselected ■ Independent control of upper and lower bits ■ Available in Pb-free and non Pb-free 44-pin 400 Mil SOJ, 44-pin TSOP II and 48-Ball FBGA packages Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO1 through IO8), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from IO pins (IO9 through IO16) is written into the location specified on the address pins (A0 through A15). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on IO1 to IO8. If Byte High Enable (BHE) is LOW, then data from memory appears on IO9 to IO16. For more information, see the “Truth Table” on page 9 for a complete description of Read and Write modes. The input and output pins (IO1 through IO16) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines. Logic Block Diagram 64K x 16 RAM Array SENSE AMPS A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS IO0–IO7 IO8–IO15 COLUMN DECODER A8 A9 A10 A11 A12 A13 A14 A15 BHE WE CE OE BLE Cypress Semiconductor Corporation Document Number: 38-05132 Rev. *H • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised October 11, 2007 CY7C1021CV33 Selection Guide -8 Maximum Access Time Maximum Operating Current Comm’l/Ind’l -10 -12 -15 8 10 12 15 ns 95 90 85 80 mA 80 mA Automotive-A Automotive-E Maximum CMOS Standby Current Comm’l/Ind’l Unit 90 5 5 mA 5 5 Automotive-A mA 5 Automotive-E mA 10 mA Pin Configuration Figure 1. 44-Pin SOJ/TSOP II [1] A4 A3 A2 A1 A0 CE IO1 IO2 IO3 IO4 VCC VSS IO5 IO6 IO7 IO8 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE IO16 IO15 IO14 IO13 VSS VCC IO12 IO11 IO10 IO9 NC A8 A9 A10 A11 NC Figure 2. 48-Ball FBGA Pinout [1] 1 2 3 4 5 6 BLE OE A0 A1 A2 NC A IO8 BHE A3 A4 CE IO0 B IO9 IO10 A5 A6 IO2 IO1 C VSS IO11 NC A7 IO3 VCC D VCC IO12 NC NC IO4 VSS E IO14 IO13 A14 A15 IO5 IO6 F IO15 NC A12 A13 WE IO7 G NC A8 A9 A10 A11 NC H Note 1. NC pins are not connected on the die. Document Number: 38-05132 Rev. *H Page 2 of 14 CY7C1021CV33 Pin Definitions Pin Name A0–A15 IO1–IO16 [2] SOJ, TSOP Pin Number BGA Pin Number 1–5, 18–21, A3, A4, A5, B3, 24–27, 42–44 B4, C3, C4, D4, H2, H3, H4, H5, G3, G4, F3, F4 IO Type Input Description Address Inputs. Used to select one of the address locations. 7–10, 13–16, B6, C6, C5, Input or Output Bidirectional Data IO lines. Used as input or output lines depending on operation. 29–32, 35–38 D5, E5, F5, F6, G6, B1, C1, C2, D2, E2, F2, F1, G1 NC 22, 23, 28 A6, D3, E3, E4, G2, H1, H6 No Connect No Connects. Not connected to the die. WE 17 G5 Input or Control Write Enable Input, Active LOW. When selected LOW, a write is conducted. When deselected HIGH, a read is conducted. CE 6 B5 Input or Control Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. BHE, BLE 40, 39 B2, A1 Input or Control Byte Write Select Inputs, Active LOW. BHE controls IO16 – IO9, BLE controls IO8 – IO1. OE 41 A2 Input or Control Output Enable, Active LOW. Controls the direction of the IO pins. When LOW, the IO pins are allowed to behave as outputs. When deasserted HIGH, the IO pins are tri-stated and act as input data pins. VSS 12, 34 D1, E6 Ground Ground for the device. Connected to ground of the system. VCC 11, 33 D6, E1 Power Supply Power Supply Inputs to the Device. Note 2. IO1–IO16 for SOJ/TSOP and IO0–IO15 for BGA packages. Document Number: 38-05132 Rev. *H Page 3 of 14 CY7C1021CV33 Maximum Ratings Static Discharge Voltage............................................ >2001V (MIL-STD-883, Method 3015) Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Latch Up Current ..................................................... >200 mA Storage Temperature ................................. –65°C to +150°C Operating Range Ambient Temperature with Power Applied ............................................ –55°C to +125°C Range Supply Voltage on VCC Relative to GND[3] .....–0.5V to +4.6V Commercial DC Voltage Applied to Outputs in High Z State[3] ...................................... –0.5V to VCC+0.5V Industrial DC Input Voltage[3] .................................. –0.5V to VCC+0.5V Ambient Temperature (TA) VCC 0°C to +70°C 3.3V ± 10% –40°C to +85°C Automotive-A –40°C to +85°C Automotive -E –40°C to +125°C Current into Outputs (LOW)......................................... 20 mA Electrical Characteristics Over the Operating Range Parameter Description Test Conditions -8 Min -10 Max Min -12 Max Min -15 Max VOH Output HIGH Voltage VCC = Min, IOH = –4.0 mA VOL Output LOW Voltage VCC = Min, IOL = 8.0 mA VIH Input HIGH Voltage 2.0 VCC + 0.3 2.0 VCC + 0.3 2.0 VCC + 0.3 VIL Input LOW Voltage[3] –0.3 0.8 –0.3 0.8 –0.3 0.8 IIX Input Leakage Current –1 +1 –1 +1 –1 +1 GND < VI < VCC 2.4 2.4 0.4 Com’l/Ind’l 2.4 0.4 IOZ Output Leakage Current GND < VI < VCC, Output disabled Com’l/Ind’l –1 +1 –1 +1 ICC ISB1 ISB2 VCC Operating Supply Current 0.4 VCC = Max, IOUT = 0 mA, f = fMAX = 1/tRC Automatic CE Power Max VCC, Down Current —TTL CE > VIH Inputs VIN > VIH or VIN < VIL, f = fMAX –12 +12 –1 +1 Auto-A Auto-E Com’l/Ind’l –12 95 90 V 0.4 V 2.0 VCC + 0.3 V –0.3 0.8 V –1 +1 µA –1 +1 –1 +1 –1 +1 µA 85 80 mA 80 Auto-E 90 15 15 15 Auto-A 15 mA 15 Auto-E Automatic CE Power Max VCC, Com’l/Ind’l Down Current — CE > VCC – 0.3V, Auto-A CMOS Inputs VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 Auto-E Unit +12 Auto-A Com’l/Ind’l Max 2.4 Auto-A Auto-E Min 20 5 5 5 5 mA 5 10 Note 3. VIL (min) = –2.0V and VIH(max) = VCC + 0.5V for pulse durations of less than 20 ns. Document Number: 38-05132 Rev. *H Page 4 of 14 CY7C1021CV33 Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max Unit 8 pF 8 pF Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions SOJ TSOP II FBGA Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 65.06 76.92 95.32 °C/W 34.21 15.86 10.68 °C/W AC Test Loads and Waveforms Figure 3. AC Test Loads and Waveforms [4] 8-ns devices: 10-, 12-, 15-ns devices: Z = 50Ω 50 Ω * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT R 317Ω 3.3V OUTPUT 30 pF* OUTPUT R2 351Ω 30 pF* 1.5V (b) (a) High-Z characteristics: 3.0V GND 90% 90% 10% Rise Time: 1 V/ns 10% (c) R 317Ω 3.3V ALL INPUT PULSES Fall Time: 1 V/ns OUTPUT R2 351Ω 5 pF (d) Note 4. AC characteristics (except High-Z) for all 8-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thevenin load shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d). Document Number: 38-05132 Rev. *H Page 5 of 14 CY7C1021CV33 Switching Characteristics Over the Operating Range [5] Parameter Description -8 Min -10 Max Min -12 Max Min -15 Max Min Max Unit Read Cycle tpower[6] VCC(Typical) to the First Access tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 8 10 tDOE OE LOW to Data Valid 5 5 [7] OE LOW to Low Z tLZOE 100 100 100 100 µs 8 10 12 15 ns 8 3 tHZOE OE HIGH to High tLZCE CE LOW to Low Z[7] 3 0 Z[7, 8] 10 4 Z[7, 8] ns 12 15 ns 6 7 ns 3 0 5 3 4 15 3 0 3 12 0 6 3 ns 7 ns 3 CE HIGH to High tPU[9] tPD[9] CE LOW to Power Up CE HIGH to Power Down 8 10 12 15 ns tDBE Byte Enable to Data Valid 5 5 6 7 ns tLZBE Byte Enable to Low Z 0 Byte Disable to High Z tHZBE 0 0 0 4 6 ns tHZCE 0 5 ns ns 0 0 5 7 ns 0 6 ns 7 ns [10] Write Cycle tWC Write Cycle Time 8 10 12 15 ns tSCE CE LOW to Write End 7 8 9 10 ns tAW Address Setup to Write End 7 8 9 10 ns tHA Address Hold from Write End 0 0 0 0 ns tSA Address Setup to Write Start 0 0 0 0 ns tPWE WE Pulse Width 6 7 8 10 ns tSD Data Setup to Write End 5 5 6 8 ns tHD Data Hold from Write End 0 0 0 0 ns tLZWE WE HIGH to Low Z[7] 3 3 3 3 ns Z[7, 8] tHZWE WE LOW to High tBW Byte Enable to End of Write 4 6 5 7 6 8 7 9 ns ns Notes 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V. 6. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady state voltage. 9. This parameter is guaranteed by design and is not tested. 10. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW, and BHE/BLE LOW. CE, WE, and BHE/BLE is LOW to initiate a write. The transition of these signals terminate the write. The input data setup and hold timing is referenced to the leading edge of the signal that terminates the write. Document Number: 38-05132 Rev. *H Page 6 of 14 CY7C1021CV33 Switching Waveforms Figure 4. Read Cycle No. 1 (Address Transition Controlled)[11, 12] tRC RC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 5. Read Cycle No. 2 (OE Controlled)[12, 13] ADDRESS tRC CE tACE OE tHZOE tDOE tLZOE BHE, BLE tHZCE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZBE DATA VALID HIGH IMPEDANCE tPD tPU 50% 50% ICC ISB Notes 11. Device is continuously selected. OE, CE, BHE, and/or BLE = VIL. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW. Document Number: 38-05132 Rev. *H Page 7 of 14 CY7C1021CV33 Switching Waveforms (continued) Figure 6. Write Cycle No. 1 (CE Controlled)[14, 15] tWC ADDRESS tSA tSCE CE tAW tHA tPWE WE tBW BHE, BLE tSD tHD DATA IO Figure 7. Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tHA tPWE WE tSCE CE tSD tHD DATA IO Notes 14. Data IO is high impedance if OE, BHE, and/or BLE= VIH. 15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document Number: 38-05132 Rev. *H Page 8 of 14 CY7C1021CV33 Switching Waveforms (continued) Figure 8. Write Cycle No. 3 (WE Controlled, LOW) tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD DATA IO tLZWE Truth Table CE OE WE BLE BHE H X X X X High Z High Z Power Down Standby (ISB) L L H L L Data Out Data Out Read – All Bits Active (ICC) L H Data Out High Z Read – Lower Bits Only Active (ICC) L X L IO1 – IO8 IO9 – IO16 Mode Power H L High Z Data Out Read – Upper Bits Only Active (ICC) L L Data In Data In Write – All Bits Active (ICC) L H Data In High Z Write – Lower Bits Only Active (ICC) H L High Z Data In Write – Upper Bits Only Active (ICC) L H H X X High Z High Z Selected, Outputs Disabled Active (ICC) L X X H H High Z High Z Selected, Outputs Disabled Active (ICC) Document Number: 38-05132 Rev. *H Page 9 of 14 CY7C1021CV33 Ordering Information Speed (ns) 8 Ordering Code CY7C1021CV33-8VXC CY7C1021CV33-8ZXC 10 Operating Range 51-85082 44-pin (400-Mil) Molded SOJ (Pb-free) Commercial 44-pin TSOP Type II (Pb-free) 51-85096 48-ball FBGA (Pb-free) CY7C1021CV33-10VC 51-85082 44-pin (400-Mil) Molded SOJ 51-85087 44-pin TSOP Type II (Pb-free) CY7C1021CV33-10ZI 51-85087 44-pin TSOP Type II 51-85096 48-ball FBGA (Pb-free) CY7C1021CV33-12VC 51-85082 44-pin (400-Mil) Molded SOJ 51-85087 44-pin TSOP Type II (Pb-free) CY7C1021CV33-12VI 51-85082 44-pin (400-Mil) Molded SOJ 51-85087 44-pin TSOP Type II (Pb-free) CY7C1021CV33-12BAI 51-85096 48-ball FBGA CY7C1021CV33-12VE CY7C1021CV33-12VXE CY7C1021CV33-12ZSE CY7C1021CV33-12ZSXE 48-ball FBGA (Pb-free) 51-85082 44-pin (400-Mil) Molded SOJ 51-85087 44-pin TSOP Type II 44-pin TSOP Type II (Pb-free) 51-85096 48-ball FBGA CY7C1021CV33-15VXC 51-85082 44-pin (400-Mil) Molded SOJ (Pb-free) CY7C1021CV33-15ZXC 51-85087 44-pin TSOP Type II (Pb-free) CY7C1021CV33-15ZI 51-85087 44-pin TSOP Type II Commercial Industrial 44-pin TSOP Type II (Pb-free) CY7C1021CV33-15BAXI 51-85096 48-ball FBGA (Pb-free) CY7C1021CV33-15ZSXA 51-85087 44-pin TSOP Type II (Pb-free) Document Number: 38-05132 Rev. *H Automotive-E 44-pin (400-Mil) Molded SOJ (Pb-free) CY7C1021CV33-12BAE CY7C1021CV33-15ZXI Industrial 44-pin (400-Mil) Molded SOJ (Pb-free) CY7C1021CV33-12ZXI CY7C1021CV33-12BAXI Commercial 44-pin (400-Mil) Molded SOJ (Pb-free) CY7C1021CV33-12ZXC CY7C1021CV33-12VXI Industrial 44-pin TSOP Type II (Pb-free) CY7C1021CV33-10BAXI CY7C1021CV33-12VXC Commercial 44-pin (400-Mil) Molded SOJ (Pb-free) CY7C1021CV33-10ZXC CY7C1021CV33-10ZXI 15 Package Type CY7C1021CV33-8BAXC CY7C1021CV33-10VXC 12 Package Diagram Automotive-A Page 10 of 14 CY7C1021CV33 Package Diagrams Figure 9. 44-Pin (400 Mil) Molded SOJ 51-85082-*B Document Number: 38-05132 Rev. *H Page 11 of 14 CY7C1021CV33 Package Diagrams (continued) Figure 10. 44-Pin Thin Small Outline Package Type II 51-85087-*A Document Number: 38-05132 Rev. *H Page 12 of 14 CY7C1021CV33 Package Diagrams (continued) Figure 11. 48-Ball FBGA (7 x 7 x 1.2 mm) BOTTOM VIEW TOP VIEW PIN 1 CORNER Ø0.05 M C PIN 1 CORNER (LASER MARK) Ø0.25 M C A B Ø0.30±0.05(48X) 1 2 3 4 5 6 6 4 3 2 1 C C F G D E F 2.625 E 0.75 B 5.25 A B 7.00±0.10 A D 7.00±0.10 5 G H H A A 1.875 0.75 B 7.00±0.10 3.75 7.00±0.10 0.10 C 0.21±0.05 0.53±0.05 0.25 C B 0.15(4X) 0.36 SEATING PLANE C 1.20 MAX. 51-85096-*G Document Number: 38-05132 Rev. *H Page 13 of 14 CY7C1021CV33 Document History Page Document Title: CY7C1021CV33, 1-Mbit (64K x 16) Static RAM Document Number: 38-05132 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 109472 12/06/01 HGK New datasheet *A 115044 05/08/02 HGK Ram7 version C4K x 16 Async Removed “Preliminary” *B 115808 06/25/02 HGK ISB1 and ICC values changed *C 120413 10/31/02 DFP Updated BGA pin E4 to NC *D 238454 See ECN RKF 1) Added Automotive Specifications to datasheet 2) Added Pb-free devices in the Ordering Information *E 334398 See ECN SYT Added Pb-free on page 9 and 10 *F 493565 See ECN NXR Added Automotive-A operating range Corrected typo in the Pin Definition table Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Removed IOS parameter from DC Electrical Characteristics table Updated the ordering information table *G 563963 See ECN VKN Added tPOWER specification in the AC Switching Characteristics table Added footnote 8 *H 1390863 See ECN VKN/AESA Corrected TSOP II package outline © Cypress Semiconductor Corporation, 2001-2007. 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Document Number: 38-05132 Rev. *H Revised October 11, 2007 All product and company names mentioned in this document are the trademarks of their respective holders. Page 14 of 14