CY7C1024AV33-10AC

024AV33 CY7C1024AV33 128K x 24 Static RAM Features Writing to the device is accomplished by taking Chip Enable (CE1, CE2, CE3) active and Write Enable (WE) inputs LOW. Data on the 24 I/O pins (I/O0 through I/O23) is then written into the location specified on the address pins (A0 through A16). • High speed — tAA = 10 ns • CMOS for optimum speed/power • Center power/ground pinout • Automatic power-down when deselected • Easy memory expansion with CE1, CE2, CE3 and OE options Reading from the device is accomplished by taking Chip Enable (CE1, CE2, CE3) active and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The 24 input/output pins (I/O0 through I/O23) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE1, CE3 LOW, CE2 HIGH, and WE LOW). Functional Description[1] The CY7C1024AV33 is a high-performance CMOS static RAM organized as 131,072 words by 24 bits. Easy memory expansion is provided by an active LOW CE1, CE3, active HIGH CE2, an active LOW Output Enable (OE), and three-state drivers. This device has an automatic power-down feature that significantly reduces power consumption when deselected. The CY7C1024AV33 is available in a standard 119-ball BGA package and a 100-pin TQFP package. Functional Block Diagram VCC VSS I/O BUFFER DQ0 ROW DECODER ADDRESS BUFFER A0 MEMORY ARRAY 128K X 24 DQ23 COLUMN DECODER A16 CONTROL CE# CE1# CE2 WE# OE# Selection Guide 7C1024AV33-10 7C1024AV33-12 7C1024AV33-15 Maximum Access Time (ns) 10 12 15 Maximum Operating Current (mA) 275 250 225 Maximum Standby Current (mA) 15 15 15 Note: 1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05149 Rev. *B • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised November 13, 2002 CY7C1024AV33 Pin Configurations 119 BGA Top View 1 2 3 4 5 6 7 A NC A A A A A NC B NC A A CE1 A A NC C DQ NC CE2 NC CE3 NC DQ D DQ VCC VSS VSS VSS VCC DQ E DQ VSS VCC VSS VCC VSS DQ F DQ VCC VSS VSS VSS VCC DQ G DQ VSS VCC VSS VCC VSS DQ H DQ VCC VSS VSS VSS VCC DQ J NC VSS VCC VSS VCC VSS NC K DQ VCC VSS VSS VSS VCC DQ L DQ VSS VCC VSS VCC VSS DQ M DQ VCC VSS VSS VSS VCC DQ N DQ VSS VCC VSS VCC VSS DQ P DQ VCC VSS VSS VSS VCC DQ R DQ NC NC NC NC NC DQ T NC A A WE A A NC U NC A A OE A A NC Document #: 38-05149 Rev. *B Page 2 of 11 CY7C1024AV33 Pin Configurations (continued) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 NC NC A11 A12 A13 A14 A15 CE2 VCC VSS CE1# CE# A16 A5 A4 A3 NC NC NC NC 100-pin TQFP Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC VCC VSS DQ0 DQ1 VSS VCC DQ2 DQ3 VSS VCC DQ4 DQ5 VCC NC NC VSS DQ6 DQ7 VCC VSS DQ8 DQ9 VCC VSS DQ10 DQ11 VCC VSS NC NC NC NC NC A10 A9 A8 A7 OE# VSS VCC WE# A6 A0 A1 A2 NC NC NC NC 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC VCC VSS DQ16 DQ17 VSS VCC DQ18 DQ19 VSS VCC DQ20 DQ21 VCC NC NC VSS DQ22 DQ23 VCC VSS DQ12 DQ13 VCC VSS DQ14 DQ15 VCC VSS NC Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-Up Current..................................................... >200 mA Operating Range Supply Voltage on VCC to Relative GND[2] .... –0.5V to +7.0V Range Ambient Temperature DC Voltage Applied to Outputs in High Z State[2] ....................................–0.5V to VCC + 0.5V VCC Commercial 0°C to +70°C 3.3V ±10% –40°C to +85°C 3.3V ±10% DC Input Voltage[2].................................–0.5V to VCC + 0.5V Industrial Note: 2. Minimum Voltage is = –2.0V for pulse durations of less than 20 ns. Document #: 38-05149 Rev. *B Page 3 of 11 CY7C1024AV33 Electrical Characteristics Over the Operating Range Parameter Description Test Conditions[3] 1024AV33-10 1024AV33-12 1024AV33-15 Min. Min. Min. Max. VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage VIL Input LOW Voltage[2] IIX Input Load Current GND < VI < VCC IOZ Output Leakage Current GND < VI < VCC, Output Disabled ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC 275 ISB1 Automatic CE Power-Down Current —TTL Inputs Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX ISB2 Automatic CE Power-Down Current —CMOS Inputs Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 Max. 2.4 0.4 Max. Unit 2.4 0.4 V 0.4 V V 2.2 VCC + 0.3 2.2 VCC + 0.3 2.2 VCC + 0.3 –0.3 0.8 –0.3 0.8 –0.3 0.8 V –3 +3 –3 +3 –3 +3 µA –5 +5 –5 +5 –5 +5 µA 250 225 mA 60 60 60 mA 15 15 15 mA Capacitance[4] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. Unit 10 pF 8 pF TA = 25°C, f = 1 MHz, VCC = 3.3V AC Test Loads and Waveforms R1 480 Ω R1 480 Ω 3.3V ALL INPUT PULSES 3.0V 3.3V OUTPUT 90% OUTPUT 30 pF R2 255Ω INCLUDING JIG AND SCOPE (a) 5 pF R2 255Ω INCLUDING JIG AND SCOPE (b) GND ≤ 3 ns 10% 90% 10% ≤ 3 ns THÉVENIN EQUIVALENT 167 Ω 1.73V OUTPUT Equivalent to: Notes: 3. CE is a combination of CE1, CE2, and CE3 4. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05149 Rev. *B Page 4 of 11 CY7C1024AV33 Switching Characteristics[5] Over the Operating Range [3] Parameter Description 7C1024AV33-10 7C1024AV33-12 7C1024AV33-15 Min. Min. Min. Max. Max. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE active to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to Low Z tHZOE tLZCE 10 [7] 3 3 CE inactive to High Z tPU CE active to Power-Up tPD CE inactive to Power-Down 3 6 0 5 6 5 ns 7 ns ns 6 6 10 15 3 0 ns ns 6 0 12 ns ns 0 3 0 ns 15 12 5 [6, 7] 15 12 10 [6, 7] tHZCE WRITE CYCLE 3 0 OE HIGH to High Z CE active to Low Z 12 10 ns ns 15 ns [8, 9] tWC Write Cycle Time 10 12 15 ns tSCE CE active to Write End 8 9 9 ns tAW Address Set-Up to Write End 7 8 8 ns tHA Address Hold from Write End 0 0 0 ns tSA Address Set-Up to Write Start 0 0 0 ns tPWE WE Pulse Width 7 8 8 ns tSD Data Set-Up to Write End 5 6 6 ns tHD Data Hold from Write End 0 0 0 ns [7] tLZWE WE HIGH to Low Z tHZWE WE LOW to High Z[6, 7] 3 3 5 3 6 ns 6 ns Notes: 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05149 Rev. *B Page 5 of 11 CY7C1024AV33 Switching Waveforms Read Cycle No. 1[10, 11] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[3, 11, 12] ADDRESS tRC CE tACE OE tHZOE tDOE DATA OUT tHZCE tLZOE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU ICC 50% 50% ISB Write Cycle No. 1 (CE Controlled)[3, 13, 14] tWC ADDRESS tSCE CE tSA tSCE tHA tAW tPWE WE tSD DATA I/O tHD DATA VALID Notes: 10. Device is continuously selected. OE, CE = VIL. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE transition LOW. 13. Data I/O is high impedance if OE = VIH. 14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05149 Rev. *B Page 6 of 11 CY7C1024AV33 Switching Waveforms (continued) Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13, 14] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE OE tSD DATA I/O tHD DATAIN VALID NOTE 15 tHZOE Write Cycle No. 3 (WE Controlled, OE LOW)[3, 14] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA I/O NOTE 15 tHD DATA VALID tHZWE tLZWE Note: 15. During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05149 Rev. *B Page 7 of 11 CY7C1024AV33 Truth Table CE1 CE2 CE3 OE WE I/O0–I/O23 Mode Power H X X X X High Z Power-Down Standby (ISB) X L X X X High Z Power-Down Standby (ISB) X X H X X High Z Power-Down Standby (ISB) L H L L H Data Out Read Active (ICC) L H L X L Data In Write Active (ICC) L H L H H High Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) Ordering Code 10 CY7C1024AV33-10AC 12 CY7C1024AV33-12AC CY7C1024AV33-10BGC 15 Package Name Package Type Operating Range A101 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) Commercial BG119 A101 119-Ball PBGA 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) CY7C1024AV33-12BGC BG119 119-Ball PBGA CY7C1024AV33-12BGI BG119 119-Ball PBGA CY7C1024AV33-15AC A101 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) CY7C1024AV33-15BGC BG119 119-Ball PBGA CY7C1024AV33-15BGI BG119 119-Ball PBGA Document #: 38-05149 Rev. *B Industrial Commercial Industrial Page 8 of 11 CY7C1024AV33 Package Diagrams 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 51-85050-*A Document #: 38-05149 Rev. *B Page 9 of 11 CY7C1024AV33 Package Diagrams (continued) 119-Lead PBGA (14 x 22 x 2.4 mm) BG119 51-85115-*B All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05149 Rev. *B Page 10 of 11 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1024AV33 Document History Page Document Title: CY7C1024AV33 128K x 24 Static RAM Document Number: 38-05149 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 109893 09/22/01 SZV Change from Spec number: 38-00983 to 38-05149 *A 116473 09/16/02 CEA Add applications foot note to data sheet, page 1. *B 121472 11/14/02 DSG Update package diagram 51-85115 (BG119) to rev. *B Document #: 38-05149 Rev. *B Page 11 of 11