CY7C1024AV33-12AC

024AV33 CY7C1024AV33 128K x 24 Static RAM Features • High speed — tAA = 10 ns • CMOS for optimum speed/power • Center power/ground pinout • Automatic power-down when deselected • Easy memory expansion with CE1, CE2, CE3 and OE options Writing to the device is accomplished by taking Chip Enable (CE1, CE2, CE3) active and Write Enable (WE) inputs LOW. Data on the 24 I/O pins (I/O0 through I/O23) is then written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable (CE1, CE2, CE3) active and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The 24 input/output pins (I/O0 through I/O23) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE1, CE3 LOW, CE2 HIGH, and WE LOW). The CY7C1024AV33 is available in a standard 119-ball BGA package and a 100-pin TQFP package. Functional Description[1] The CY7C1024AV33 is a high-performance CMOS static RAM organized as 131,072 words by 24 bits. Easy memory expansion is provided by an active LOW CE1, CE3, active HIGH CE2, an active LOW Output Enable (OE), and three-state drivers. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Functional Block Diagram VCC VSS A0 ADDRESS BUFFER ROW DECODER DQ0 MEMORY ARRAY 128K X 24 I/O BUFFER DQ23 A16 COLUMN DECODER CONTROL CE# CE1# CE2 WE# OE# Selection Guide 7C1024AV33-10 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA) 10 275 15 7C1024AV33-12 12 250 15 7C1024AV33-15 15 225 15 Note: 1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05149 Rev. *B • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised November 13, 2002 CY7C1024AV33 Pin Configurations 119 BGA Top View 1 A B C D E F G H J K L M N P R T U NC NC DQ DQ DQ DQ DQ DQ NC DQ DQ DQ DQ DQ DQ NC NC 2 A A NC VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC NC A A 3 A A CE2 VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS NC A A 4 A CE1 NC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC WE OE 5 A A CE3 VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS NC A A 6 A A NC VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC NC A A 7 NC NC DQ DQ DQ DQ DQ DQ NC DQ DQ DQ DQ DQ DQ NC NC Document #: 38-05149 Rev. *B Page 2 of 11 CY7C1024AV33 Pin Configurations (continued) 100-pin TQFP Top View NC NC A11 A12 A13 A14 A15 CE2 VCC VSS CE1# CE# A16 A5 A4 A3 NC NC NC NC NC VCC VSS DQ16 DQ17 VSS VCC DQ18 DQ19 VSS VCC DQ20 DQ21 VCC NC NC VSS DQ22 DQ23 VCC VSS DQ12 DQ13 VCC VSS DQ14 DQ15 VCC VSS NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC VCC VSS DQ0 DQ1 VSS VCC DQ2 DQ3 VSS VCC DQ4 DQ5 VCC NC NC VSS DQ6 DQ7 VCC VSS DQ8 DQ9 VCC VSS DQ10 DQ11 VCC VSS NC Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VCC to Relative GND[2] .... –0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[2] .................................... –0.5V to VCC + 0.5V DC Input Voltage[2]................................. –0.5V to VCC + 0.5V Note: 2. Minimum Voltage is = –2.0V for pulse durations of less than 20 ns. NC NC NC NC A10 A9 A8 A7 OE# VSS VCC WE# A6 A0 A1 A2 NC NC NC NC 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-Up Current..................................................... >200 mA Operating Range Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 3.3V ±10% 3.3V ±10% Document #: 38-05149 Rev. *B Page 3 of 11 CY7C1024AV33 Electrical Characteristics Over the Operating Range 1024AV33-10 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[2] Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current — TTL Inputs Automatic CE Power-Down Current — CMOS Inputs GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 Test Conditions[3] Min. 2.4 0.4 2.2 –0.3 –3 –5 VCC + 0.3 0.8 +3 +5 275 2.2 –0.3 –3 –5 Max. VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA 1024AV33-12 Min. 2.4 0.4 VCC + 0.3 0.8 +3 +5 250 2.2 –0.3 –3 –5 Max. 1024AV33-15 Min. 2.4 0.4 VCC + 0.3 0.8 +3 +5 225 Max. Unit V V V V µA µA mA ISB1 60 60 60 mA ISB2 15 15 15 mA Capacitance[4] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max. 10 8 Unit pF pF AC Test Loads and Waveforms R1 480 Ω R1 480 Ω 3.3V OUTPUT 30 pF INCLUDING JIG AND SCOPE (a) R2 255 Ω 5 pF INCLUDING JIG AND SCOPE (b) R2 255Ω GND ≤ 3 ns 3.0V 90% 10% 90% 10% ≤ 3 ns ALL INPUT PULSES 3.3V OUTPUT Equivalent to: THÉVENIN EQUIVALENT 167 Ω 1.73V OUTPUT Notes: 3. CE is a combination of CE1, CE2, and CE3 4. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05149 Rev. *B Page 4 of 11 CY7C1024AV33 Switching Characteristics[5] Over the Operating Range 7C1024AV33-10 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CE active to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z CE active to Low Z [6, 7] [7] [6, 7] 7C1024AV33-12 Min. 12 Max. 7C1024AV33-15 Min. 15 Max. Unit ns 15 3 15 7 0 6 3 6 0 15 15 9 8 0 0 8 6 0 3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 6 ns Description [3] Min. 10 Max. 10 3 10 5 0 5 3 5 0 10 10 8 7 0 0 7 5 0 3 5 12 9 8 0 0 8 6 0 3 0 3 0 3 12 12 6 6 6 12 CE inactive to High Z CE active to Power-Up CE inactive to Power-Down [8, 9] WRITE CYCLE Write Cycle Time CE active to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z [7] WE LOW to High Z[6, 7] 6 Notes: 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05149 Rev. *B Page 5 of 11 CY7C1024AV33 Switching Waveforms Read Cycle No. 1[10, 11] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[3, 11, 12] ADDRESS tRC CE tACE OE tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZOE tHZCE DATA VALID tPD 50% ISB ICC HIGH IMPEDANCE DATA OUT Write Cycle No. 1 (CE Controlled)[3, 13, 14] tWC ADDRESS tSCE CE tSA tSCE tAW tPWE WE tSD DATA I/O DATA VALID tHD tHA Notes: 10. Device is continuously selected. OE, CE = VIL. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE transition LOW. 13. Data I/O is high impedance if OE = VIH. 14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05149 Rev. *B Page 6 of 11 CY7C1024AV33 Switching Waveforms (continued) Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13, 14] tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA OE tSD DATA I/O NOTE 15 tHZOE DATAIN VALID tHD Write Cycle No. 3 (WE Controlled, OE LOW)[3, 14] tWC ADDRESS tSCE CE tAW tSA WE tSD DATA I/O NOTE 15 tHZWE Note: 15. During this period the I/Os are in the output state and input signals should not be applied. tHA tPWE tHD DATA VALID tLZWE Document #: 38-05149 Rev. *B Page 7 of 11 CY7C1024AV33 Truth Table CE1 H X X L L L CE2 X L X H H H CE3 X X H L L L OE X X X L X H WE X X X H L H I/O0–I/O23 High Z High Z High Z Data Out Data In High Z Power-Down Power-Down Power-Down Read Write Selected, Outputs Disabled Mode Power Standby (ISB) Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 10 12 Ordering Code CY7C1024AV33-10AC CY7C1024AV33-10BGC CY7C1024AV33-12AC CY7C1024AV33-12BGC CY7C1024AV33-12BGI 15 CY7C1024AV33-15AC CY7C1024AV33-15BGC CY7C1024AV33-15BGI Package Name A101 BG119 A101 BG119 BG119 A101 BG119 BG119 119-Ball PBGA 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) 119-Ball PBGA 119-Ball PBGA 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) 119-Ball PBGA 119-Ball PBGA Industrial Industrial Commercial Package Type 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) Operating Range Commercial Document #: 38-05149 Rev. *B Page 8 of 11 CY7C1024AV33 Package Diagrams 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 51-85050-*A Document #: 38-05149 Rev. *B Page 9 of 11 CY7C1024AV33 Package Diagrams (continued) 119-Lead PBGA (14 x 22 x 2.4 mm) BG119 51-85115-*B All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05149 Rev. *B Page 10 of 11 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1024AV33 Document History Page Document Title: CY7C1024AV33 128K x 24 Static RAM Document Number: 38-05149 REV. ** *A *B ECN NO. 109893 116473 121472 Issue Date 09/22/01 09/16/02 11/14/02 Orig. of Change SZV CEA DSG Description of Change Change from Spec number: 38-00983 to 38-05149 Add applications foot note to data sheet, page 1. Update package diagram 51-85115 (BG119) to rev. *B Document #: 38-05149 Rev. *B Page 11 of 11