CY7C1041B-20VXI

CY7C1041B 256K x 16 Static RAM Features • High speed — tAA = 12 ns • Low active power — 1540 mW (max.) • Low CMOS standby power (L version) — 2.75 mW (max.) • 2.0V Data Retention (400 µW at 2.0V retention) • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE and OE features (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1041B is available in a standard 44-pin 400-mil-wide body width SOJ and 44-pin TSOP II package with center power and ground (revolutionary) pinout. Functional Description The CY7C1041B is a high-performance CMOS static RAM organized as 262,144 words by 16 bits. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable Logic Block Diagram INPUT BUFFER Pin Configuration SOJ TSOP II Top View A0 A1 A2 A3 A4 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A0 A1 A2 A3 A4 A5 A6 A7 A8 256K x 16 ARRAY 1024 x 4096 I/O0–I/O7 I/O8–I/O15 COLUMN DECODER BHE WE CE OE BLE A17 A16 A15 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A14 A13 A12 A11 A10 ROW DECODER A9 A10 A 11 A 12 A 13 A14 A15 A16 A17 SENSE AMPS Cypress Semiconductor Corporation Document #: 38-05142 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised March 24, 2005 CY7C1041B Selection Guide 7C1041B-12 7C1041B-15 7C1041B-17 7C1041B-20 7C1041B-25 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Com’l Ind’l Com’l Com’l Ind’l L 12 200 220 3 15 190 210 3 0.5 6 17 180 200 3 0.5 6 20 170 190 3 0.5 6 25 160 180 3 0.5 6 mA Unit ns mA Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VCC to Relative GND[1] .... –0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] ....................................–0.5V to VCC + 0.5V DC Input Voltage[1] ................................ –0.5V to VCC + 0.5V Current into Outputs (LOW)......................................... 20 mA Operating Range Range Commercial Industrial Ambient Temperature[2] 0°C to +70°C –40°C to +85°C VCC 5V ± 0.5 Electrical Characteristics Over the Operating Range 7C1041B-12 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current —TTL Inputs Automatic CE Power-Down Current —CMOS Inputs GND < VI < VCC GND < VOUT < VCC, Output Disabled VCC = Max., f = fMAX = 1/tRC Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 Com’l Com’l Ind’l L Com’l Ind’l Test Conditions VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA 2.2 –0.5 –1 –1 Min. 2.4 0.4 VCC + 0.5 0.8 +1 +1 200 220 40 2.2 –0.5 –1 –1 Max. 7C1041B-15 Min. 2.4 0.4 VCC + 0.5 0.8 +1 +1 190 210 40 2.2 –0.5 –1 –1 Max. 7C1041B-17 Min. 2.4 0.4 VCC + 0.5 0.8 +1 +1 180 200 40 Max. Unit V V V V mA mA mA mA mA ISB2 3 - 3 0.5 6 3 0.5 6 mA mA mA Notes: 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 2. TA is the case temperature. Document #: 38-05142 Rev. *A Page 2 of 11 CY7C1041B Electrical Characteristics Over the Operating Range (continued) Test Conditions Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current —TTL Inputs Automatic CE Power-Down Current —CMOS Inputs GND < VI < VCC GND < VOUT < VCC, Output Disabled VCC = Max., f = fMAX = 1/tRC Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 Com’l Com’l Ind’l L Com’l Ind’l VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA 2.2 –0.5 –1 –1 7C1041B-20 Min. 2.4 0.4 VCC + 0.5 0.8 +1 +1 170 190 40 2.2 –0.5 –1 –1 Max. 7C1041B-25 Min. 2.4 0.4 VCC + 0.5 0.8 +1 +1 160 180 40 Max. Unit V V V V mA mA mA mA mA 3 0.5 6 3 0.5 6 mA mA mA Capacitance[3] Parameter CIN COUT Description Input Capacitance I/O Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 8 8 Unit pF pF AC Test Loads and Waveforms 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE (a) Equivalent to: R2 255Ω R1 481Ω 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE (b) R2 255Ω GND ≤ 3 ns R1 481 Ω 3.0V ALL INPUT PULSES 90% 10% 90% 10% ≤ 3 ns THÉVENIN EQUIVALENT 167Ω 1.73V OUTPUT Note: 3. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05142 Rev. *A Page 3 of 11 CY7C1041B Switching Characteristics[4] Over the Operating Range 7C1041B-12 Parameter Read Cycle tpower tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW VCC(typical) to the First Access[5] Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z[6, 7] CE LOW to Low Z[7] Z[6, 7] 0 12 6 0 6 12 10 10 0 0 10 7 0 3 6 10 12 15 12 12 0 0 12 8 0 3 7 12 0 7 17 14 14 0 0 14 8 0 3 7 3 6 0 15 7 0 7 CE HIGH to High 0 6 3 7 0 17 7 3 12 6 0 7 3 7 1 12 12 3 15 7 0 7 1 15 15 3 17 7 1 17 17 µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. 7C1041B-15 Min. Max. 7C1041B-17 Min. Max. Unit CE LOW to Power-Up CE HIGH to Power-Down Byte Enable to Data Valid Byte Enable to Low Z Byte Disable to High Z Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low WE LOW to High Z[7] Z[6, 7] Write Cycle[8, 9] Byte Enable to End of Write Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. This part has a voltage regulator which steps down the voltage from 5V to 3.3V internally. tpower time has to be provided initially before a read/write operation is started. 6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05142 Rev. *A Page 4 of 11 CY7C1041B Switching Characteristics[4] Over the Operating Range (continued) 7C1041B-20 Parameter Read Cycle tpower tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE WRITE tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW VCC(typical) to the First Access[5] Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z CE LOW to Low CE HIGH to High [6, 7] 7C1041B-25 Min. 1 25 Max. Unit µs ns 25 5 25 10 0 10 5 10 0 25 10 0 10 25 15 15 0 0 15 10 0 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 15 ns ns Description Min. 1 20 Max. 20 3 20 8 0 8 3 8 0 20 8 0 8 20 13 13 0 0 13 9 0 3 8 13 Z[7] Z[6, 7] CE LOW to Power-Up CE HIGH to Power-Down Byte Enable to Data Valid Byte Enable to Low Z Byte Disable to High Z CYCLE[8, 9] Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low WE LOW to High Z[7] Z[6, 7] Byte Enable to End of Write Data Retention Characteristics Over the Operating Range (L version only) Parameter VDR ICCDR tCDR[3] tR[10] Description VCC for Data Retention Data Retention Current Com’l L Chip Deselect to Data Retention Time Operation Recovery Time VCC = VDR = 3.0V, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V Conditions[11] Min. 2.0 200 0 tRC Max. Unit V mA ns ns Notes: 10. tr < 3 ns for the -12 and -15 speeds. tr < 5 ns for the -20 and slower speeds. 11. No input may exceed VCC + 0.5V. Document #: 38-05142 Rev. *A Page 5 of 11 CY7C1041B Data Retention Waveform DATA RETENTION MODE VCC CE 3.0V tCDR VDR > 2V 3.0V tR Switching Waveforms Read Cycle No. 1[12, 13] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Read Cycle No. 2 (OE Controlled)[13, 14] ADDRESS tRC CE tACE OE BHE, BLE tDOE tLZOE tDBE tLZBE DATA OUT VCC SUPPLY CURRENT HIGH IMPEDANCE tLZCE tPU 50% DATA VALID tPD 50% ISB tHZCE tHZBE tHZOE HIGH IMPEDANCE ICC Notes: 12. Device is continuously selected. OE, CE, BHE, and/or BHE = VIL. 13. WE is HIGH for read cycle. 14. Address valid prior to or coincident with CE transition LOW. Document #: 38-05142 Rev. *A Page 6 of 11 CY7C1041B Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[15, 16] tWC ADDRESS CE tSA tSCE tAW tPWE WE tBW BHE, BLE tSD DATAI/O tHD tHA Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tPWE WE tSCE CE tSD DATAI/O tHD tHA Notes: 15. Data I/O is high impedance if OE or BHE and/or BLE= VIH. 16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05142 Rev. *A Page 7 of 11 CY7C1041B Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) tWC ADDRESS CE tSCE tAW tSA WE tBW BHE, BLE tHZWE DATA I/O tSD tHD tPWE tHA tLZWE Truth Table CE H L L L L L L L OE X L L L X X X H WE X H H H L L L H BLE X L L H L L H X BHE X L H L L H L X I/O0–I/O7 High Z Data Out Data Out High Z Data In Data In High Z High Z I/O8–I/O15 High Z Data Out High Z Data Out Data In High Z Data In High Z Read All bits Read Lower bits only Read Upper bits only Write All bits Write Lower bits only Write Upper bits only Selected, Outputs Disabled Mode Power Down Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Document #: 38-05142 Rev. *A Page 8 of 11 CY7C1041B Ordering Information Speed (ns) 12 Ordering Code CY7C1041B-12VC CY7C1041B-12VXC CY7C1041B-12ZC CY7C1041B-12ZXC 15 CY7C1041B-15VC CY7C1041B-15VXC CY7C1041BL-15VC CY7C1041B-15ZC CY7C1041B-15ZXC CY7C1041BL-15ZC CY7C1041BL-15ZXC 17 CY7C1041B-17VC CY7C1041BL-17VC CY7C1041B-17ZC CY7C1041BL-17ZC 20 CY7C1041B-20VC CY7C1041B-20VXC CY7C1041BL-20VC CY7C1041BL-20VXC CY7C1041B-20ZC CY7C1041B-20ZXC CY7C1041BL-20ZC 25 CY7C1041B-25VC CY7C1041BL-25VC CY7C1041B-25ZC CY7C1041BL-25ZC 15 CY7C1041B-15ZI CY7C1041B-15ZXI CY7C1041B-15VI CY7C1041B-15VXI 17 20 CY7C1041B-17ZI CY7C1041B-17VI CY7C1041B-20ZI CY7C1041B-20ZXI CY7C1041B-20VI CY7C1041B-20VXI 25 CY7C1041B-25ZI CY7C1041B-25VI Package Name V34 V34 Z44 Z44 V34 V34 V34 Z44 Z44 Z44 Z44 V34 V34 Z44 Z44 V34 V34 V34 V34 Z44 Z44 Z44 V34 V34 Z44 Z44 Z44 Z44 V34 V34 V34 Z44 Z44 Z44 Z44 Z44 Z44 Z44 Package Type 44-Lead (400-Mil) Molded SOJ 44-Lead (400-Mil) Molded SOJ (Pb-free) 44-Lead TSOP Type II 44-Lead TSOP Type II (Pb-free) 44-Lead (400-Mil) Molded SOJ 44-Lead (400-Mil) Molded SOJ (Pb-free) 44-Lead (400-Mil) Molded SOJ 44-Lead TSOP Type II 44-Lead TSOP Type II (Pb-free) 44-Lead TSOP Type II 44-Lead TSOP Type II (Pb-free) 44-Lead (400-Mil) Molded SOJ 44-Lead (400-Mil) Molded SOJ 44-Lead TSOP Type II 44-Lead TSOP Type II 44-Lead (400-Mil) Molded SOJ 44-Lead (400-Mil) Molded SOJ (Pb-free) 44-Lead (400-Mil) Molded SOJ 44-Lead (400-Mil) Molded SOJ (Pb-free) 44-Lead TSOP Type II 44-Lead TSOP Type II (Pb-free) 44-Lead TSOP Type II 44-Lead (400-Mil) Molded SOJ 44-Lead (400-Mil) Molded SOJ 44-Lead TSOP Type II 44-Lead TSOP Type II 44-Lead TSOP Type II 44-Lead TSOP Type II (Pb-free) 44-Lead (400-Mil) Molded SOJ 44-Lead (400-Mil) Molded SOJ (Pb-free) 44-Lead TSOP Type II 44-Lead (400-Mil) Molded SOJ 44-Lead TSOP Type II 44-Lead TSOP Type II (Pb-free) 44-Lead (400-Mil) Molded SOJ 44-Lead (400-Mil) Molded SOJ (Pb-free) 44-Lead TSOP Type II 44-Lead (400-Mil) Molded SOJ Industrial Operating Range Commercial Document #: 38-05142 Rev. *A Page 9 of 11 CY7C1041B Package Diagrams 44-Lead (400-Mil) Molded SOJ V34 51-85082-*B 44-Pin TSOP II Z44 51-85087-*A All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05142 Rev. *A Page 10 of 11 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C1041B Document History Page Document Title: CY7C1041B 256K x 16 Static RAM Document Number: 38-05142 REV. ** *A ECN NO. 109886 341401 Issue Date 09/15/01 See ECN Orig. of Change SZV AJU Description of Change Change from Spec number: 38-00938 to 38-05142 Added Pb-free ordering information Document #: 38-05142 Rev. *A Page 11 of 11