CY7C1041BNV33

CY7C1041BNV33 256 K × 16 Static RAM 256 K × 16 Static RAM Features ■ Functional Description The CY7C1041BNV33 is a high-performance CMOS Static RAM organized as 262,144 words by 16 bits. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1041BNV33 is available in a standard 44-pin 400-mil-wide body width SOJ and 44-pin TSOP II package with center power and ground (revolutionary) pinout. High speed ❐ tAA = 12 ns Low active power ❐ 612 mW (max.) Low CMOS standby power ❐ 1.8 mW (max.) 2.0 V Data Retention (660 W at 2.0 V retention) Automatic power-down when deselected TTL-compatible inputs and outputs Easy memory expansion with CE and OE features ■ ■ ■ ■ ■ ■ Logic Block Diagram INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 ROW DECODER SENSE AMPS 256K x 16 ARRAY 1024 x 4096 I/O0 – I/O7 I/O8 – I/O15 COLUMN DECODER A9 A10 A 11 A 12 A 13 A14 A15 A16 A17 BHE WE CE OE BLE Cypress Semiconductor Corporation Document #: 001-06434 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 30, 2011 [+] Feedback CY7C1041BNV33 Contents Pin Configuration ............................................................. 3 Selection Guide ................................................................ 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 4 AC Test Loads and Waveforms ....................................... 4 Switching Characteristics ................................................ 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 Switching Waveforms ...................................................... 7 Read Cycle No. 1 ........................................................ 7 Read Cycle No. 2 (OE Controlled) .............................. 7 Write Cycle No. 1 (CE Controlled) ............................... 8 Write Cycle No. 2 (BLE or BHE Controlled) ................ 8 Truth Table ........................................................................ 9 Write Cycle No. 3 (WE Controlled, OE LOW) ............. 9 Ordering Information ...................................................... 10 Ordering Code Definitions ......................................... 10 Package Diagrams .......................................................... 11 Acronyms ........................................................................ 12 Document Conventions ................................................. 12 Units of Measure ....................................................... 12 Document History Page ................................................. 13 Sales, Solutions, and Legal Information ...................... 14 Worldwide Sales and Design Support ....................... 14 Products .................................................................... 14 PSoC Solutions ......................................................... 14 Document #: 001-06434 Rev. *C Page 2 of 14 [+] Feedback CY7C1041BNV33 Pin Configuration SOJ TSOP II Top View A0 A1 A2 A3 A4 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A14 A13 A12 A11 A10 Selection Guide -12 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) Commercial Commercial 12 190 0.5 Document #: 001-06434 Rev. *C Page 3 of 14 [+] Feedback CY7C1041BNV33 Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................ –65 °C to +150 °C Ambient Temperature with Power Applied .......................................... –55 °C to +125 °C Supply Voltage on VCC to Relative GND[1] ...–0.5 V to +4.6 V DC Voltage Applied to Outputs in High Z State[1] .................................. –0.5 V to VCC + 0.5 V DC Input Voltage[1] .............................. –0.5 V to VCC + 0.5 V Current into Outputs (LOW)......................................... 20 mA Operating Range Range Commercial Ambient Temperature[2] 0 °C to +70 °C VCC 3.3 V ± 0.3 V Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] GND < VI < VCC GND < VOUT < VCC, Output Disabled VCC = Max., f = fMAX = 1/tRC Commercial Input Leakage Current Output Leakage Current VCC Operating Supply Current Test Conditions VCC = Min, IOH = –4.0 mA VCC = Min, IOL = 8.0 mA -12 Min 2.4 – 2.2 –0.5 –1 –1 – – – Max – 0.4 VCC + 0.5 0.8 +1 +1 190 40 0.5 Unit V V V V mA mA mA mA mA Automatic CE Power-Down Current Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX —TTL Inputs Automatic CE Power-Down Current Max. VCC, CE > VCC – 0.3V, Commercial —CMOS Inputs VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 Capacitance[3] Parameter CIN COUT Description Input Capacitance I/O Capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = 3.3 V Max 8 8 Unit pF pF AC Test Loads and Waveforms 3.3 V OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 351 R1 317  THÉVENIN EQUIVALENT OUTPUT 167  1.73 V GND Rise time: 1 V/ns 3.3 V ALL INPUT PULSES 90% 10% 90% 10% Fall time: 1 V/ns (b) (a) Notes 1. VIL (min.) = –2.0 V for pulse durations of less than 20 ns. 2. TA is the “Instant On” case temperature. 3. Tested initially and after any design or process changes that may affect these parameters. Document #: 001-06434 Rev. *C Page 4 of 14 [+] Feedback CY7C1041BNV33 Switching Characteristics[4] Over the Operating Range Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE WRITE tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW CYCLE[7, 8] Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z [6] Description -12 Min 12 – 3 – – 0 – 3 – 0 – – 0 – 12 10 10 0 0 10 7 0 3 – 10 Max – 12 – 12 6 – 6 – 6 – 12 6 – 6 – – – – – – – – – 6 – Unit Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High CE LOW to Low Z[5, 6] Z[6] ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CE HIGH to High Z[5, 6] CE LOW to Power-Up CE HIGH to Power-Down Byte Enable to Data Valid Byte Enable to Low Z Byte Disable to High Z WE LOW to High Z[5, 6] Byte Enable to End of Write Notes 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads and Waveforms on page 4. Transition is measured ±500 mV from steady-state voltage. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 8. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 001-06434 Rev. *C Page 5 of 14 [+] Feedback CY7C1041BNV33 Data Retention Characteristics Over the Operating Range Parameter VDR ICCDR tCDR[10] tR[11] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC = VDR = 2.0 V, CE > VCC – 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V Conditions[9] Min 2.0 – 0 tRC Max – 330 – – Unit V A ns ns Data Retention Waveform DATA RETENTION MODE VCC CE 3.0 V tCDR VDR > 2 V 3.0 V tR Notes 9. No input may exceed VCC + 0.5V. 10. Tested initially and after any design or process changes that may affect these parameters. 11. tr < 3 ns for the -12 and -15 speeds. Document #: 001-06434 Rev. *C Page 6 of 14 [+] Feedback CY7C1041BNV33 Switching Waveforms Read Cycle No. 1[12, 13] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Read Cycle No. 2 (OE Controlled)[13, 14] ADDRESS tRC CE tACE OE BHE, BLE tDOE tLZOE tDBE tLZBE DATA OUT VCC SUPPLY CURRENT HIGH IMPEDANCE tLZCE tPU 50% DATA VALID tPD 50% tHZCE tHZBE tHZOE HIGH IMPEDANCE ICC ISB Notes 12. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. 13. WE is HIGH for read cycle. 14. Address valid prior to or coincident with CE transition LOW. Document #: 001-06434 Rev. *C Page 7 of 14 [+] Feedback CY7C1041BNV33 Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[15, 16] tWC ADDRESS CE tSA tSCE tAW tPWE WE tBW BHE, BLE tSD DATAI/O tHD tHA Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tPWE WE tSCE CE tSD DATAI/O tHD tHA Notes 15. Data I/O is high-impedance if OE or BHE and/or BLE= VIH. 16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high–impedance state. Document #: 001-06434 Rev. *C Page 8 of 14 [+] Feedback CY7C1041BNV33 Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) tWC ADDRESS CE tSCE tAW tSA WE tBW BHE, BLE tHZWE DATA I/O tSD tHD tPWE tHA tLZWE Truth Table CE H L L L L L L L OE X L L L X X X H WE X H H H L L L H BLE X L L H L L H X BHE X L H L L H L X I/O0–I/O7 High Z Data Out Data Out High Z Data In Data In High Z High Z I/O8–I/O15 High Z Data Out High Z Data Out Data In High Z Data In High Z Mode Power Down Read All Bits Read Lower Bits Only Read Upper Bits Only Write All Bits Write Lower Bits Only Write Upper Bits Only Selected, Outputs Disabled Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Document #: 001-06434 Rev. *C Page 9 of 14 [+] Feedback CY7C1041BNV33 Ordering Information Speed (ns) 12 Ordering Code CY7C1041BNV33L-12VXC CY7C1041BNV33L-12ZXC Package Diagram 51-85082 51-85087 Package Type 44-pin (400-Mil) Molded SOJ (Pb-free) 44-pin TSOP II (Pb-free) Operating Range Commercial Ordering Code Definitions CY 7 C 1 04 1 BN V33 L - 12 XX C Temperature Range: C = Commercial Package Type: XX = VX or ZX VX = 44-pin Molded SOJ (Pb-free) ZX = 44-pin TSOP II (Pb-free) Speed: 12 ns L = Low Power V33 = Voltage range (3 V to 3.6 V) BN = 0.25 µm Technology 1 = Data width × 16-bits 04 = 4-Mbit density 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS 7 = SRAM CY = Cypress Please contact local sales representative regarding availability of these parts. Document #: 001-06434 Rev. *C Page 10 of 14 [+] Feedback CY7C1041BNV33 Package Diagrams Figure 1. 44-Lead (400-Mil) Molded SOJ (51-85082) 51-85082 *C Figure 2. 44-Pin TSOP II (51-85087) 51-85087 *C Document #: 001-06434 Rev. *C Page 11 of 14 [+] Feedback CY7C1041BNV33 Acronyms Acronym CMOS CE I/O OE SRAM SOJ TTL TSOP WE Chip Enable Input/output Output Enable Static Random Access Memory Small Outline J-lead transistor-transistor logic thin small-outline package Write Enable Description Complementary metal oxide semiconductor °C A mA F s ms ns pF V  W mW W % Document Conventions Units of Measure Symbol Unit of Measure degree Celsius micro Amperes milli Amperes micro Farad micro seconds milli seconds nano seconds pico Farad Volts ohms micro Watts milli Watts Watts percent Document #: 001-06434 Rev. *C Page 12 of 14 [+] Feedback CY7C1041BNV33 Document History Page Document Title: CY7C1041BNV33 256 K × 16 Static RAM Document Number: 001-06434 REV. ** *A ECN NO. 423877 2899016 Issue Date See ECN See ECN Orig. of Change NXR VKN New Data Sheet Removed Industrial grade Removed 15ns speed Updated Ordering Information table Updated Package Diagrams Added Ordering Code Definitions. Updated Selection Guide. Added Acronyms and Units of Measure. Updated in new template. Description of Change *B *C 3109184 3210222 12/13/2010 03/30/2011 AJU PRAS Document #: 001-06434 Rev. *C Page 13 of 14 [+] Feedback CY7C1041BNV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2006-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. 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Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-06434 Rev. *C Revised March 30, 2011 Page 14 of 14 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback