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CY7C1041CV33-10BAJXET

CY7C1041CV33-10BAJXET

  • 厂商:

    CYPRESS(赛普拉斯)

  • 封装:

    TFBGA48

  • 描述:

    IC SRAM 4MBIT PARALLEL 48FBGA

  • 数据手册
  • 价格&库存
CY7C1041CV33-10BAJXET 数据手册
CY7C1041CV33 Automotive 4-Mbit (256 K × 16) Static RAM 4-Mbit (256 K × 16) Static RAM Features Functional Description ■ Temperature ranges ❐ Automotive-E: –40 °C to 125 °C The CY7C1041CV33 Automotive is a high performance complementary metal oxide semiconductor (CMOS) static RAM organized as 262,144 words by 16 bits. This device has an automatic power down feature that significantly reduces power consumption when deselected. ■ High speed ❐ tAA = 10 ns ■ Low active power ❐ 468 mW (max) ■ 2.0 V data retention ■ Automatic power down when deselected ■ Independent control of upper and lower bits ■ Easy memory expansion with Chip Enable (CE) and Output Enable (OE) features ■ Available in Pb-free 48-ball grid array (BGA) package To write to the device, take CE and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). To read from the device, take CE and OE LOW while forcing the Write Enable (WE) HIGH. If BLE is LOW, then data from the memory location specified by the address pins appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. For more information, see the Truth Table on page 10 for a complete description of Read and Write modes. The input and output pins (I/O0 through I/O15) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). For a complete list of related resources, click here. Logic Block Diagram ECC DECODER 256 K x 16 RAM ARRAY DATAIN  DRIVERS SENSE  AMPLIFIERS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER ECC ENCODER I/O0‐I/O7 I/O8‐I/O15 A10 A11 A12 A13 A14 A15 A16 A17 COLUMN  DECODER BHE WE OE CE BLE Cypress Semiconductor Corporation Document Number: 001-86495 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised December 22, 2017 CY7C1041CV33 Automotive Contents Pin Configuration ............................................................. 3 Selection Guide ................................................................ 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Switching Characteristics ................................................ 6 Switching Waveforms ...................................................... 7 Truth Table ...................................................................... 10 Ordering Information ...................................................... 11 Ordering Code Definitions ......................................... 11 Document Number: 001-86495 Rev. *D Package Diagrams .......................................................... 12 Acronyms ........................................................................ 13 Document Conventions ................................................. 13 Units of Measure ....................................................... 13 Document History Page ................................................. 14 Sales, Solutions, and Legal Information ...................... 15 Worldwide Sales and Design Support ....................... 15 Products .................................................................... 15 PSoC® Solutions ...................................................... 15 Cypress Developer Community ................................. 15 Technical Support ..................................................... 15 Page 2 of 15 CY7C1041CV33 Automotive Pin Configuration Figure 1. 48 ball BGA pinout [1] 1 2 3 4 5 6 A0 A1 A2 NC _____ _____ A BLE OE B I/O8 BHE A3 A4 CE I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 VSS I/O11 A17 A7 I/O3 VCC E VCC I/O12 NC A16 I/O4 VSS F I/O14 I/O13 A14 A15 I/O5 I/O6 I/O15 NC A12 A13 WE I/O7 NC A8 A9 A10 A11 NC D G H _____ _____ _____ Selection Guide Description -10 Maximum access time Unit 10 ns Maximum operating current Automotive-E 130 mA Maximum CMOS standby current Automotive-E 15 mA Note 1. NC pins are not connected on the die. Document Number: 001-86495 Rev. *D Page 3 of 15 CY7C1041CV33 Automotive DC input voltage [2] .............................. –0.5 V to VCC+ 0.5 V Maximum Ratings Current into outputs (LOW) ........................................ 20 mA Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Static discharge voltage (MIL-STD-883, method 3015) ................................. > 2001 V Storage temperature ................................ –65 C to +150 C Latch up current ..................................................... > 200 mA Ambient temperature with power applied .......................................... –55 C to +125 C Operating Range Supply voltage on VCC relative to GND [2] .........................................–0.5 V to +4.6 V Range DC voltage applied to outputs in High Z state [2] ................................. –0.5 V to VCC+ 0.5 V Automotive-E Ambient Temperature (TA) VCC –40 C to +125 C 3.3 V  10% Electrical Characteristics Over the Operating Range Parameter Description -10 Test Conditions VOH Output HIGH voltage VCC = Min, IOH = –4.0 mA VOL Output LOW voltage VCC = Min, IOL = 8.0 mA VIH Input HIGH voltage [2] Unit Min Max 2.4 – V – 0.4 V 2.0 VCC + 0.3 V VIL Input LOW voltage –0.3 0.8 V IIX Input leakage current GND < VI < VCC Automotive-E –20 +20 A IOZ Output leakage current GND < VI < VCC, Output disabled Automotive-E –20 +20 A ICC VCC operating supply current VCC = Max, IOUT = 0 mA, f = fMAX = 1/tRC Automotive-E – 130 mA ISB1 Automatic CE power down current – TTL Inputs Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX Automotive-E – 45 mA ISB2 Automatic CE power down current – CMOS inputs Max VCC, CE > VCC – 0.3 V, VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0 Automotive-E – 15 mA Note 2. VIL (min) = –2.0 V for pulse durations of less than 20 ns. Document Number: 001-86495 Rev. *D Page 4 of 15 CY7C1041CV33 Automotive Capacitance Parameter [3] Description CIN Input capacitance COUT Output capacitance Test Conditions Max Unit 8 pF 8 pF Test Conditions 48-ball BGA Unit Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 38.15 C/W 9.15 C/W TA = 25 C, f = 1 MHz, VCC = 3.3 V Thermal Resistance Parameter [3] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms [4] 10-ns devices: 12-ns devices: Z = 50  50  * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT R 317 3.3 V OUTPUT 30 pF* OUTPUT R2 351 30 pF* 1.5 V (b) (a) High-Z characteristics: 3.0 V GND ALL INPUT PULSES 90% 90% 10% 10% Rise Time: 1 V/ns (b) R 317 3.3 V Fall Time: 1 V/ns OUTPUT R2 351 5 pF (c) Notes 3. Tested initially and after any design or process changes that may affect these parameters. 4. AC characteristics (except High Z) for 10-ns parts are tested using the load conditions shown in Figure 2 (a). High Z characteristics are tested using the test load shown in Figure 2 (c). Document Number: 001-86495 Rev. *D Page 5 of 15 CY7C1041CV33 Automotive Switching Characteristics Over the Operating Range Parameter [5] Description -10 Min Max Unit Read Cycle tpower[6] VCC (typical) to the first access 100 – s tRC Read cycle time 10 – ns tAA Address to data valid – 10 ns tOHA Data hold from address change 3 – ns tACE CE LOW to data valid – 10 ns tDOE OE LOW to data valid – 6 ns 0 – ns – 5 ns 3 – ns – 5 ns 0 – ns tLZOE OE LOW to Low Z [7] [7, 8] tHZOE OE HIGH to High Z tLZCE CE LOW to Low Z [7] [7, 8] tHZCE CE HIGH to High Z tPU CE LOW to power up tPD CE HIGH to power down – 10 ns tDBE Byte enable to data valid – 6 ns tLZBE Byte enable to Low Z 0 – ns Byte disable to High Z – 6 ns tHZBE Write Cycle [9, 10] tWC Write cycle time 10 – ns tSCE CE LOW to write end 7 – ns tAW Address setup to write end 7 – ns tHA Address hold from write end 0 – ns tSA Address setup to write start 0 – ns tPWE WE pulse width 7 – ns tSD Data setup to write end 5 – ns tHD Data hold from write end 0 – ns tLZWE WE HIGH to Low Z [7] 3 – ns – 5 ns 7 – ns [7, 8] tHZWE WE LOW to High Z tBW Byte enable to end of write Notes 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, and input pulse levels of 0 to 3.0 V. 6. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed. 7. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 8. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of Figure 2 on page 5. Transition is measured 500 mV from steady state voltage. 9. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW, and BHE/BLE LOW. CE, WE, and BHE/BLE must be LOW to initiate a write. The transition of these signals terminate the write. The input data setup and hold timing is referenced to the leading edge of the signal that terminates the write. 10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 001-86495 Rev. *D Page 6 of 15 CY7C1041CV33 Automotive Switching Waveforms Figure 3. Read Cycle No. 1 (Address Transition Controlled) [11, 12] tRC RC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 4. Read Cycle No. 2 (OE Controlled) [12, 13] ADDRESS tRC CE tACE OE tHZOE tDOE tLZOE BHE, BLE tHZCE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZBE DATA VALID HIGH IMPEDANCE tPD tPU 50% 50% ICC ISB Notes 11. Device is continuously selected. OE, CE, BHE, and/or BLE = VIL. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW. Document Number: 001-86495 Rev. *D Page 7 of 15 CY7C1041CV33 Automotive Switching Waveforms (continued) Figure 5. Write Cycle No. 1 (CE Controlled) [14, 15] tWC ADDRESS tSA tSCE CE tAW tHA tPWE WE t BW BHE, BLE tSD tHD DATA IO Figure 6. Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tHA tPWE WE tSCE CE tSD tHD DATA I/O Notes 14. Data I/O is high impedance if OE, BHE, and/or BLE = VIH. 15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document Number: 001-86495 Rev. *D Page 8 of 15 CY7C1041CV33 Automotive Switching Waveforms (continued) Figure 7. Write Cycle No. 3 (WE Controlled, LOW) tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD DATA I/O tLZWE Document Number: 001-86495 Rev. *D Page 9 of 15 CY7C1041CV33 Automotive Truth Table CE OE WE BLE BHE H X X X X High Z I/O0–I/O7 High Z I/O8–I/O15 Power down Mode Standby (ISB) Power L L H L L Data Out Data Out Read – all bits Active (ICC) L L H L H Data Out High Z Read – lower bits only Active (ICC) L L H H L High Z Data Out Read – upper bits only Active (ICC) L X L L L Data In Data In Write – all bits Active (ICC) L X L L H Data In High Z Write – lower bits only Active (ICC) L X L H L High Z Data In Write – upper bits only Active (ICC) L H H X X High Z High Z Selected, outputs disabled Active (ICC) Document Number: 001-86495 Rev. *D Page 10 of 15 CY7C1041CV33 Automotive Ordering Information Speed (ns) 10 Ordering Code CY7C1041CV33-10BAJXE Package Diagram Operating Range Package Type 001-85259 48-ball BGA (Pb-free) Automotive-E Ordering Code Definitions CY 7 C 1 04 1 C V33 - 10 BA J X E Temperature range: E = Automotive-E Pb-free J = JEDEC Package Type: BA = 48-ball BGA Speed grade: 10 ns V33 = 3.3 V Process Technology: C = 150 nm Bus Width: 1 = × 16 bits Density: 04 = 4-Mbit Family Code: 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-86495 Rev. *D Page 11 of 15 CY7C1041CV33 Automotive Package Diagrams Figure 8. 48-ball FBGA (6 × 8 × 1.2 mm) BA48M/BK48M (0.35 mm Ball Diameter) Package Outline, 001-85259 001-85259 *A Document Number: 001-86495 Rev. *D Page 12 of 15 CY7C1041CV33 Automotive Acronyms Acronym Document Conventions Description Units of Measure BHE Byte High Enable BLE Byte Low Enable °C degree Celsius CMOS Complementary Metal Oxide Semiconductor MHz megahertz CE Chip Enable µA microampere I/O Input/Output µs microsecond OE Output Enable mA milliampere SRAM Static Random Access Memory mm millimeter TTL Transistor-Transistor Logic VFBGA Very Fine-Pitch Ball Grid Array WE Write Enable Document Number: 001-86495 Rev. *D Symbol Unit of Measure ms millisecond mV millivolt mW milliwatt ns nanosecond % percent pF picofarad V volt W watt Page 13 of 15 CY7C1041CV33 Automotive Document History Page Document Title: CY7C1041CV33 Automotive, 4-Mbit (256 K × 16) Static RAM Document Number: 001-86495 Revision ECN Orig. of Change Submission Date ** 3925192 TAVA 04/04/2013 New data sheet. *A 4103029 MEMJ 08/23/2013 Changed status from Preliminary to Final. Description of Change Updated Ordering Information: No change in part numbers. Replaced “51-85087” with “001-85259” in “Package Diagram” column. Updated Package Diagrams: spec 001-85259 – Changed revision from ** to *A. Updated in new template. *B 4396000 VINI 06/02/2014 No technical updates. *C 4724503 PSR 04/14/2015 Updated Functional Description: Added “For a complete list of related resources, click here.” at the end. Updated to new template. Completing Sunset Review. *D 6003585 AESATP12 12/22/2017 Updated logo and copyright. Completing Sunset Review. Document Number: 001-86495 Rev. *D Page 14 of 15 CY7C1041CV33 Automotive Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Arm® Cortex® Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers Interface cypress.com/clocks cypress.com/interface Internet of Things Memory cypress.com/iot cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs Cypress Developer Community Community | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/pmic Touch Sensing cypress.com/touch USB Controllers Wireless Connectivity PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU cypress.com/usb cypress.com/wireless © Cypress Semiconductor Corporation, 2013-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document, including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach, such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 001-86495 Rev. *D Revised December 22, 2017 Page 15 of 15
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