CY7C1041CV33-10ZXC

CY7C1041CV33 4-Mbit (256K x 16) Static RAM Features • Pin equivalent to CY7C1041BV33 • Temperature Ranges — Commercial: 0°C to 70°C — Industrial: –40°C to 85°C — Automotive-A: –40°C to 85°C — Automotive-E: –40°C to 125°C • High speed — tAA = 10 ns • Low active power — 324 mW (max.) • 2.0V data retention • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE and OE features • Available in Pb-free and non Pb-free 44-pin 400-milSOJ, 44-pin TSOP II and 48-ball FBGA packages Functional Description[1] The CY7C1041CV33 is a high-performance CMOS Static RAM organized as 262,144 words by 16 bits. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte LOW Enable (BLE) is LOW, then data from I/O pins (I/O0–I/O7), is written into the location specified on the address pins (A0–A17). If Byte HIGH Enable (BHE) is LOW, then data from I/O pins (I/O8–I/O15) is written into the location specified on the address pins (A0–A17). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte LOW Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 – I/O7. If Byte HIGH Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of Read and Write modes. The input/output pins (I/O0–I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a Write operation (CE LOW, and WE LOW). The CY7C1041CV33 is available in a standard 44-pin 400-mil-wide body width SOJ and 44-pin TSOP II package with center power and ground (revolutionary) pinout, as well as a 48-ball fine-pitch ball grid array (FBGA) package. Logic Block Diagram INPUT BUFFER Pin Configuration SOJ/ TSOP II Top View A0 A1 A2 A3 A4 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A0 A1 A2 A3 A4 A5 A6 A7 A8 256K × 16 ARRAY I/O0–I/O7 I/O8–I/O15 COLUMN DECODER BHE WE CE OE BLE A17 A16 A15 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A14 A13 A12 A11 A10 ROW DECODER Notes: 1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com. A9 A10 A 11 A 12 A 13 A14 A15 A16 A17 SENSE AMPS Cypress Semiconductor Corporation Document #: 38-05134 Rev. *H • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 1, 2006 [+] [+] Feedback CY7C1041CV33 Selection Guide -10 Maximum Access Time Maximum Operating Current Commercial Industrial Automotive-A Automotive-E Maximum CMOS Standby Current Commercial/ Industrial Automotive-A Automotive-E 10 10 15 10 10 10 90 100 100 -12 12 85 95 -15 15 80 90 -20 20 75 85 85 90 10 Unit ns mA mA mA mA mA mA mA Pin Configurations 48-ball FBGA (Top View) 1 BLE I/O0 I/O1 VSS VCC I/O6 I/O7 NC 2 OE BHE I/O 2 I/O3 I/O4 I/O5 NC A8 3 A0 A3 A5 A17 NC A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE 6 NC I/O8 A B C D E F G H I/O10 I/O9 I/O 11 I/O12 I/O13 WE A11 VCC VSS I/O14 I/O15 NC Document #: 38-05134 Rev. *H Page 2 of 12 [+] [+] Feedback CY7C1041CV33 Pin Definitions Pin Name A0–A17 44-SOJ, 44-TSOP Pin Number 1–5, 18–27, 42–44 48-ball FBGA Pin Number A3, A4, A5, B3, B4, C3, C4, D4, H2, H3, H4, H5, G3, G4, F3, F4, E4, D3 B1, C1, C2, D2, E2, F2, F1, G1, B6, C6, C5, D5, E5, F5, F6, G6 A6, E3, G2, H1, H6 G5 I/O Type Input Description Address Inputs used to select one of the address locations. I/O0–I/O15 7–10,13–16, 29–32, 35–38 Input/Output Bidirectional Data I/O lines. Used as input or output lines depending on operation NC WE 28 17 No Connect No Connects. This pin is not connected to the die Input/Control Write Enable Input, active LOW. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is conducted. Input/Control Chip Enable Input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Input/Control Byte Write Select Inputs, active LOW. BHE controls I/O15–I/O8, BLE controls I/O7–I/O0 Input/Control Output Enable, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. Ground Ground for the device. Should be connected to ground of the system. CE BHE, BLE OE 6 40, 39 41 B5 B2, A1 A2 VSS VCC 12, 34 11, 33 D1, E6 D6, E1 Power Supply Power Supply inputs to the device. Document #: 38-05134 Rev. *H Page 3 of 12 [+] [+] Feedback CY7C1041CV33 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VCC to Relative GND[2] .... –0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[2] ....................................–0.5V to VCC + 0.5V DC Input Voltage[2] .................................–0.5V to VCC + 0.5V Current into Outputs (LOW) .........................................20 mA Static Discharge Voltage............. ...............................>2001V (per MIL-STD-883, Method 3015) Latch-up Current...................................................... >200 mA Operating Range Range Commercial Industrial Automotive-A Automotive-E Ambient Temperature 0°C to +70°C –40°C to +85°C –40°C to +85°C –40°C to +125°C VCC 3.3V ± 0.3V DC Electrical Characteristics Over the Operating Range -10 Parameter VOH VOL VIH VIL[2] IIX Description Test Conditions Min. Max. 2.4 0.4 2.0 –0.3 GND < VI < VCC Com’l/Ind’l Auto-A Auto-E IOZ Output Leakage Current GND < VOUT < VCC, Com’l/Ind’l Output Disabled Auto-A Auto-E ICC VCC Operating Supply Current VCC = Max., f = fMAX = 1/tRC Com’l Ind’l Auto-A Auto-E ISB1 Max. VCC, Automatic CE Com’l/Ind’l Power-down Current CE > VIH Auto-A —TTL Inputs VIN > VIH or VIN < VIL, f = fMAX Auto-E Max. VCC, Automatic CE Com’l/Ind’l Power-down Current CE > VCC – 0.3V, Auto-A —CMOS Inputs VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 Auto-E 40 40 10 10 10 10 40 40 90 100 100 85 95 80 90 –1 –1 +1 +1 –1 +1 –1 +1 –1 –1 VCC + 0.3 0.8 +1 +1 2.0 –0.3 –1 Output HIGH Voltage VCC = Min., IOH = –4.0 mA Output LOW Voltage VCC = Min., IOL = 8.0 mA Input HIGH Voltage Input LOW Voltage Input Leakage Current 2.4 0.4 VCC + 0.3 0.8 +1 2.0 –0.3 –1 -12 Min. Max. 2.4 0.4 VCC + 0.3 0.8 +1 2.0 –0.3 –1 –1 –20 –1 –1 –20 -15 Min. Max. 2.4 0.4 VCC + 0.3 0.8 +1 +1 +20 +1 +1 +20 75 85 85 90 40 40 45 10 10 15 -20 Min. Max. Unit V V V V µA µA µA µA µA µA mA mA mA mA mA mA mA mA mA mA ISB2 Capacitance[3] Parameter CIN COUT Description Input Capacitance I/O Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max. 8 8 Unit pF pF Notes: 2. VIL (min.) = –2.0V and VIH(max) = VCC + 0.5V for pulse durations of less than 20 ns. 3. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05134 Rev. *H Page 4 of 12 [+] [+] Feedback CY7C1041CV33 Thermal Resistance[3] Parameter Description Test Conditions TSOP-II 42.96 10.75 FBGA 38.15 9.15 SOJ 25.99 18.8 Unit °C/W °C/W ΘJA ΘJC Thermal Resistance (Junction to Ambient) Test conditions follow standard Thermal Resistance (Junction to Case) test methods and procedures for measuring thermal impedance, per EIA / JESD51. AC Test Loads and Waveforms[4] 10-ns Devices OUTPUT 50 Ω * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 1.5V Z = 50Ω 12-, 15-, 20-ns Devices 3.3V R 317 Ω 30 pF* OUTPUT 30 pF R2 351Ω High-Z Characteristics R 317 Ω (a) ALL INPUT PULSES (b) 3.3V OUTPUT 5 pF R2 351Ω 3.0V 90% GND 10% 90% 10% Rise Time: 1 V/ns (c) Fall Time: 1 V/ns (d) AC Switching Characteristics[5] Over the Operating Range -10 Parameter Read Cycle tpower[6] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE VCC(typical) to the first access Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z OE HIGH to High-Z[7, 8] 3 5 0 10 5 0 6 0 6 0 12 6 0 7 CE LOW to Low-Z[8] CE HIGH to High-Z[7, 8] CE LOW to Power-Up CE HIGH to Power-Down Byte Enable to Data Valid Byte Enable to Low-Z Byte Disable to High-Z 0 5 3 6 0 15 7 0 8 3 10 5 0 6 3 7 0 20 8 100 10 10 3 12 6 0 7 3 8 100 12 12 3 15 7 0 8 100 15 15 3 20 8 100 20 20 µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Min. -12 Max. Min. -15 Max. Min. -20 Max. Unit Notes: 4. AC characteristics (except High-Z) for 10-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thevenin load shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d). 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. 6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 9. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. Document #: 38-05134 Rev. *H Page 5 of 12 [+] [+] Feedback CY7C1041CV33 AC Switching Characteristics[5] Over the Operating Range (continued) -10 Parameter Write Cycle[9, 10] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low-Z[7] WE LOW to High-Z[7, 8] Byte Enable to End of Write 7 10 7 7 0 0 7 5 0 3 5 8 12 8 8 0 0 8 6 0 3 6 10 15 10 10 0 0 10 7 0 3 7 10 20 10 10 0 0 10 8 0 3 8 ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Min. -12 Max. Min. -15 Max. Min. -20 Max. Unit Switching Waveforms Read Cycle No. 1[11, 12] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[12, 13] ADDRESS tRC CE tACE OE BHE, BLE tDOE tLZOE tDBE tLZBE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZCE tHZBE DATA VALID tPD 50% IISB SB IICC CC tHZOE HIGH IMPEDANCE DATA OUT Notes: 10. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 11. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. 12. WE is HIGH for Read cycle. 13. Address valid prior to or coincident with CE transition LOW. Document #: 38-05134 Rev. *H Page 6 of 12 [+] [+] Feedback CY7C1041CV33 Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[14, 15] tWC ADDRESS CE tSA tSCE tAW tPWE WE tBW BHE, BLE tSD DATA I/O tHD tHA Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tPWE WE tSCE CE tSD DATA I/O tHD tHA Notes: 14. Data I/O is high-impedance if OE or BHE and/or BLE = VIH. 15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05134 Rev. *H Page 7 of 12 [+] [+] Feedback CY7C1041CV33 Switching Waveforms (continued) Write Cycle No. 2 (WE Controlled, OE LOW) tWC ADDRESS CE tSCE tAW tSA tPWE tHA WE tBW BHE, BLE tHZWE DATA I/O tLZWE tSD tHD Truth Table CE H L L L L L L L OE X L L L X X X H WE X H H H L L L H BLE X L L H L L H X BHE X L H L L H L X I/O0–I/O7 High-Z Data Out Data Out High-Z Data In Data In High-Z High-Z I/O8–I/O15 High-Z Data Out High-Z Data Out Data In High-Z Data In High-Z Power-down Read All Bits Read Lower Bits Only Read Upper Bits Only Write All Bits Write Lower Bits Only Write Upper Bits Only Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Document #: 38-05134 Rev. *H Page 8 of 12 [+] [+] Feedback CY7C1041CV33 Ordering Information Speed (ns) 10 Ordering Code CY7C1041CV33-10BAC CY7C1041CV33-10BAXC CY7C1041CV33-10VC CY7C1041CV33-10VXC CY7C1041CV33-10ZC CY7C1041CV33-10ZXC CY7C1041CV33-10BAI CY7C1041CV33-10BAXI CY7C1041CV33-10ZI CY7C1041CV33-10ZXI CY7C1041CV33-10ZSXA CY7C1041CV33-10BAXA 12 CY7C1041CV33-12VC CY7C1041CV33-12VXC CY7C1041CV33-12ZC CY7C1041CV33-12ZXC CY7C1041CV33-12VXI CY7C1041CV33-12ZI CY7C1041CV33-12ZXI 15 CY7C1041CV33-15VC CY7C1041CV33-15VXC CY7C1041CV33-15ZC CY7C1041CV33-15ZXC CY7C1041CV33-15VI CY7C1041CV33-15VXI CY7C1041CV33-15ZI CY7C1041CV33-15ZXI 20 CY7C1041CV33-20ZC CY7C1041CV33-20ZXC CY7C1041CV33-20ZSXA CY7C1041CV33-20VE CY7C1041CV33-20VXE CY7C1041CV33-20ZE CY7C1041CV33-20ZSXE 51-85087 51-85082 51-85087 51-85087 51-85082 51-85087 51-85082 51-85082 51-85087 51-85087 51-85106 51-85082 51-85087 51-85106 51-85087 51-85082 Package Diagram 51-85106 Package Type 48-ball Fine Pitch BGA 48-ball Fine Pitch BGA (Pb-Free) 44-lead (400-mil) Molded SOJ 44-lead (400-mil) Molded SOJ (Pb-Free) 44-pin TSOP II 44-pin TSOP II (Pb-Free) 48-ball Fine Pitch BGA 48-ball Fine Pitch BGA (Pb-Free) 44-pin TSOP II 44-pin TSOP II (Pb-Free) 44-pin TSOP II (Pb-Free) 48-ball Fine Pitch BGA (Pb-Free) 44-lead (400-mil) Molded SOJ 44-lead (400-mil) Molded SOJ (Pb-Free) 44-pin TSOP II 44-pin TSOP II (Pb-Free) 44-lead (400-mil) Molded SOJ (Pb-Free) 44-pin TSOP II 44-pin TSOP II (Pb-Free) 44-lead (400-mil) Molded SOJ 44-lead (400-mil) Molded SOJ (Pb-Free) 44-pin TSOP II 44-pin TSOP II (Pb-Free) 44-lead (400-mil) Molded SOJ 44-lead (400-mil) Molded SOJ (Pb-Free) 44-pin TSOP II 44-pin TSOP II (Pb-Free) 44-pin TSOP II 44-pin TSOP II (Pb-Free) 44-pin TSOP II (Pb-Free) 44-lead (400-mil) Molded SOJ 44-lead (400-mil) Molded SOJ (Pb-Free) 44-pin TSOP II 44-pin TSOP II (Pb-Free) Automotive-A Automotive-E Commercial Industrial Commercial Industrial Commercial Automotive-A Industrial Operating Range Commercial Please contact your local Cypress sales representative for availability of these parts Document #: 38-05134 Rev. *H Page 9 of 12 [+] [+] Feedback CY7C1041CV33 Package Diagrams 48-Ball (7.00 mm x 8.5 mm x 1.2 mm) FBGA (51-85106) TOP VIEW BOTTOM VIEW A1 CORNER Ø0.05 M C A1 CORNER Ø0.25 M C A B Ø0.30±0.05(48X) 1 2 3 4 5 6 6 5 4 3 2 1 A B C 0.75 8.50±0.10 8.50±0.10 5.25 D E F G H A B C D E 2.625 F G H A B 7.00±0.10 A 1.875 0.75 3.75 B 7.00±0.10 0.53±0.05 0.25 C 0.21±0.05 0.15(4X) 0.15 C 51-85106-*E SEATING PLANE 0.36 C 1.20 MAX. Document #: 38-05134 Rev. *H Page 10 of 12 [+] [+] Feedback CY7C1041CV33 Package Diagrams (continued) 44-lead (400-mil) Molded SOJ (51-85082) 51-85082-*B 44-pin TSOP II (51-85087) 51-85087-*A All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05134 Rev. *H Page 11 of 12 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] [+] Feedback CY7C1041CV33 Document History Page Document Title: CY7C1041CV33 4-Mbit (256K x 16) Static RAM Document Number: 38-05134 REV. ** *A *B *C *D *E *F *G ECN NO. 109513 112440 112859 116477 119797 262949 361795 435387 Issue Date 12/13/01 12/20/01 03/25/02 09/16/02 10/21/02 See ECN See ECN See ECN Orig. of Change HGK BSS DFP CEA DFP RKF SYT NXR New Data Sheet Updated 51-85106 from revision *A to *C Added CY7C1042CV33 in BGA package Removed 1042 BGA option pin ACC Final Data Sheet Add applications foot note to data sheet Added 20-ns speed bin 1) Added Lead (Pb)-Free parts in the Ordering info (Page #9) 2) Added Automotive Specs to Datasheet Added Pb-Free offerings in the Ordering Information Removed -8 Speed bin from Product offering. Corrected typo in description for BHE/BLE in pin definitions table on Page# 3 corrected ther Pin name from OE2 to OE. Included the Maximum Ratings for Static Discharge Voltage and Latch up Current. Changed the description of IIX current from Input Load Current to Input Leakage Current Added note# 4 on page# 4 Updated the Ordering Information table Added Automotive-A Operating Range Changed tpower value from 1 µs to 100 µs Updated Ordering Information table Description of Change *H 499153 See ECN NXR Document #: 38-05134 Rev. *H Page 12 of 12 [+] [+] Feedback