CY7C1041CV33-15ZXCT

CY7C1041CV33 4-Mbit (256K x 16) Static RAM Features Functional Description ■ The CY7C1041CV33 is a high performance CMOS static RAM organized as 262,144 words by 16 bits. Temperature ranges ❐ Commercial: 0°C to 70°C ❐ Industrial: –40°C to 85°C ❐ Automotive-A: –40°C to 85°C ❐ Automotive-E: –40°C to 125°C ■ Pin and function compatible with CY7C1041BV33 ■ High speed ❐ tAA = 10 ns (Commercial, Industrial and Automotive-A) ❐ tAA = 12 ns (Automotive-E) To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A17). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from memory appears on IO8 to IO15. For more information, see the Truth Table on page 9 for a complete description of Read and Write modes. ■ Low active power ❐ 324 mW (max) ■ 2.0V data retention ■ Automatic power down when deselected ■ TTL-compatible inputs and outputs ■ Easy memory expansion with CE and OE features ■ Available in Pb-free and non Pb-free 44-pin 400 Mil SOJ, 44-pin TSOP II and 48-Ball FBGA packages The input and output pins (IO0 through IO15) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines. Logic Block Diagram SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 ROW DECODER INPUT BUFFER 256K x 16 RAM Array IO0–IO7 IO8–IO15 • BHE WE CE OE BLE A16 A17 A15 A14 A12 A13 A9 Cypress Semiconductor Corporation Document Number: 38-05134 Rev. *I A10 A11 COLUMN DECODER 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised February 14, 2008 [+] Feedback CY7C1041CV33 Selection Guide Description Maximum Access Time Maximum Operating Current -10 -12 -15 -20 10 12 15 20 ns Commercial 90 85 80 75 mA Industrial 100 95 90 85 mA Automotive-A 100 85 mA 90 mA 10 mA 10 mA 15 mA Automotive-E Maximum CMOS Standby Current Unit 120 Commercial/ Industrial 10 Automotive-A 10 Automotive-E 10 10 15 Pin Configuration Figure 1. 44-Pin SOJ/TSOP II (Top View) [1] A0 A1 A2 A3 A4 CE IO0 IO1 IO2 IO3 VCC VSS IO4 IO5 IO6 IO7 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE BHE BLE IO15 IO14 IO13 IO12 VSS VCC IO11 IO10 IO9 IO8 NC A14 A13 A12 A11 A10 Figure 2. 48-Ball FBGA Pinout (Top View) [1] 1 2 3 4 5 6 BLE OE A0 A1 A2 NC A IO0 BHE A3 A4 CE IO8 B IO1 IO2 A5 A6 IO10 IO9 C VSS IO3 A17 A7 IO11 VCC D VCC IO4 NC A16 IO12 VSS E IO6 IO5 A14 A15 IO13 IO14 F IO7 NC A12 A13 WE IO15 G NC A8 A9 A10 A11 NC H Note 1. NC pins are not connected on the die. Document Number: 38-05134 Rev. *I Page 2 of 14 [+] Feedback CY7C1041CV33 Pin Definitions Pin Name SOJ, TSOP Pin Number BGA Pin Number IO Type A0–A17 1–5, 18–27, 42–44 A3, A4, A5, B3, B4, C3, C4, D4, H2, H3, H4, H5, G3, G4, F3, F4, E4, D3 Input IO0–IO15 Description Address Inputs. Used to select one of the address locations. 7–10,13–16, B1, C1, C2, D2, Input or Output Bidirectional Data IO lines. Used as input or output lines depending 29–32, 35–38 E2, F2, F1, G1, on operation. B6, C6, C5, D5, E5, F5, F6, G6 NC 28 A6, E3, G2, H1, H6 No Connect WE 17 G5 Input or Control Write Enable Input, Active LOW. When selected LOW, a write is conducted. When deselected HIGH, a read is conducted. CE 6 B5 Input or Control Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. BHE, BLE 40, 39 B2, A1 Input or Control Byte Write Select Inputs, Active LOW. BHE controls IO16 – IO9, BLE controls IO8 – IO1. OE 41 A2 Input or Control Output Enable, Active LOW. Controls the direction of the IO pins. When LOW, the IO pins are allowed to behave as outputs. When deasserted HIGH, the IO pins are tri-stated and act as input data pins. VSS 12, 34 D1, E6 Ground Ground for the Device. Connected to ground of the system. VCC 11, 33 D6, E1 Document Number: 38-05134 Rev. *I No Connects. Not connected to the die. Power Supply Power Supply Inputs to the Device. Page 3 of 14 [+] Feedback CY7C1041CV33 Maximum Ratings Static Discharge Voltage............................................ >2001V (MIL-STD-883, Method 3015) Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Latch Up Current ..................................................... >200 mA Storage Temperature ................................. –65°C to +150°C Operating Range Ambient Temperature with Power Applied ............................................ –55°C to +125°C Range Ambient Temperature (TA) VCC 0°C to +70°C 3.3V ± 10% Supply Voltage on VCC Relative to GND[2] .....–0.5V to +4.6V Commercial DC Voltage Applied to Outputs in High Z State[2] ...................................... –0.5V to VCC+0.5V Industrial Automotive-A –40°C to +85°C DC Input Voltage[2] .................................. –0.5V to VCC+0.5V Automotive -E –40°C to +125°C –40°C to +85°C Current into Outputs (LOW)......................................... 20 mA Electrical Characteristics Over the Operating Range Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min, IOH = –4.0 mA VOL Output LOW Voltage VCC = Min, IOL = 8.0 mA VIH Input HIGH Voltage VIL [2] Input LOW Voltage IIX Input Leakage Current GND < VI < VCC -10 Min -12 Max 2.4 Output Leakage Current 0.4 VCC Operating Supply Current ISB2 Automatic CE Power Max VCC, Down Current —TTL CE > VIH VIN > VIH or Inputs VIN < VIL, f = fMAX 2.4 0.4 Min Max 2.4 0.4 Unit V 0.4 V VCC + 0.3 2.0 VCC + 0.3 2.0 VCC + 0.3 2.0 VCC + 0.3 V –0.3 0.8 –0.3 0.8 –0.3 0.8 –0.3 0.8 V –1 +1 –1 +1 –1 +1 –1 +1 μA Auto-A –1 +1 –20 +20 –1 +1 –20 +20 –1 +1 –1 +1 –1 +1 –1 +1 –20 +20 –1 +1 –1 +1 –20 +20 Com’l 90 85 80 75 Ind’l 100 95 90 85 Auto-A 100 Auto-E ISB1 Max Com’l/Ind’l GND < VOUT < VCC, Com’l/Ind’l Output disabled Auto-A VCC = Max, f = fMAX = 1/tRC Min -20 2.0 Auto-E ICC Max 2.4 Auto-E IOZ Min -15 40 Auto-A 40 Auto-E Automatic CE Power Max VCC, Com’l/Ind’l Down Current — CE > VCC – 0.3V, Auto-A CMOS Inputs VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 Auto-E 40 90 40 40 mA 40 45 10 mA 85 120 Com’l/Ind’l μA 10 10 45 10 10 mA 10 15 15 Note 2. VIL (min) = –2.0V and VIH(max) = VCC + 0.5V for pulse durations of less than 20 ns. Document Number: 38-05134 Rev. *I Page 4 of 14 [+] Feedback CY7C1041CV33 Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max Unit 8 pF 8 pF Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions SOJ TSOP II FBGA Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 25.99 42.96 38.15 °C/W 18.8 10.75 9.15 °C/W AC Test Loads and Waveforms Figure 3. AC Test Loads and Waveforms [3] 12-, 15-, 20-ns devices: 10-ns devices: Z = 50Ω 50 Ω * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT R 317Ω 3.3V OUTPUT 30 pF* OUTPUT R2 351Ω 30 pF* 1.5V (b) (a) High-Z characteristics: 90% GND R 317Ω ALL INPUT PULSES 3.0V 90% 10% Rise Time: 1 V/ns 3.3V 10% (c) Fall Time: 1 V/ns OUTPUT R2 351Ω 5 pF (d) Note 3. AC characteristics (except High-Z) for 10-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thevenin load shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d). Document Number: 38-05134 Rev. *I Page 5 of 14 [+] Feedback CY7C1041CV33 Switching Characteristics Over the Operating Range [4] Parameter -10 Description Min -12 Max Min -15 Max Min -20 Max Min Max Unit Read Cycle tpower[5] VCC(Typical) to the First Access 100 100 100 100 μs tRC Read Cycle Time 10 12 15 20 ns tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid tDOE OE LOW to Data Valid 10 3 Comm’l/Ind’l/Auto-A 12 3 tLZOE OE LOW to Low Z tHZOE OE HIGH to High Z[6, 7] 20 ns 5 6 7 8 ns 7 tHZCE CE HIGH to High Z tPU CE LOW to Power Up tPD CE HIGH to Power Down tDBE Byte Enable to Data Valid 0 3 [6, 7] Byte Enable to Low Z tHZBE Byte Disable to High Z 0 7 3 6 0 ns 8 3 7 0 ns ns 8 0 ns ns 10 12 15 20 ns 5 6 7 8 ns Auto-E tLZBE 0 3 0 8 6 5 Comm’l/Ind’l/Auto-A ns 15 5 CE LOW to Low Z tLZCE 3 ns 12 0 [6] 3 20 10 Auto-E [6] 15 7 0 0 6 8 0 6 0 7 ns 8 ns [8, 9] Write Cycle tWC Write Cycle Time 10 12 15 20 ns tSCE CE LOW to Write End 7 8 10 10 ns tAW Address Setup to Write End 7 8 10 10 ns tHA Address Hold from Write End 0 0 0 0 ns tSA Address Setup to Write Start 0 0 0 0 ns tPWE WE Pulse Width 7 8 10 10 ns tSD Data Setup to Write End 5 6 7 8 ns tHD Data Hold from Write End 0 0 0 0 ns 3 3 3 3 ns WE HIGH to Low Z[6] tHZWE WE LOW to High Z[6, 7] tBW Byte Enable to End of Write tLZWE 5 7 6 8 7 10 8 10 ns ns Notes 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V. 5. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed. 6. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 7. tHZOE, tHZCE, tHZBE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads and Waveforms on page 5. Transition is measured ±500 mV from steady state voltage. 8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW, and BHE/BLE LOW. CE, WE, and BHE/BLE must be LOW to initiate a write. The transition of these signals terminate the write. The input data setup and hold timing is referenced to the leading edge of the signal that terminates the write. 9. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 38-05134 Rev. *I Page 6 of 14 [+] Feedback CY7C1041CV33 Switching Waveforms Figure 4. Read Cycle No. 1 (Address Transition Controlled)[10, 11] tRC RC ADDRESS tAA tOHA DATA OUT DATA VALID PREVIOUS DATA VALID Figure 5. Read Cycle No. 2 (OE Controlled)[11, 12] ADDRESS tRC CE tACE OE tHZOE tDOE tLZOE BHE, BLE tHZCE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZBE HIGH IMPEDANCE DATA VALID tPD tPU 50% ICC 50% ISB Notes 10. Device is continuously selected. OE, CE, BHE, and/or BLE = VIL. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE transition LOW. Document Number: 38-05134 Rev. *I Page 7 of 14 [+] Feedback CY7C1041CV33 Switching Waveforms (continued) Figure 6. Write Cycle No. 1 (CE Controlled)[13, 14] tWC ADDRESS tSA tSCE CE tAW tHA tPWE WE tBW BHE, BLE tSD tHD DATA IO Figure 7. Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS tSA tBW BHE, BLE tAW tHA tPWE WE tSCE CE tSD tHD DATA IO Notes 13. Data IO is high impedance if OE, BHE, and/or BLE = VIH. 14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document Number: 38-05134 Rev. *I Page 8 of 14 [+] Feedback CY7C1041CV33 Switching Waveforms (continued) Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD DATA IO tLZWE Truth Table CE OE WE BLE BHE H X X X X High Z High Z Power Down Standby (ISB) L L H L L Data Out Data Out Read – All Bits Active (ICC) L H Data Out High Z Read – Lower Bits Only Active (ICC) L X L IO0 – IO7 IO8 – IO15 Mode Power H L High Z Data Out Read – Upper Bits Only Active (ICC) L L Data In Data In Write – All Bits Active (ICC) L H Data In High Z Write – Lower Bits Only Active (ICC) H L High Z Data In Write – Upper Bits Only Active (ICC) L H H X X High Z High Z Selected, Outputs Disabled Active (ICC) L X X H H High Z High Z Selected, Outputs Disabled Active (ICC) Document Number: 38-05134 Rev. *I Page 9 of 14 [+] Feedback CY7C1041CV33 Ordering Information Speed (ns) 10 Ordering Code 51-85106 48-ball Fine Pitch BGA (Pb-Free) CY7C1041CV33-10VC 51-85082 44-pin (400-mil) Molded SOJ 51-85087 44-pin TSOP II (Pb-Free) CY7C1041CV33-10BAI 51-85106 48-ball Fine Pitch BGA CY7C1041CV33-10ZI CY7C1041CV33-10ZXI CY7C1041CV33-10BAXA 51-85087 44-pin TSOP II (Pb-Free) CY7C1041CV33-12ZXC 51-85087 44-pin TSOP II (Pb-Free) CY7C1041CV33-12ZI 51-85087 44-pin TSOP II Automotive-A Commercial Industrial 44-pin TSOP II (Pb-Free) CY7C1041CV33-12BAXE 51-85106 48-ball Fine Pitch BGA (Pb-Free) CY7C1041CV33-12ZSXE 51-85087 44-pin TSOP II (Pb-Free) CY7C1041CV33-15ZXC 51-85087 44-pin TSOP II (Pb-Free) CY7C1041CV33-15VI 51-85082 44-pin (400-mil) Molded SOJ CY7C1041CV33-15ZXI 20 44-pin TSOP II (Pb-Free) 51-85106 48-ball Fine Pitch BGA (Pb-Free) 51-85082 44-pin (400-mil) Molded SOJ (Pb-Free) CY7C1041CV33-15ZI Industrial 48-ball Fine Pitch BGA (Pb-Free) CY7C1041CV33-12VXC CY7C1041CV33-15VXI Commercial 51-85087 44-pin TSOP II CY7C1041CV33-10ZSXA CY7C1041CV33-12ZXI Operating Range 44-pin (400-mil) Molded SOJ (Pb-Free) CY7C1041CV33-10ZXC CY7C1041CV33-10BAXI 15 Package Type CY7C1041CV33-10BAXC CY7C1041CV33-10VXC 12 Package Diagram Automotive-E Commercial Industrial 44-pin (400-mil) Molded SOJ (Pb-Free) 51-85087 44-pin TSOP II 44-pin TSOP II (Pb-Free) CY7C1041CV33-20ZC 51-85087 44-pin TSOP II CY7C1041CV33-20ZSXA 51-85087 44-pin TSOP II (Pb-Free) Automotive-A CY7C1041CV33-20VE 51-85082 44-pin (400-mil) Molded SOJ Automotive-E CY7C1041CV33-20VXE CY7C1041CV33-20ZE CY7C1041CV33-20ZSXE Commercial 44-pin (400-mil) Molded SOJ (Pb-Free) 51-85087 44-pin TSOP II 44-pin TSOP II (Pb-Free) Please contact your local Cypress sales representative for availability of these parts Document Number: 38-05134 Rev. *I Page 10 of 14 [+] Feedback CY7C1041CV33 Package Diagrams Figure 9. 44-Pin (400 Mil) Molded SOJ, 51-85082 51-85082-*B Document Number: 38-05134 Rev. *I Page 11 of 14 [+] Feedback CY7C1041CV33 Package Diagrams (continued) Figure 10. 44-Pin Thin Small Outline Package Type II, 51-85087 51-85087-*A Document Number: 38-05134 Rev. *I Page 12 of 14 [+] Feedback CY7C1041CV33 Package Diagrams (continued) Figure 11. 48-Ball FBGA (7 x 8.5 x 1.2 mm), 51-85106 BOTTOM VIEW TOP VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 1 2 3 4 5 6 6 4 3 2 1 C C F G D E 2.625 8.50±0.10 E 0.75 A B 5.25 A B D 8.50±0.10 5 F G H H 1.875 A A B 0.75 7.00±0.10 3.75 7.00±0.10 0.15 C 0.21±0.05 0.25 C 0.53±0.05 B 0.15(4X) Document Number: 38-05134 Rev. *I 1.20 MAX. 0.36 SEATING PLANE C 51-85106-*E Page 13 of 14 [+] Feedback CY7C1041CV33 Document History Page Document Title: CY7C1041CV33, 4-Mbit (256K x 16) Static RAM Document Number: 38-05134 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 109513 12/13/01 HGK New Data Sheet *A 112440 12/20/01 BSS Updated 51-85106 from revision *A to *C *B 112859 03/25/02 DFP Added CY7C1042CV33 in BGA package Removed 1042 BGA option pin ACC Final Data Sheet *C 116477 09/16/02 CEA Add applications foot note to data sheet *D 119797 10/21/02 DFP Added 20-ns speed bin *E 262949 See ECN RKF 1) Added Lead (Pb)-Free parts in the Ordering info (Page #9) 2) Added Automotive Specs to Datasheet *F 361795 See ECN SYT Added Pb-Free offerings in the Ordering Information *G 435387 See ECN NXR Removed -8 Speed bin from Product offering. Corrected typo in description for BHE/BLE in pin definitions table on Page# 3 corrected their Pin name from OE2 to OE. Included the Maximum Ratings for Static Discharge Voltage and Latch up Current. Changed the description of IIX current from Input Load Current to Input Leakage Current Added note# 4 on page# 4 Updated the Ordering Information table *H 499153 See ECN NXR Added Automotive-A Operating Range Changed tpower value from 1 μs to 100 μs Updated Ordering Information table *I 2104110 See ECN VKN/AESA Added Automotive-E specs for 12 ns speed Updated Ordering Information table © Cypress Semiconductor Corporation, 2001-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05134 Rev. *I Revised February 14, 2008 Page 14 of 14 All product and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback