CY7C1041CV33_10

CY7C1041CV33 4-Mbit (256 K × 16) Static RAM 4-Mbit (256 K × 16) Static RAM Features ■ Functional Description The CY7C1041CV33 is a high performance CMOS static RAM organized as 262,144 words by 16 bits. To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (/IO0 through I/O7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from IO pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. For more information, see the Truth Table on page 10 for a complete description of Read and Write modes. The input and output pins (I/O0 through I/O15) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines. Temperature ranges ❐ Commercial: 0 °C to 70°C Pin and function compatible with CY7C1041BV33 High speed ❐ tAA = 8 ns Low active power ❐ 360 mW (max) 2.0 V data retention Automatic power down when deselected TTL-compatible inputs and outputs Easy memory expansion with CE and OE features Available in Pb-free 44-pin TSOP II package ■ ■ ■ ■ ■ ■ ■ ■ Logic Block Diagram INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 ROW DECODER 256K x 16 RAM Array SENSE AMPS I/O0–I/O7 I/O8–I/O15 COLUMN DECODER BHE WE CE OE BLE A10 A11 A12 A14 A13 A16 A17 A15 A9 Cypress Semiconductor Corporation Document Number: 38-05134 Rev. *L • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 4, 2011 [+] Feedback CY7C1041CV33 Contents Selection Guide ................................................................ 3 Pin Configuration ............................................................. 3 Pin Definitions .................................................................. 4 Maximum Ratings ............................................................. 5 Operating Range ............................................................... 5 Electrical Characteristics ................................................. 5 Capacitance ...................................................................... 6 Thermal Resistance .......................................................... 6 AC Test Loads and Waveforms ....................................... 6 Switching Characteristics ................................................ 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 10 Ordering Information ...................................................... 11 Ordering Code Definitions ......................................... 11 Package Diagram ............................................................ 12 Acronyms ....................................................................... 13 Document Conventions ................................................. 13 Units of Measure ....................................................... 13 Document History Page ................................................. 14 Sales, Solutions, and Legal Information ...................... 15 Worldwide Sales and Design Support ....................... 15 Products .................................................................... 15 PSoC Solutions ......................................................... 15 Document Number: 38-05134 Rev. *L Page 2 of 15 [+] Feedback CY7C1041CV33 Selection Guide Description Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current -8 8 100 10 Unit ns mA mA Pin Configuration Figure 1. 44-pin TSOP II (Top View) [1] A0 A1 A2 A3 A4 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 IO5 IO6 IO7 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 IO10 IO9 IO8 NC A14 A13 A12 A11 A10 Note 1. NC pins are not connected on the die. Document Number: 38-05134 Rev. *L Page 3 of 15 [+] Feedback CY7C1041CV33 Pin Definitions Pin Name A0–A17 TSOP Pin Number 1–5, 18–27, 42–44 I/O Type Input Description Address Inputs. Used to select one of the address locations. I/O0–I/O15 7–10,13–16, Input or Output Bidirectional Data IO lines. Used as input or output lines depending on operation. 29–32, 35–38 NC WE CE BHE, BLE OE 28 17 6 40, 39 41 No Connect Input or Control Input or Control Input or Control Input or Control Ground No Connects. Not connected to the die. Write Enable Input, Active LOW. When selected LOW, a write is conducted. When deselected HIGH, a read is conducted. Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Byte Write Select Inputs, Active LOW. BHE controls I/O15 – I/O8, BLE controls I/O7 – I/O0. Output Enable, Active LOW. Controls the direction of the I/O pins. When LOW, the IO pins are allowed to behave as outputs. When deasserted HIGH, the I/O pins are tri-stated and act as input data pins. Ground for the Device. Connected to ground of the system. VSS VCC 12, 34 11, 33 Power Supply Power Supply Inputs to the Device. Document Number: 38-05134 Rev. *L Page 4 of 15 [+] Feedback CY7C1041CV33 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ............................... –65 C to +150 C Ambient Temperature with Power Applied .......................................... –55 C to +125 C Supply Voltage on VCC Relative to GND[2] ...–0.5 V to +4.6 V DC Voltage Applied to Outputs in High Z State[2] .................................. –0.5 V to VCC + 0.5 V DC Input Voltage[2] ............................... –0.5 V to VCC + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage.......................................... > 2001 V (MIL-STD-883, Method 3015) Latch Up Current .................................................... > 200 mA Operating Range Range Commercial Ambient Temperature (TA) 0 C to +70 C VCC 3.3 V  10% Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL [2] IIX IOZ ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power Down Current —TTL Inputs Automatic CE Power Down Current — CMOS Inputs GND < VI < VCC GND < VOUT < VCC, Output disabled VCC = Max, f = fMAX = 1/tRC Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX Max VCC, CE > VCC – 0.3 V, VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0 Test Conditions VCC = Min, IOH = –4.0 mA VCC = Min, IOL = 8.0 mA -8 Min 2.4 – 2.0 –0.3 –1 –1 – – – Max – 0.4 VCC + 0.3 0.8 +1 +1 100 40 10 Unit V V V V A A mA mA mA Note 2. VIL (min) = –2.0 V and VIH(max) = VCC + 0.5 V for pulse durations of less than 20 ns. Document Number: 38-05134 Rev. *L Page 5 of 15 [+] Feedback CY7C1041CV33 Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 3.3 V Max 8 8 Unit pF pF Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 TSOP II 42.96 10.75 Unit C/W C/W JA JC AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms [3] 10-ns devices: OUTPUT 50  * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 1.5 V 12-, 15-, 20-ns devices: 3.3V OUTPUT R 317  Z = 50  30 pF* 30 pF* R2 351 (a) (b) High Z characteristics: 3.0 V GND Rise Time: 1 V/ns ALL INPUT PULSES 90% 10% 90% 10% 3.3 V OUTPUT 5 pF R 317  R2 351 (c) Fall Time: 1 V/ns (d) Note 3. AC characteristics (except High Z) for 10-ns parts are tested using the load conditions shown in Figure 2 (a). All other speeds are tested using the Thevenin load shown in Figure 2 (b). High Z characteristics are tested for all speeds using the test load shown in Figure 2 (d). Document Number: 38-05134 Rev. *L Page 6 of 15 [+] Feedback CY7C1041CV33 Switching Characteristics Over the Operating Range [4] Parameter Read Cycle tpower[5] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle[8, 9] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW Write Cycle Time CE LOW to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width Data Setup to Write End Data Hold from Write End WE HIGH to Low Z[6] WE LOW to High Z[6, 7] Byte Enable to End of Write 8 6 6 0 0 6 4 0 3 – 6 – – – – – – – – – 4 – ns ns ns ns ns ns ns ns ns ns ns VCC(Typical) to the First Access Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low CE LOW to Low Z[6] Z[6] Z[6, 7] OE HIGH to High Z[6, 7] CE HIGH to High 100 8 – 3 – – 0 – 3 – 0 – – 0 – – – 8 – 8 5 – 4 – 4 – 8 5 – 5 s ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description -8 Min Max Unit CE LOW to Power Up CE HIGH to Power Down Byte Enable to Data Valid Byte Enable to Low Z Byte Disable to High Z Notes 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, and input pulse levels of 0 to 3.0 V. 5. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed. 6. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 7. tHZOE, tHZCE, tHZBE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of Figure 2 on page 6. Transition is measured 500 mV from steady state voltage. 8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW, and BHE/BLE LOW. CE, WE, and BHE/BLE must be LOW to initiate a write. The transition of these signals terminate the write. The input data setup and hold timing is referenced to the leading edge of the signal that terminates the write. 9. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 38-05134 Rev. *L Page 7 of 15 [+] Feedback CY7C1041CV33 Switching Waveforms Figure 3. Read Cycle No. 1 (Address Transition Controlled)[10, 11] tRC RC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Figure 4. Read Cycle No. 2 (OE Controlled)[11, 12] ADDRESS tRC CE tACE OE tDOE BHE, BLE tLZOE tDBE tLZBE DATA OUT VCC SUPPLY CURRENT HIGH IMPEDANCE tLZCE tPU 50% DATA VALID tPD 50% tHZCE tHZBE tHZOE HIGH IMPEDANCE ICC ISB Notes 10. Device is continuously selected. OE, CE, BHE, and/or BLE = VIL. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE transition LOW. Document Number: 38-05134 Rev. *L Page 8 of 15 [+] Feedback CY7C1041CV33 Switching Waveforms (continued) Figure 5. Write Cycle No. 1 (CE Controlled)[13, 14] tWC ADDRESS tSA CE tAW tSCE tHA tPWE WE t BW BHE, BLE tSD DATA IO tHD Figure 6. Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tPWE WE tSCE CE tSD DATA IO tHD tHA Notes 13. Data IO is high impedance if OE, BHE, and/or BLE = VIH. 14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document Number: 38-05134 Rev. *L Page 9 of 15 [+] Feedback CY7C1041CV33 Switching Waveforms (continued) Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW) tWC ADDRESS tSCE CE tAW tSA WE tBW BHE, BLE tPWE tHA tHZWE DATA IO tSD tHD tLZWE Truth Table CE H L OE X L WE X H BLE X L L H L X L L L H L L H X H X X H BHE X L H L L H L X H I/O0 – I/O7 High Z Data Out Data Out High Z Data In Data In High Z High Z High Z I/O8 – I/O15 High Z Data Out High Z Data Out Data In High Z Data In High Z High Z Mode Power Down Read – All Bits Read – Lower Bits Only Read – Upper Bits Only Write – All Bits Write – Lower Bits Only Write – Upper Bits Only Selected, Outputs Disabled Selected, Outputs Disabled Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Document Number: 38-05134 Rev. *L Page 10 of 15 [+] Feedback CY7C1041CV33 Ordering Information Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the list of parts that are currently available.For a complete listing of all options, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. Speed (ns) 8 Ordering Code CY7C1041CV33-8ZSXC Package Diagram Package Type Operating Range Commercial 51-85087 44-pin Thin Small Outline Package Type II (Pb-free) Please contact your local Cypress sales representative for availability of these parts Ordering Code Definitions CY 7C 1 04 1 C V33 - 8 ZS X C Temperature Range: C= Commercial X = Pb-free; X Absent = Leaded Package Type: ZS = 44-pin TSOP II Speed Grade: 8 ns V33 = 3.0 V to 3.6 V Process Technology:C  150 nm Data width: × 16-bits 4-Mbit density Fast Asynchronous SRAM Marketing Code: 7C = SRAMs Company ID: CY = Cypress Document Number: 38-05134 Rev. *L Page 11 of 15 [+] Feedback CY7C1041CV33 Package Diagram Figure 8. 44-pin Thin Small Outline Package Type II, 51-85087 51-85087 *C Document Number: 38-05134 Rev. *L Page 12 of 15 [+] Feedback CY7C1041CV33 Acronyms Acronym CE CMOS FBGA I/O OE SOJ SRAM TSOP TTL WE Chip Enable complementary metal oxide semiconductor fine-pitch ball grid array input/output Output Enable Small Outline J-lead static random access memory thin small outline package transistor-transistor logic Write Enable  ns V µs µA mA mm ms MHz pF % mW W °C Description Document Conventions Units of Measure Symbol ohms nano seconds Volts micro seconds micro Amperes milli Amperes milli meter milli seconds Mega Hertz pico Farad percent milli Watts Watts degree Celcius Unit of Measure Document Number: 38-05134 Rev. *L Page 13 of 15 [+] Feedback CY7C1041CV33 Document History Page Document Title: CY7C1041CV33, 4-Mbit (256 K × 16) Static RAM Document Number: 38-05134 REV. ** *A *B *C *D *E *F *G ECN NO. Issue Date 109513 112440 112859 116477 119797 262949 361795 435387 12/13/01 12/20/01 03/25/02 09/16/02 10/21/02 See ECN See ECN See ECN Orig. of Change HGK BSS DFP CEA DFP RKF SYT NXR New Data Sheet Updated 51-85106 from revision *A to *C Added CY7C1042CV33 in BGA package Removed 1042 BGA option pin ACC Final Data Sheet Add applications foot note to data sheet Added 20-ns speed bin 1) Added Lead (Pb)-Free parts in the Ordering info (Page #9) 2) Added Automotive Specs to Datasheet Added Pb-Free offerings in the Ordering Information Removed -8 Speed bin from Product offering. Corrected typo in description for BHE/BLE in pin definitions table on Page# 3 corrected their Pin name from OE2 to OE. Included the Maximum Ratings for Static Discharge Voltage and Latch up Current. Changed the description of IIX current from Input Load Current to Input Leakage Current Added note# 4 on page# 4 Updated the Ordering Information table Added Automotive-A Operating Range Changed tpower value from 1 s to 100 s Updated Ordering Information table Description of Change *H 499153 See ECN NXR *I *J *K *L 2104110 2897141 3072834 3186840 See ECN 03/22/10 11/12/2010 03/03/2011 VKN/AESA Added Automotive-E specs for 12 ns speed Updated Ordering Information table AJU/VIVG Removed inactive parts. Updated package diagrams. PRAS PRAS Removed inactive parts. Added Ordering Code Definitions on page 11. Updated Features. Updated Selection Guide (Added -8 ns speed grade devices and removed -10 ns, -12 ns, -15 ns and -20 ns speed grade devices). Removed Figure “48-Ball FBGA Pinout (Top View)” and renamed Figure “44-Pin SOJ/TSOP II (Top View)” as “44-pin TSOP II (Top View)” in Pin Configuration. Updated Pin Definitions (Deleted the column “BGA Pin Number” and renamed the column “SOJ, TSOP Pin Number” as “TSOP Pin Number”. Updated Operating Range Updated Electrical Characteristics (Added -8 ns speed grade devices and removed -10 ns, -12 ns, -15 ns and -20 ns speed grade devices). Updated Thermal Resistance (Deleted the columns SOJ and FBGA). Updated Switching Characteristics (Added -8 ns speed grade devices and removed -10 ns, -12 ns, -15 ns and -20 ns speed grade devices). Updated Ordering Information (Added new speed bin (-8 ns speed grade devices) and removed -10 ns, -12 ns, -15 ns and -20 ns speed grade devices). Added Acronyms and Units of Measure. Dislodged Automotive information to new datasheet (001-67307) Removed SOJ and FBGA package related information in all instances in the document. Updated in new template. Document Number: 38-05134 Rev. *L Page 14 of 15 [+] Feedback CY7C1041CV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2001-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05134 Rev. *L Revised March 4, 2011 Page 15 of 15 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback