CY7C1041D-10ZSXI

CY7C1041D 4-Mbit (256K x 16) Static RAM Features • Pin-and function-compatible with CY7C1041B • High speed — tAA = 10 ns • Low active power — ICC = 90 mA @ 10 ns (Industrial) • Low CMOS standby power — ISB2 = 10 mA • 2.0 V Data Retention • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE and OE features • Available in lead-free 44-Lead (400-Mil) Molded SOJ and 44-Pin TSOP II packages Functional Description[1] The CY7C1041D is a high-performance CMOS static RAM organized as 256K words by 16 bits. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1041D is available in a standard 44-pin 400-mil-wide body width SOJ and 44-pin TSOP II package with center power and ground (revolutionary) pinout. Logic Block Diagram Pin Configurations SOJ / TSOPII Top View INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 I/O0–I/O7 I/O8–I/O15 256K x 16 COLUMN DECODER BHE WE CE OE BLE A0 A1 A2 A3 A4 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A14 A13 A12 A11 A10 ROW DECODER Note: 1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com. A9 A10 A 11 A 12 A 13 A14 A15 A16 A17 SENSE AMPS Cypress Semiconductor Corporation Document #: 38-05472 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 31, 2006 [+] [+] Feedback CY7C1041D Selection Guide -10 (Industrial) Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 10 90 10 -12 (Automotive)[2] 12 95 15 Unit ns mA mA Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VCC to Relative GND[3] .... –0.5V to +6.0V DC Voltage Applied to Outputs in High Z State[3] .....................................–0.5V to VCC +0.5V DC Input Voltage[3] ..................................–0.5V to VCC +0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage............. ...............................>2001V (per MIL-STD-883, Method 3015) Latch-up Current...................................................... >200 mA Operating Range Range Industrial Automotive Ambient Temperature –40°C to +85°C –40°C to +125°C VCC 5V ± 0.5 5V ± 0.5 Speed 10 ns 12 ns Electrical Characteristics Over the Operating Range -10 (Industrial) Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[3] GND < VOUT < VCC, Output Disabled 100 MHz 83 MHz 66 MHz 40 MHz ISB1 Automatic CE Power-Down Current —TTL Inputs Automatic CE Power-Down Current —CMOS Inputs Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f=0 Input Leakage Current GND < VI < VCC Output Leakage Current 2.0 –0.5 –1 –1 Test Conditions VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA Min. 2.4 0.4 VCC + 0.5 0.8 +1 +1 90 80 70 60 20 2.0 –0.5 –1 –1 Max. -12 (Automotive) Min. 2.4 0.4 VCC + 0.5 0.8 +1 +1 95 85 75 25 Max. Unit V V V V µA µA mA mA mA mA mA VCC Operating Supply VCC = Max., Current f = fMAX = 1/tRC ISB2 10 15 mA Capacitance[4] Parameter CIN COUT Description Input Capacitance I/O Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 8 8 Unit pF pF Notes: 2. Automotive product information is Preliminary. 3. VIL (min.) = –2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns. 4. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05472 Rev. *C Page 2 of 9 [+] [+] Feedback CY7C1041D Thermal Resistance[4] Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient)[4] Thermal Resistance (Junction to Case)[4] Test Conditions Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board SOJ Package TSOP II Package 57.91 36.73 50.66 17.17 Unit °C/W °C/W AC Test Loads and Waveforms[5] 10 ns device Z = 50Ω 3.0V 50 Ω OUTPUT ALL INPUT PULSES 90% 10% (b) 90% 10% ≤ 3 ns 30 pF* GND ≤ 3 ns * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 1.5V (a) High-Z Characteristics: 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 255Ω (c) R1 481 Ω Equivalent to: THÉVENIN EQUIVALENT 167Ω 1.73V OUTPUT Switching Characteristics[6] Over the Operating Range -10 (Industrial) Parameter Read Cycle tpower tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE VCC(typical) to the First Access[7] Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z CE HIGH to High Z [8, 9] -12 (Automotive) Min. 100 12 Max. Unit µs ns 12 3 12 6 0 6 3 6 0 12 6 0 6 ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. 100 10 Max. 10 3 10 5 0 5 3 5 0 10 5 0 5 CE LOW to Low Z[9] [8, 9] CE LOW to Power-Up CE HIGH to Power-Down Byte Enable to Data Valid Byte Enable to Low Z Byte Disable to High Z Notes: 5. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load shown in Figure (c) 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 7. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 8. tHZOE, tHZCE, tHZBE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of AC Test Loads. Transition is measured when the outputs enter a high impedance state. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, tHZBE is less than tLZBE, and tHZWE is less than tLZWE for any given device. Document #: 38-05472 Rev. *C Page 3 of 9 [+] [+] Feedback CY7C1041D Switching Characteristics[6] Over the Operating Range(continued) -10 (Industrial) Parameter Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW [10, 11] -12 (Automotive) Min. 12 10 10 0 0 10 7 0 3 Max. Unit ns ns ns ns ns ns ns ns ns 6 10 ns ns Description Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z[9] WE LOW to High Z[8, 9] Byte Enable to End of Write Min. 10 7 7 0 0 7 6 0 3 Max. 5 7 Data Retention Characteristics Over the Operating Range Parameter VDR ICCDR ICCDR tCDR[4] tR[12] Description VCC for Data Retention Data Retention Current Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC = VDR = 2.0V, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V Ind’l Auto 0 tRC Conditions[13] Min. 2.0 10 15 Max. Unit V mA mA ns ns Data Retention Waveform DATA RETENTION MODE VCC CE 4.5V tCDR VDR > 2V 4.5V tR Switching Waveforms Read Cycle No. 1[13, 14] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Notes: 10. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. 11. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 12. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 µs or stable at VCC(min.) > 50 µs 13. No input may exceed VCC + 0.5V 14. Device is continuously selected. OE, CE, BHE, and/or BHE = VIL. Document #: 38-05472 Rev. *C Page 4 of 9 [+] [+] Feedback CY7C1041D Switching Waveforms (continued) Read Cycle No. 2 (OE Controlled) [15,16] ADDRESS tRC CE tACE OE BHE, BLE tDOE tLZOE tDBE tLZBE DATA OUT VCC SUPPLY CURRENT HIGH IMPEDANCE tLZCE tPU 50% DATA VALID tPD 50% ISB tHZCE tHZBE tHZOE HIGH IMPEDANCE ICC Write Cycle No. 1 (CE Controlled)[17, 18] tWC ADDRESS CE tSA tSCE tAW tPWE WE tBW BHE, BLE tSD DATAI/O tHD tHA Notes: 15. WE is HIGH for read cycle. 16. Address valid prior to or coincident with CE transition LOW 17. Data I/O is high impedance if OE or BHE and/or BLE= VIH. 18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05472 Rev. *C Page 5 of 9 [+] [+] Feedback CY7C1041D Switching Waveforms (continued) Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tPWE WE tSCE CE tSD DATAI/O tHD tHA Write Cycle No. 3 (WE Controlled, OE HIGH During Write)[16, 17] tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA OE BHE, BLE t DATA I/O NOTE 19 t HZOE SD tHD DATAIN VALID Note: 19. During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05472 Rev. *C Page 6 of 9 [+] [+] Feedback CY7C1041D Switching Waveforms (continued) Write Cycle No. 4 (WE Controlled, OE LOW) BHE, BLE ADDRESS tWC CE tSCE tAW tSA WE tBW BHE, BLE tHZWE DATA I/O NOTE 19 tSD tHD tPWE tHA tLZWE Truth Table CE H L L L L L L L OE X L L L X X X H WE X H H H L L L H BLE X L L H L L H X BHE X L H L L H L X I/O0–I/O7 High Z Data Out Data Out High Z Data In Data In High Z High Z I/O8–I/O15 High Z Data Out High Z Data Out Data In High Z Data In High Z Power Down Read All bits Read Lower bits only Read Upper bits only Write All bits Write Lower bits only Write Upper bits only Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 10 12 Ordering Code CY7C1041D-10VXI CY7C1041D-10ZSXI CY7C1041D-12VXE CY7C1041D-12ZSXE Package Diagram 51-85082 51-85087 51-85082 51-85087 Package Type 44-Lead (400-Mil) Molded SOJ (Pb-Free) 44-Lead TSOP Type II (Pb-Free) 44-Lead (400-Mil) Molded SOJ (Pb-Free) 44-Lead TSOP Type II (Pb-Free) Automotive Operating Range Industrial Please contact your local Cypress sales representative for availability of these parts. Document #: 38-05472 Rev. *C Page 7 of 9 [+] [+] Feedback CY7C1041D Package Diagrams 44-Lead (400-Mil) Molded SOJ (51-85082) 51-85082-*B 44-Pin TSOP II (51-85087) 51-85087-*A All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05472 Rev. *C Page 8 of 9 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] [+] Feedback CY7C1041D Document History Page Document Title: CY7C1041D 4-Mbit (256K x 16) Static RAM Document Number: 38-05472 REV. ** *A *B ECN NO. 201560 233729 351117 Orig. of Issue Date Change See ECN See ECN See ECN SWI RKF PCI Description of Change Advance Datasheet for C9 IPP 1.AC, DC parameters are modified as per EROS (Spec #01-2165) 2.Pb-free offering in the ‘ordering information’ Changed from Advance to Preliminary Removed 17 and 20 ns Speed bin Added footnote # 4 Redefined ICC values for Com’l and Ind’l temperature ranges ICC (Com’l): Changed from 67 and 54 mA to 75 and 70 mA for 12 and 15 ns speed bins respectively ICC (Ind’l): Changed from 80, 67 and 54 mA to 90, 85 and 80 mA for 10, 12 and 15 ns speed bins respectively Changed footnote # 10 on tR Changed tSCE from 8 to 7 ns for 10 ns speed bin Added Static Discharge Voltage and latch-up current spec Added VIH(max) spec in footnote # 2 Changed reference voltage level for measurement of Hi-Z parameters from ±500 mV to ±200 mV Added Write Cycle (WE Controlled, OE HIGH During Write) Timing Diagram Changed part names from Z to ZS in the Ordering Information Table Removed L-Version Added 10 ns parts in the Ordering Information Table Added Lead-Free Ordering Information Shaded Ordering Information Table Converted Preliminary to Final Removed -15 speed bin Removed Commercial Operating Range product information Added Automotive Operating Range product information Changed Maximum Rating for supply voltage from 7V to 6V Updated Thermal Resistance table Changed tHZWE from 6 ns to 5 ns Updated footnote #8 on High-Z parameter measurement Updated the Ordering Information and replaced Package Name column with Package Diagram in the Ordering Information table *C 446328 See ECN NXR Document #: 38-05472 Rev. *C Page 9 of 9 [+] [+] Feedback