CY7C1041DV33-10BVI

THIS SPEC IS OBSOLETE Spec No: 38-05473 Spec Title: CY7C1041DV33, 4-MBIT (256K X 16) STATIC RAM Replaced by: None CY7C1041DV33 4-Mbit (256K × 16) Static RAM 4-Mbit (256K × 16) Static RAM Features Functional Description ■ Temperature ranges ❐ Industrial: –40 °C to 85 °C The CY7C1041DV33 is a high performance CMOS Static RAM organized as 256K words by 16-bits. To write to the device, take chip enable (CE) and write enable (WE) inputs LOW. If byte low enable (BLE) is LOW, then data from I/O pins (I/O0 to I/O7) is written into the location specified on the address pins (A0 to A17). If byte high enable (BHE) is LOW, then data from I/O pins (I/O8 to I/O15) is written into the location specified on the address pins (A0 to A17). ■ Pin and function compatible with CY7C1041CV33 ■ High speed ❐ tAA = 10 ns ■ Low active power ❐ ICC = 90 mA ■ Low CMOS standby power ❐ ISB2 = 10 mA ■ 2.0 V data retention ■ Automatic power-down when deselected ■ TTL compatible inputs and outputs ■ Easy memory expansion with CE and OE features ■ Available in Pb-free 48-ball VFBGA, 44-pin (400-mil) molded SOJ, and 44-pin TSOP II Packages To read from the device, take chip enable (CE) and output enable (OE) LOW while forcing the write enable (WE) HIGH. If BLE is LOW, then data from the memory location specified by the address pins appears on I/O0 to I/O7. If BHE is LOW, then data from memory appears on I/O8 to I/O15. See the Truth Table on page 11 for a complete description of read and write modes. The input and output pins (I/O0 to I/O15) are placed in a high impedance state when the device is deselected (CE HIGH), outputs are disabled (OE HIGH), BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). The CY7C1041DV33 is available in a standard 44-pin 400-mil wide SOJ and 44-pin TSOP II package with center power and ground (revolutionary) pinout and a 48-ball FBGA package. For a complete list of related documentation, click here. Logic Block Diagram 256K × 16 SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 ROW DECODER INPUT BUFFER I/O0–I/O7 I/O8–I/O15 A9 A10 A 11 A 12 A 13 A14 A15 A16 A17 COLUMN DECODER Cypress Semiconductor Corporation Document Number: 38-05473 Rev. *O • 198 Champion Court BHE WE CE OE BLE • San Jose, CA 95134-1709 • 408-943-2600 Revised November 8, 2016 CY7C1041DV33 Contents Selection Guide ................................................................ 3 Pin Configuration ............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 DC Electrical Characteristics .......................................... 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 AC Switching Characteristics ......................................... 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 11 Document Number: 38-05473 Rev. *O Ordering Information ...................................................... 12 Ordering Code Definitions ......................................... 12 Package Diagrams .......................................................... 13 Acronyms ........................................................................ 15 Document Conventions ................................................. 15 Units of Measure ....................................................... 15 Document History Page ................................................. 16 Sales, Solutions, and Legal Information ...................... 18 Worldwide Sales and Design Support ....................... 18 Products .................................................................... 18 PSoC® Solutions ...................................................... 18 Cypress Developer Community ................................. 18 Technical Support ..................................................... 18 Page 2 of 18 CY7C1041DV33 Selection Guide Description -10 (Industrial) Unit Maximum access time 10 ns Maximum operating current 90 mA Maximum CMOS standby current 10 mA Pin Configuration Figure 1. 48-ball VFBGA (Pinout 1) [1, 2] 1 2 3 4 5 6 BLE OE A0 A1 A2 NC I/O0 BHE A3 A4 CE I/O1 I/O2 A5 A6 I/O10 VSS I/O3 A17 VCC I/O4 I/O6 Figure 2. 48-ball VFBGA (Pinout 2) [1, 2] 1 2 3 4 5 6 A BLE OE A0 A1 A2 NC A I/O8 B I/O8 BHE A3 A4 CE I/O0 B I/O9 C I/O9 I/O10 A5 A6 I/O1 I/O2 C A7 I/O11 VCC D VSS I/O11 A17 A7 I/O3 VCC D NC A16 I/O12 VSS E VCC I/O12 NC A16 I/O4 VSS E I/O5 A14 A15 I/O13 I/O14 F I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O7 NC A12 A13 WE I/O15 G I/O15 NC A12 A13 WE I/O7 G NC A8 A9 A10 A11 NC H NC A8 A9 A10 A11 NC H Figure 3. 44-pin SOJ/TSOP II pinout A0 A1 A2 A3 A4 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A14 A13 A12 A11 A10 Notes 1. NC pins are not connected on the die. 2. Pinout 1 is compliant with CY7C1041CV33 and pinout 2 is JEDEC compliant. The difference between the two is that the higher and lower byte I/Os (I/O[7:0] and I/O[15:8] balls) are swapped. Document Number: 38-05473 Rev. *O Page 3 of 18 CY7C1041DV33 DC input voltage [3] ............................. –0.3 V to VCC + 0.3 V Maximum Ratings Current into outputs (LOW) ........................................ 20 mA Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Static discharge voltage (MIL-STD-883, method 3015) ................................. > 2001 V Storage temperature ................................ –65 C to +150 C Latch up current ..................................................... > 200 mA Ambient temperature with power applied ................................... –55 C to +125 C Operating Range Supply voltage on VCC relative to GND [3] ...–0.3 V to +4.6 V DC voltage applied to outputs in high Z State [3] ................................ –0.3 V to VCC + 0.3 V Range Industrial Ambient Temperature VCC Speed –40 C to +85 C 3.3 V  0.3 V 10 ns DC Electrical Characteristics Over the Operating Range Parameter Description -10 (Industrial) Test Conditions VOH Output HIGH voltage VCC = Min, IOH = –4.0 mA VOL Output LOW voltage VCC = Min, IOL = 8.0 mA VIH[3] VIL[3] Min Max Unit 2.4 – V – 0.4 V Input HIGH voltage 2.0 VCC + 0.3 V Input LOW voltage –0.3 0.8 V IIX Input leakage current GND < VI < VCC –1 +1 A IOZ Output leakage current GND < VOUT < VCC, output disabled –1 +1 A ICC VCC operating supply current VCC = Max, f = fMAX = 1/tRC 100 MHz – 90 mA 83 MHz – 80 mA 66 MHz – 70 mA 40 MHz – 60 mA ISB1 Automatic CE power-down current – TTL inputs Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX – 20 mA ISB2 Automatic CE power-down current – CMOS inputs Max VCC, CE > VCC – 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V, f=0 – 10 mA Note 3. Minimum voltage is –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns. Document Number: 38-05473 Rev. *O Page 4 of 18 CY7C1041DV33 Capacitance Parameter [4] Description CIN Input capacitance COUT I/O capacitance Test Conditions Max Unit 8 pF 8 pF TA = 25 C, f = 1 MHz, VCC = 3.3 V Thermal Resistance Parameter [4] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions Still Air, soldered on a 3 × 4.5 inch, four layer printed circuit board 48-ball FBGA Package 44-pin SOJ Package 44-pin TSOP II Unit Package 27.89 57.91 50.66 C/W 14.74 36.73 17.17 C/W AC Test Loads and Waveforms The AC test loads and waveform diagram follows. Figure 4. AC Test Loads and Waveforms [5] 10 ns device Z = 50  50  * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT ALL INPUT PULSES 3.0 V OUTPUT 30 pF* GND 90% 90% 10% 10% 1.5 V Rise Time: 1 V/ns (b) Fall Time: 1 V/ns (a) High Z Characteristics R 317 3.3 V OUTPUT R2 351 5 pF (c) Notes 4. Tested initially and after any design or process changes that may affect these parameters. 5. AC characteristics (except high Z) are tested using the load conditions shown in Figure 4 (a). High Z characteristics are tested for all speeds using the test load shown in Figure 4 (c). Document Number: 38-05473 Rev. *O Page 5 of 18 CY7C1041DV33 Data Retention Characteristics Over the Operating Range Parameter Conditions[6] Description VDR VCC for data retention ICCDR Data retention current tCDR[7] Chip deselect to data retention time tR[8] Operation recovery time VCC = VDR = 2.0 V, CE > VCC – 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V Min Max Unit 2.0 – V – 10 0 – ns tRC – ns mA Data Retention Waveform Figure 5. Data Retention Waveform DATA RETENTION MODE VCC 3.0 V VDR > 2 V tCDR 3.0 V tR CE Notes 6. No input may exceed VCC + 0.3 V. 7. Tested initially and after any design or process changes that may affect these parameters. 8. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s. Document Number: 38-05473 Rev. *O Page 6 of 18 CY7C1041DV33 AC Switching Characteristics Over the Operating Range Parameter [9] Description -10 (Industrial) Min Max Unit Read Cycle tpower[10] VCC(Typical) to the first access 100 – s tRC Read cycle time 10 – ns tAA Address to data valid – 10 ns tOHA Data hold from address change 3 – ns tACE CE LOW to data valid – 10 ns tDOE OE LOW to data valid – 5 ns 0 – ns – 5 ns 3 – ns – 5 ns 0 – ns tLZOE OE LOW to low Z[11] Z[11, 12] tHZOE OE HIGH to high tLZCE CE LOW to low Z[11] Z[11, 12] tHZCE CE HIGH to high tPU CE LOW to power-up tPD CE HIGH to power-down – 10 ns tDBE Byte enable to data valid – 5 ns tLZBE Byte enable to low Z 0 – ns Byte disable to high Z – 6 ns tHZBE Write Cycle[13, 14] tWC Write cycle time 10 – ns tSCE CE LOW to write end 7 – ns tAW Address setup to write end 7 – ns tHA Address hold from write end 0 – ns tSA Address setup to write start 0 – ns tPWE WE pulse width 7 – ns tSD Data setup to write end 5 – ns tHD Data hold from write end 0 – ns tLZWE WE HIGH to low Z[11] 3 – ns – 5 ns 7 – ns [11, 12] tHZWE WE LOW to high Z tBW Byte enable to end of write Notes 9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 10. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access is performed. 11. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, tHZBE is less than tLZBE, and tHZWE is less than tLZWE for any given device. 12. tHZOE, tHZCE, tHZBE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of Figure 4. Transition is measured when the outputs enter a high impedance state. 13. The internal write time of the memory is defined by the overlap of CE LOW and BHE or BLE, and WE LOW. All signals must be in valid states to initiate a Write, but any one signal can go inactive to terminate the write. 14. The minimum write cycle time for Write Cycle No. 4 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 38-05473 Rev. *O Page 7 of 18 CY7C1041DV33 Switching Waveforms Figure 6. Read Cycle No. 1 [15, 16] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 7. Read Cycle No. 2 (OE Controlled) [16, 17] ADDRESS tRC CE tACE OE tHZOE tDOE BHE, BLE tLZOE tHZCE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZBE DATA VALID HIGH IMPEDANCE tPD tPU 50% 50% IICC CC IISB SB Notes 15. Device is continuously selected. OE, CE, BHE, and BLE = VIL. 16. WE is HIGH for read cycle. 17. Address valid prior to or coincident with CE transition LOW. Document Number: 38-05473 Rev. *O Page 8 of 18 CY7C1041DV33 Switching Waveforms (continued) Figure 8. Write Cycle No. 1 (CE Controlled) [18, 19] tWC ADDRESS CE tSA tSCE tAW tHA tPWE WE tBW BHE, BLE tSD tHD DATAI/O Figure 9. Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tHA tPWE WE tSCE CE tSD tHD DATAI/O Notes 18. Data I/O is high impedance if OE or BHE and BLE = VIH. 19. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document Number: 38-05473 Rev. *O Page 9 of 18 CY7C1041DV33 Switching Waveforms (continued) Figure 10. Write Cycle No. 3 (WE Controlled, OE HIGH During Write) [20, 21] tWC ADDRESS tSCE CE tHA tAW tPWE tSA WE OE BHE, BLE t SD DATA I/O NOTE 22 tHD DATAIN VALID t HZOE Figure 11. Write Cycle No. 4 (WE Controlled, OE LOW) tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE DATA I/O tSD tHD NOTE 22 tLZWE Notes 20. Data I/O is high impedance if OE or BHE and BLE = VIH. 21. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. 22. During this period the I/Os are in the output state and input signals should not be applied. Document Number: 38-05473 Rev. *O Page 10 of 18 CY7C1041DV33 Truth Table CE H OE X WE X BLE X BHE X I/O0–I/O7 I/O8–I/O15 High Z High Z Mode Power down Power Standby (ISB) L L H L L Data out Data out Read all bits Active (ICC) L L H L H Data out High Z Read lower bits only Active (ICC) L L H H L High Z Data out Read upper bits only Active (ICC) L X L L L Data in Data in Write all bits Active (ICC) L X L L H Data in High Z Write lower bits only Active (ICC) L X L H L High Z Data in Write upper bits only Active (ICC) L H H X X High Z High Z Selected, outputs disabled Active (ICC) L X X H H High Z High Z Selected, outputs disabled Active (ICC) Document Number: 38-05473 Rev. *O Page 11 of 18 CY7C1041DV33 Ordering Information Speed (ns) 10 Ordering Code CY7C1041DV33-10BVI Package Diagram Package Type 51-85150 48-ball VFBGA Pinout - 1[23] CY7C1041DV33-10BVXI 48-ball VFBGA (Pb-free) Pinout - 1[23] CY7C1041DV33-10BVJXI 48-ball VFBGA (Pb-free) Pinout - 2[23] CY7C1041DV33-10VXI 51-85082 44-pin (400-mil) Molded SOJ (Pb-free) CY7C1041DV33-10ZSXI 51-85087 44-pin TSOP II (Pb-free) Operating Range Industrial Contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions CY 7 C 1 04 1 D V33 - 10 XXX X I Temperature Range: I = Industrial Pb-free Package Type: xxx = BV or BVJ or V or ZS BV = 48-ball VFBGA Pinout - 1 BVJ = 48-ball VFBGA Pinout - 2 V = 44-pin (400-mil) Molded SOJ ZS = 44-pin TSOP II Speed: 10 ns V33 = Voltage range (3 V to 3.6 V) Process Technology: D = C9, 90 nm Technology Data Width: 1 = Data width × 16-bits Density: 04 = 4-Mbit density Family Code: 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Note 23. Pinout 1 is compliant with CY7C1041CV33 and pinout 2 is JEDEC compliant. The difference between the two is that the higher and lower byte I/Os (I/O[7:0] and I/O[15:8] balls) are swapped. Document Number: 38-05473 Rev. *O Page 12 of 18 CY7C1041DV33 Package Diagrams Figure 12. 48-ball VFBGA (6 × 8 × 1 mm) BV48/BZ48 Package Outline, 51-85150 51-85150 *H Document Number: 38-05473 Rev. *O Page 13 of 18 CY7C1041DV33 Package Diagrams (continued) Figure 13. 44-pin Molded SOJ (400-mil) V44.4 Package Outline, 51-85082 51-85082 *E Figure 14. 44-pin TSOP Z44-II Package Outline, 51-85087 51-85087 *E Document Number: 38-05473 Rev. *O Page 14 of 18 CY7C1041DV33 Acronyms Acronym Document Conventions Description Units of Measure CE Chip Enable CMOS Complementary Metal Oxide Semiconductor °C degree Celsius FBGA Fine-Pitch Ball Grid Array MHz megahertz I/O Input/Output µA microampere OE Output Enable µs microsecond SOJ Small Outline J-lead mA milliampere mm millimeter ns nanosecond pF picofarad V volt W watt SRAM Static Random Access Memory TSOP Thin Small Outline Package TTL Transistor-Transistor Logic VFBGA Very Fine-Pitch Ball Grid Array WE Write Enable Document Number: 38-05473 Rev. *O Symbol Unit of Measure Page 15 of 18 CY7C1041DV33 Document History Page Document Title: CY7C1041DV33, 4-Mbit (256K × 16) Static RAM Document Number: 38-05473 Rev. ECN No. Orig. of Change Submission Date ** 201560 SWI See ECN Advance Data sheet for C9 IPP *A 233729 RKF See ECN 1.AC, DC parameters are modified as per EROS(Spec # 01-2165) 2.Pb-free offering in the ‘Ordering information’ *B 351117 PCI See ECN Changed from Advance to Preliminary Removed 15 and 20 ns Speed bin Corrected DC voltage (min) value in maximum ratings section from - 0.5 to - 0.3V Redefined ICC values for Com’l and Ind’l temperature ranges ICC (Com’l): Changed from 100, 80 and 67 mA to 90, 80 and 75 mA for 8, 10 and 12ns speed bins respectively ICC (Ind’l): Changed from 80 and 67 mA to 90 and 85 mA for 10 and 12ns speed bins respectively Added Static Discharge Voltage and latch-up current spec Added VIH(max) spec in Note# 2 Changed Note# 4 on AC Test Loads Changed reference voltage level for measurement of Hi-Z parameters from 500 mV to 200 mV Added Data Retention Characteristics/Waveform and footnote # 11, 12 Added Write Cycle (WE Controlled, OE HIGH During Write) Timing Diagram Changed Package Diagram name from 44-Pin TSOP II Z44 to 44-Pin TSOP II ZS44 and from 44-Pin (400-mil) Molded SOJ V34 to 44-Pin (400-mil) Molded SOJ V44 Changed part names from Z to ZS in the Ordering Information Table Added 8 ns Product Information Added Pin-Free Ordering Information Shaded Ordering Information Table *C 446328 NXR See ECN Converted from Preliminary to Final Removed -8 speed bin Removed Commercial Operating Range product information Included Automotive Operating Range product information Updated Thermal Resistance table Updated footnote #8 on High-Z parameter measurement Updated the ordering information and replaced Package Name column with Package Diagram in the Ordering Information Table Document Number: 38-05473 Rev. *O Description of Change Page 16 of 18 CY7C1041DV33 Document History Page (continued) Document Title: CY7C1041DV33, 4-Mbit (256K × 16) Static RAM Document Number: 38-05473 Rev. ECN No. Orig. of Change Submission Date Description of Change *D 480177 VKN See ECN Added -10BVI product ordering code in the Ordering Information table *E 2541850 VKN / PYRS 07/22/08 Added -10BVJXI part *F 2752971 VKN 08/18/2009 Added Automotive-A information For 12 ns speed, changed ISB1 spec from 25 mA to 15 mA For 12 ns speed, changed tDOE and tDBE specs from 6 ns to 7 ns Updated ordering information table *G 3034079 PRAS 09/20/2010 Added Ordering Code Definitions. Added Acronyms and Units of Measure. Minor edits *H 3082285 HRP 11/09/2010 Corrected typo in Note 20. *I 3149096 AJU 01/24/2011 No technical updates. *J 3182129 HRP 03/02/2011 No technical updates. *K 3271586 PRAS 06/01/2011 Updated Features (Dislodged automotive part information to 001-69789). Updated Functional Description (Removed “For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.”). Updated Selection Guide (Dislodged automotive part information to 001-69789). Updated Operating Range (Dislodged automotive part information to 001-69789). Updated DC Electrical Characteristics (Dislodged automotive part information to 001-69789). Updated AC Switching Characteristics (Dislodged automotive part information to 001-69789). Updated Data Retention Characteristics (Dislodged automotive part information to 001-69789). Updated Truth Table. Updated Ordering Information (Dislodged automotive part information to 001-69789). Updated to new template. *L 3438781 TAVA 11/15/2011 Updated Package Diagrams. *M 4170254 MEMJ 10/22/2013 Updated Package Diagrams: spec 51-85150 – Changed revision from *G to *H. spec 51-85082 – Changed revision from *D to *E. spec 51-85087 – Changed revision from *D to *E. Updated to new template. *N 4578500 MEMJ 12/16/2014 Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. Updated AC Switching Characteristics: Updated Note 13. *O 5514203 VINI 11/08/2016 Obsolete document. Completing Sunset Review. Document Number: 38-05473 Rev. *O Page 17 of 18 CY7C1041DV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2004-2016. 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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05473 Rev. *O Revised November 8, 2016 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 18 of 18