CY7C1041G
CY7C1041GE
4-Mbit (256K words × 16 bit) Static RAM
with Error-Correcting Code (ECC)
4-Mbit (256K words × 16 bit) Static RAM with Error-Correcting Code (ECC)
Features
■
High speed
❐ tAA = 10 ns/15 ns
■
Embedded ECC for single-bit error correction[1]
■
Low active and standby currents
❐ Active current: ICC = 38-mA typical
❐ Standby current: ISB2 = 6-mA typical
Data writes are performed by asserting the Chip Enable (CE) and
Write Enable (WE) inputs LOW, while providing the data on I/O0
through I/O15 and address on A0 through A17 pins. The Byte High
Enable (BHE) and Byte Low Enable (BLE) inputs control write
operations to the upper and lower bytes of the specified memory
location. BHE controls I/O8 through I/O15 and BLE controls I/O0
through I/O7.
■
Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and
4.5 V to 5.5 V
■
1.0-V data retention
■
TTL-compatible inputs and outputs
Data reads are performed by asserting the Chip Enable (CE) and
Output Enable (OE) inputs LOW and providing the required
address on the address lines. Read data is accessible on the I/O
lines (I/O0 through I/O15). Byte accesses can be performed by
asserting the required byte enable signal (BHE or BLE) to read
either the upper byte or the lower byte of data from the specified
address location.
■
Error indication (ERR) pin to indicate 1-bit error detection and
correction
All I/Os (I/O0 through I/O15) are placed in a high-impedance state
during the following events:
■
Pb-free 44-pin SOJ, 44-pin TSOP II, and 48-ball VFBGA
packages
Functional Description
CY7C1041G and CY7C1041GE are high-performance CMOS
fast static RAM devices with embedded ECC. Both devices are
offered in single chip-enable option and in multiple pin
configurations. The CY7C1041GE device includes an ERR pin
that signals an error-detection and correction event during a read
cycle.
■
The device is deselected (CE HIGH)
■
The control signals (OE, BLE, BHE) are de-asserted
On the CY7C1041GE devices, the detection and correction of a
single-bit error in the accessed location is indicated by the
assertion of the ERR output (ERR = HIGH)[1]. See the Truth
Table on page 14 for a complete description of read and write
modes.
The logic block diagram is on page 2.
Product Portfolio
Product [2]
Features and Options (see Pin
Configurations on page 4)
CY7C1041G(E)18 Single Chip Enable
CY7C1041G(E)30
CY7C1041G(E)
Optional ERR pins
Power Dissipation
Speed
Operating
ICC, (mA)
(ns)
Standby, ISB2
(mA)
f = fmax
10/15
[3]
[3]
Typ
Max
Typ
Max
Range
VCC Range
(V)
Industrial
1.65 V–2.2 V
15
–
40
2.2 V–3.6 V
10
38
45
4.5 V–5.5 V
10
38
45
6
8
Notes
1. This device does not support automatic write-back on error detection.
2. The ERR pin is available only for devices which have ERR option “E” in the ordering code. Refer Ordering Information on page 15 for details.
3. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for a VCC range of 1.65 V–2.2 V),
VCC = 3 V (for a VCC range of 2.2 V–3.6 V), and VCC = 5 V (for a VCC range of 4.5 V–5.5 V), TA = 25 °C.
Cypress Semiconductor Corporation
Document Number: 001-91368 Rev. *M
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 9, 2017
CY7C1041G
CY7C1041GE
Logic Block Diagram – CY7C1041G
ECC DECODER
ROW DECODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
INPUT BUFFER
SENSE
AMPLIFIERS
ECC ENCODER
MEMORY
ARRAY
I/O0‐I/O7
I/O8‐I/O15
A10
A11
A12
A13
A14
A15
A16
A17
COLUMN DECODER
BHE
WE
CE
OE
BLE
Logic Block Diagram – CY7C1041GE
ECC DECODER
MEMORY
ARRAY
INPUT BUFFER
SENSE
AMPLIFIERS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
ROW DECODER
ECC ENCODER
ERR
I/O0‐I/O7
I/O8‐I/O15
A10
A11
A12
A13
A14
A15
A16
A17
COLUMN DECODER
BHE
WE
CE
OE
BLE
Document Number: 001-91368 Rev. *M
Page 2 of 21
CY7C1041G
CY7C1041GE
Contents
Pin Configurations ........................................................... 4
Maximum Ratings ............................................................. 6
Operating Range ............................................................... 6
DC Electrical Characteristics .......................................... 6
Capacitance ...................................................................... 7
Thermal Resistance .......................................................... 7
AC Test Loads and Waveforms ....................................... 7
Data Retention Characteristics ....................................... 8
Data Retention Waveform ................................................ 8
AC Switching Characteristics ......................................... 9
Switching Waveforms .................................................... 10
Truth Table ...................................................................... 14
ERR Output – CY7C1041GE .......................................... 14
Document Number: 001-91368 Rev. *M
Ordering Information ...................................................... 15
Ordering Code Definitions ......................................... 16
Package Diagrams .......................................................... 17
Acronyms ........................................................................ 19
Document Conventions ................................................. 19
Units of Measure ....................................................... 19
Document History Page ................................................. 20
Sales, Solutions, and Legal Information ...................... 21
Worldwide Sales and Design Support ....................... 21
Products .................................................................... 21
PSoC® Solutions ...................................................... 21
Cypress Developer Community ................................. 21
Technical Support ..................................................... 21
Page 3 of 21
CY7C1041G
CY7C1041GE
Pin Configurations
Figure 1. 48-ball VFBGA (6 × 8 × 1.0 mm) Single Chip Enable Figure 2. 48-ball VFBGA (6 × 8 × 1.0 mm) Single Chip Enable
without ERR, CY7C1041G [4], Package/Grade ID: BVXI [6]
with ERR, CY7C1041GE [4, 5], Package/Grade ID: BVXI [6]
1
2
BLE
OE
I/O 0
3
4
5
6
A0
A1
A2
NC
BHE
A3
A4
CE
I/O 1
I/O2
A5
A6
VSS
I/O3
A17
VCC
I/O4
I/O 6
1
2
A
BLE
OE
I/O8
B
I/O0
I/O10
I/O9
C
A7
I/O11
VCC
D
NC
A 16
I/O12
VSS
E
I/O5
A14
A 15
I/O13
I/O14
F
I/O 7
NC
A12
A 13
WE
I/O15
G
NC
A8
A9
A 10
A 11
NC
H
Figure 3. 48-ball VFBGA (6 × 8 × 1.0 mm)
Single Chip Enable without ERR, CY7C1041G [4],
Package/Grade ID: BVJXI [6]
1
2
BLE
OE
I/O8
3
4
5
6
A0
A1
A2
NC
BHE
A3
A4
CE
I/O9
I/O10
A5
A6
VSS
I/O11
A17
VCC
I/O12
I/O14
3
4
5
6
A0
A1
A2
NC
A
BHE
A3
A4
CE
I/O8
B
I/O1
I/O2
A5
A6
I/O10
I/O9
C
VSS
I/O3
A17
A7
I/O11
VCC
D
VCC
I/O4
ERR
A16
I/O12
VSS
E
I/O6
I/O5
A14
A15
I/O13
I/O14
F
I/O7
NC
A12
A13
WE
I/O15
G
NC
A8
A9
A10
A11
NC
H
Figure 4. 48-ball VFBGA (6 × 8 × 1.0 mm)
Single Chip Enable with ERR, CY7C1041GE [4, 5],
Package/Grade ID: BVJXI [6]
1
2
A
BLE
OE
I/O0
B
I/O8
I/O1
I/O2
C
A7
I/O3
VCC
NC
A16
I/O4
I/O13
A14
A15
I/O15
NC
A12
NC
A8
A9
3
4
5
6
A0
A1
A2
NC
A
BHE
A3
A4
CE
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
D
VSS
I/O11
A17
A7
I/O3
VCC
D
VSS
E
VCC
I/O12
ERR
A16
I/O4
VSS
E
I/O5
I/O6
F
I/O14
I/O13
A14
A15
I/O5
I/O6
F
A13
WE
I/O7
G
I/O15
NC
A12
A13
WE
I/O7
G
A10
A11
NC
H
NC
A8
A9
A10
A11
NC
H
Notes
4. NC pins are not connected internally to the die.
5. ERR is an output pin.
6. Package type BVJXI is JEDEC compliant compared to package type BVXI. The difference between the two is that the higher and lower byte I/Os (I/O[7:0] and I/O[15:8]
balls are swapped.
Document Number: 001-91368 Rev. *M
Page 4 of 21
CY7C1041G
CY7C1041GE
Pin Configurations (continued)
Figure 5. 44-pin TSOP II/44-pin SOJ Single Chip Enable with ERR, CY7C1041GE [7, 8]
A0
A1
A2
A3
A4
/CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
/WE
A5
A6
A7
A8
A9
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
44- pin TSOP II36
10
35
11
34
12
33
13
32
14
31
15
30
16
29
17
28
18
27
19
26
20
25
21
24
22
23
A17
A16
A15
/OE
/ BHE
/ BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
ERR
A14
A13
A12
A11
A10
Figure 6. 44-pin TSOP II/44-pin SOJ Single Chip Enable without ERR, CY7C1041G [7]
A0
A1
A2
A3
A4
/CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
/WE
A5
A6
A7
A8
A9
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
44-pin TSOP II 36
10
35
11
34
12
33
13
32
14
31
15
30
16
29
17
28
18
27
19
26
20
25
21
24
22
23
A17
A16
A15
/OE
/BHE
/BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A14
A13
A12
A11
A10
Notes
7. NC pins are not connected internally to the die.
8. ERR is an output pin.
Document Number: 001-91368 Rev. *M
Page 5 of 21
CY7C1041G
CY7C1041GE
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 C to +150 C
Ambient temperature
with power applied ................................... –55 C to +125 C
Supply voltage
on VCC relative to GND [9] .................. –0.5 V to VCC + 0.5 V
DC voltage applied to outputs
in HI-Z State [9] ................................... –0.5 V to VCC + 0.5 V
DC input voltage [9] ............................. –0.5 V to VCC + 0.5 V
Current into outputs (in LOW state) ............................ 20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ................................. > 2001 V
Latch-up current .................................................... > 140 mA
Operating Range
Grade
Industrial
Ambient Temperature
–40 C to +85 C
VCC
1.65 V to 2.2 V,
2.2 V to 3.6 V,
4.5 V to 5.5 V
DC Electrical Characteristics
Over the operating range of –40 C to 85 C
Parameter
VOH
VOL
VIH
VIL
Description
Output HIGH
voltage
Output LOW
voltage
Input HIGH
voltage
Input LOW
voltage
Test Conditions
10 ns/15 ns
Min
Typ [10]
Max
1.65 V to 2.2 V VCC = Min, IOH = –0.1 mA
2.2 V to 2.7 V VCC = Min, IOH = –1.0 mA
1.4
–
–
2
–
–
2.7 V to 3.0 V
VCC = Min, IOH = –4.0 mA
2.2
–
–
3.0 V to 3.6 V
VCC = Min, IOH = –4.0 mA
2.4
–
–
4.5 V to 5.5 V
VCC = Min, IOH = –4.0 mA
2.4
–
–
4.5 V to 5.5 V
VCC = Min, IOH = –0.1 mA
VCC – 0.5 [11]
–
–
–
–
0.2
1.65 V to 2.2 V VCC = Min, IOL = 0.1 mA
2.2 V to 2.7 V VCC = Min, IOL = 2 mA
V
–
–
0.4
2.7 V to 3.6 V
VCC = Min, IOL = 8 mA
–
–
0.4
4.5 V to 5.5 V
VCC = Min, IOL = 8 mA
–
–
0.4
1.4
–
VCC + 0.2 [9]
1.65 V to 2.2 V –
2.2 V to 2.7 V
–
2
–
VCC + 0.3 [9]
2.7 V to 3.6 V
–
2
–
VCC + 0.3 [9]
4.5 V to 5.5 V
–
2
1.65 V to 2.2 V –
–
VCC + 0.5 [9]
–0.2
[9]
–
0.4
[9]
2.2 V to 2.7 V
–
–0.3
–
0.6
2.7 V to 3.6 V
–
–0.3 [9]
–
0.8
–
[9]
–
0.8
4.5 V to 5.5 V
–0.5
Unit
V
V
V
IIX
Input leakage current
GND < VIN < VCC
–1
–
+1
A
IOZ
Output leakage current
GND < VOUT < VCC, Output disabled
–1
–
+1
A
ICC
Operating supply current
Max VCC, IOUT = 0 mA, f = 100 MHz
CMOS levels
f = 66.7 MHz
–
38
45
mA
–
–
40
ISB1
Automatic CE power-down
current – TTL inputs
Max VCC, CE > VIH,
VIN > VIH or VIN < VIL, f = fMAX
–
–
15
mA
ISB2
Automatic CE power-down
current – CMOS inputs
Max VCC, CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0
–
6
8
mA
Notes
9. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V – 2.2 V),
VCC = 3 V (for VCC range of 2.2V – 3.6 V), and VCC = 5 V (for VCC range of 4.5 V – 5.5 V), TA = 25 °C.
11. This parameter is guaranteed by design and not tested.
Document Number: 001-91368 Rev. *M
Page 6 of 21
CY7C1041G
CY7C1041GE
Capacitance
Parameter [12]
Description
CIN
Input capacitance
COUT
I/O capacitance
Test Conditions
48-ball VFBGA
44-pin SOJ
10
10
10
pF
10
10
10
pF
Test Conditions
48-ball VFBGA
44-pin SOJ
Still air, soldered on a 3 ×
4.5 inch, four layer
printed circuit board
31.35
55.37
68.85
C/W
14.74
30.41
15.97
C/W
TA = 25 C, f = 1 MHz,
VCC = VCC(typ)
44-pin TSOP II Unit
Thermal Resistance
Parameter [12]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
44-pin TSOP II Unit
AC Test Loads and Waveforms
Figure 7. AC Test Loads and Waveforms [13]
High-Z Characteristics:
VCC
50
Output
VTH
Z0 = 50
R1
Output
30 pF*
* Including
jig and
scope
(a)
* Capacitive load consists
of all components of the
test environment
R2
5 pF*
(b)
All Input Pulses
VHIGH
GND
90%
90%
10%
Rise Time:
> 1 V/ns
10%
Fall Time:
> 1 V/ns
(c)
Parameters
1.8 V
3.0 V
5.0 V
Unit
R1
1667
317
317
R2
1538
351
351
VTH
0.9
1.5
1.5
V
VHIGH
1.8
3
3
V
Notes
12. Tested initially and after any design or process changes that may affect these parameters.
13. Full-device AC operation assumes a 100-µs ramp time from 0 to VCC(min) and a 100-µs wait time after VCC stabilization.
Document Number: 001-91368 Rev. *M
Page 7 of 21
CY7C1041G
CY7C1041GE
Data Retention Characteristics
Over the operating range of –40 C to 85 C
Parameter
VDR
Description
Conditions
Min
Max
Unit
1
–
V
–
8
mA
0
–
ns
VCC > 2.2 V
10
–
ns
VCC < 2.2 V
15
–
ns
VCC for data retention
[14]
ICCDR
Data retention current
tCDR[15]
Chip deselect to data retention
time
tR[14, 15]
Operation recovery time
VCC = 1.2 V, CE > VCC – 0.2 V ,
VIN > VCC – 0.2 V, or VIN < 0.2 V
Data Retention Waveform
Figure 8. Data Retention Waveform [14]
VCC
VCC(min)
DATA RETENTION MODE
VDR = 1.0 V
tCDR
VCC(min)
tR
CE
Notes
14. Full-device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC (min) > 100 s.
15. These parameters are guaranteed by design.
Document Number: 001-91368 Rev. *M
Page 8 of 21
CY7C1041G
CY7C1041GE
AC Switching Characteristics
Over the operating range of –40 C to 85 C
Parameter [16]
Description
10 ns
15 ns
Min
Max
Min
Max
Unit
Read Cycle
tRC
Read cycle time
10
–
15
–
ns
tAA
Address to data / ERR valid
–
10
–
15
ns
tOHA
Data / ERR hold from address change
3
–
3
–
ns
tACE
CE LOW to data / ERR valid
–
10
–
15
ns
tDOE
OE LOW to data / ERR valid
–
4.5
–
8
ns
0
–
0
–
ns
–
5
–
8
ns
3
–
3
–
ns
–
5
–
8
ns
0
–
0
–
ns
–
10
–
15
ns
tLZOE
tHZOE
OE LOW to low impedance
OE HIGH to HI-Z
[17, 18]
tLZCE
CE LOW to low impedance
tHZCE
CE HIGH to HI-Z [17, 18]
tPU
[17]
CE LOW to power-up
[17]
[18, 17]
[18, 17]
tPD
CE HIGH to power-down
tDBE
Byte enable to data valid
–
4.5
–
8
ns
tLZBE
Byte enable to low impedance [17]
0
–
0
–
ns
–
6
–
8
ns
tHZBE
Write Cycle
Byte disable to HI-Z
[18]
[19, 20]
tWC
Write cycle time
10
–
15
–
ns
tSCE
CE LOW to write end
7
–
12
–
ns
tAW
Address setup to write end
7
–
12
–
ns
tHA
Address hold from write end
0
–
0
–
ns
tSA
Address setup to write start
0
–
0
–
ns
tPWE
WE pulse width
7
–
12
–
ns
tSD
Data setup to write end
5
–
8
–
ns
tHD
Data hold from write end
0
–
0
–
ns
[17]
tLZWE
WE HIGH to low impedance
3
–
3
–
ns
tHZWE
WE LOW to HI-Z [18]
–
5
–
8
ns
tBW
Byte Enable to write end
7
–
12
–
ns
Notes
16. Test conditions assume a signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse
levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3 V). Test conditions for the read cycle use output loading, as shown in part (a) of Figure 7 on page 7, unless specified otherwise
17. tHZOE, tHZCE, tHZWE, tHZBE, tLZOE, tLZCE, tLZWE, and tLZBE are specified with a load capacitance of 5 pF, as shown in part (b) of Figure 7 on page 7. Transition is measured 200 mV from
steady state voltage.
18. These parameters are guaranteed by design and are not tested.
19. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the
HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates
the write.
20. The minimum write cycle pulse width in Write Cycle No 2 (WE Controlled, OE LOW) should be equal to sum of tsdand tHZWE.
Document Number: 001-91368 Rev. *M
Page 9 of 21
CY7C1041G
CY7C1041GE
Switching Waveforms
Figure 9. Read Cycle No. 1 of CY7C1041G (Address Transition Controlled) [21, 22]
tRC
ADDRESS
tAA
tOHA
DATA I/O
PREVIOUS DATAOUT
VALID
DATAOUT VALID
Figure 10. Read Cycle No. 1 of CY7C1041GE (Address Transition Controlled) [21, 22]
tRC
ADDRESS
tAA
tOHA
DATA I/O
PREVIOUS DATAOUT
VALID
DATAOUT VALID
tAA
tOHA
ERR
PREVIOUS ERR VALID
ERR VALID
Notes
21. The device is continuously selected, OE = VIL, CE = VIL, BHE or BLE or both = VIL.
22. WE is HIGH for the read cycle.
Document Number: 001-91368 Rev. *M
Page 10 of 21
CY7C1041G
CY7C1041GE
Switching Waveforms (continued)
Figure 11. Read Cycle No. 2 (OE Controlled) [23, 24]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
t HZOE
tDOE
tLZOE
BHE/
BLE
tDBE
tLZBE
DATA I/O
HIGH IMPEDANCE
t HZBE
DATAOUT VALID
HIGH
IMPEDANCE
tLZCE
tPU
VCC
SUPPLY
CURRENT
ISB
Notes
23. WE is HIGH for the read cycle.
24. Address valid prior to or coincident with CE LOW transition.
Document Number: 001-91368 Rev. *M
Page 11 of 21
CY7C1041G
CY7C1041GE
Switching Waveforms (continued)
Figure 12. Write Cycle No. 1 (CE Controlled) [25, 26]
tW
C
ADDRESS
tS A
tSC E
CE
tA W
tH A
tPW
E
W E
tB W
B H E/
BLE
O E
tHZOE
tH D
tS D
D A T A I /O
D A T AI N
V A L ID
Figure 13. Write Cycle No. 2 (WE Controlled, OE LOW) [25, 26, 27]
tW C
ADDRESS
tSCE
CE
tB W
BHE /
BLE
tA W
tS A
tH A
tPW E
WE
t LZ W E
t HZW E
D A T A I /O
tS D
DATA
tH D
IN
V A L ID
Notes
25. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the
HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates
the write.
26. Data I/O is in HI-Z state if CE = VIH, or OE = VIH, or BHE, and/or BLE = VIH.
27. The minimum write cycle pulse width should be equal to sum of tSD and tHZWE.
Document Number: 001-91368 Rev. *M
Page 12 of 21
CY7C1041G
CY7C1041GE
Switching Waveforms (continued)
Figure 14. Write Cycle No. 3 (BLE or BHE Controlled) [28, 29]
tWC
ADDRESS
t SCE
CE
tAW
tSA
tHA
tBW
BHE /
BLE
t PWE
WE
t HZWE
tHD
tSD
t LZWE
DATA IN VALID
DATA I /O
Figure 15. Write Cycle No. 4 (WE Controlled) [28, 29, 30]
tWC
ADDRESS
tSCE
CE1
CE2
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
tHD
tSD
DATA I/O
NOTE 31
DATA IN VALID
tHZOE
Notes
28. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the
HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates
the write.
29. Data I/O is in HI-Z state if CE = VIH, or OE = VIH, or BHE, and/or BLE = VIH.
30. Data I/O is high impedance if OE = VIH.
31. During this period the I/Os are in output state. Do not apply input signals.
Document Number: 001-91368 Rev. *M
Page 13 of 21
CY7C1041G
CY7C1041GE
Truth Table
CE
OE
WE
BLE
BHE
H
X[32]
X[32]
X[32]
X[32]
L
L
H
L
L
L
H
L
L
L
I/O0–I/O7
I/O8–I/O15
Mode
Power
HI-Z
HI-Z
Power down
Standby (ISB)
L
Data out
Data out
Read all bits
Active (ICC)
L
H
Data out
HI-Z
Read lower bits only
Active (ICC)
H
H
L
HI-Z
Data out
Read upper bits only
Active (ICC)
X
L
L
L
Data in
Data in
Write all bits
Active (ICC)
L
X
L
L
H
Data in
HI-Z
Write lower bits only
Active (ICC)
L
X
L
H
L
HI-Z
Data in
Write upper bits only
Active (ICC)
L
H
H
X
X
HI-Z
HI-Z
Selected, outputs disabled
Active (ICC)
L
X
X
H
H
HI-Z
HI-Z
Selected, outputs disabled
Active (ICC)
ERR Output – CY7C1041GE
Output [33]
0
Mode
Read operation, no single-bit error in the stored data.
1
Read operation, single-bit error detected and corrected.
HI-Z
Device deselected or outputs disabled or Write operation
Notes
32. The input voltage levels on these pins should be either at VIH or VIL.
33. ERR is an Output pin.If not used, this pin should be left floating.
Document Number: 001-91368 Rev. *M
Page 14 of 21
CY7C1041G
CY7C1041GE
Ordering Information
Speed
(ns)
10
Voltage
Range
Ordering Code
2.2 V–3.6 V CY7C1041GE30-10ZSXI
Package Type
(all Pb-free)
51-85087 44-pin TSOP II, ERR output
CY7C1041GE30-10ZSXIT
51-85087 44-pin TSOP II, ERR output, Tape and Reel
CY7C1041G30-10ZSXI
51-85087 44-pin TSOP II
CY7C1041G30-10ZSXIT
51-85087 44-pin TSOP II, Tape and Reel
CY7C1041GE30-10BVXI
51-85150 48-ball VFBGA (6 × 8 × 1.0 mm), ERR output
CY7C1041GE30-10BVXIT
51-85150 48-ball VFBGA (6 × 8 × 1.0 mm), ERR output,
Tape and Reel
CY7C1041G30-10BVXI
51-85150 48-ball VFBGA (6 × 8 × 1.0 mm)
CY7C1041G30-10BVXIT
51-85150 48-ball VFBGA (6 × 8 × 1.0 mm), Tape and Reel
CY7C1041G30-10BVJXI
51-85150 48-ball VFBGA (6 × 8 × 1.0 mm), JEDEC
CY7C1041G30-10BVJXIT
51-85150 48-ball VFBGA (6 × 8 × 1.0 mm), JEDEC,
Tape and Reel
CY7C1041G30-10VXI
51-85082 44-pin SOJ (400 Mils)
CY7C1041G30-10VXIT
51-85082 44-pin SOJ (400 Mils), Tape and Reel
CY7C1041GE30-10VXI
51-85082 44-pin SOJ (400 Mils), ERR output
CY7C1041GE30-10VXIT
51-85082 44-pin SOJ (400 Mils), ERR output,
Tape and Reel
4.5 V–5.5 V CY7C1041G-10ZSXI
15
Package
Diagram
51-85087 44-pin TSOP II, Tape and Reel
CY7C1041GE-10ZSXI
51-85087 44-pin TSOP II, ERR output
CY7C1041GE-10ZSXIT
51-85087 44-pin TSOP II, ERR output, Tape and Reel
CY7C1041GE-10VXI
51-85082 44-pin SOJ (400 Mils), ERR output
CY7C1041GE-10VXIT
51-85082 44-pin SOJ (400 Mils), ERR output,
Tape and Reel
CY7C1041G-10VXI
51-85082 44-pin SOJ (400 Mils)
CY7C1041G-10VXIT
51-85082 44-pin SOJ (400 Mils), Tape and Reel
51-85087 44-pin TSOP II
CY7C1041G18-15ZSXIT
51-85087 44-pin TSOP II, Tape and Reel
CY7C1041G18-15VXI
51-85082 44-pin SOJ (400 Mils)
CY7C1041G18-15VXIT
51-85082 44-pin SOJ (400 Mils), Tape and Reel
CY7C1041G18-15BVXI
51-85150 48-ball VFBGA (6 × 8 × 1.0 mm)
CY7C1041G18-15BVXT
51-85150 48-ball VFBGA (6 × 8 × 1.0 mm), Tape and Reel
Document Number: 001-91368 Rev. *M
Industrial
51-85087 44-pin TSOP II
CY7C1041G-10ZSXIT
1.65 V–2.2 V CY7C1041G18-15ZSXI
Operating
Range
Page 15 of 21
CY7C1041G
CY7C1041GE
Ordering Code Definitions
CY 7 C 1 04 1
G
E
XX - XX XX X
I X
X = blank or T
blank = Bulk; T = Tape and Reel
Temperature Range: I = Industrial
Pb-free
Package Type: XX = ZS or BV or BVJ or V
ZS = 44-pin TSOP II; BV = 48-ball VFBGA;
BVJ = 48-ball VFBGA-JEDEC Compliant; V = 44-pin Molded SOJ
Speed: XX = 10 ns or 15 ns
Voltage Range: XX = 30 or blank or 18
30 = 2.2 V–3.6 V; blank = 4.5 V–5.5 V; 18 = 1.65 V–2.2 V
E = ERR output Single bit error indication
Revision Code “G”: Process Technology = 65 nm
Data Width: 1 = × 16-bits
Density: 04 = 4-Mbit
Family Code: 1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-91368 Rev. *M
Page 16 of 21
CY7C1041G
CY7C1041GE
Package Diagrams
Figure 16. 44-pin TSOP II (Z44) Package Outline, 51-85087
51-85087 *E
Figure 17. 44-pin SOJ (400 Mils) Package Outline, 51-85082
51-85082 *E
Document Number: 001-91368 Rev. *M
Page 17 of 21
CY7C1041G
CY7C1041GE
Package Diagrams (continued)
Figure 18. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150
51-85150 *H
Document Number: 001-91368 Rev. *M
Page 18 of 21
CY7C1041G
CY7C1041GE
Acronyms
Acronym
Document Conventions
Description
Units of Measure
BHE
byte high enable
BLE
byte low enable
°C
Degrees Celsius
CE
chip enable
MHz
megahertz
CMOS
complementary metal oxide semiconductor
A
microamperes
I/O
input/output
s
microseconds
OE
output enable
mA
milliamperes
mm
millimeters
ns
nanoseconds
ohms
%
percent
pF
picofarads
V
volts
W
watts
SRAM
static random access memory
TSOP
thin small outline package
TTL
transistor-transistor logic
VFBGA
very fine-pitch ball grid array
WE
write enable
Document Number: 001-91368 Rev. *M
Symbol
Unit of Measure
Page 19 of 21
CY7C1041G
CY7C1041GE
Document History Page
Document Title: CY7C1041G/CY7C1041GE, 4-Mbit (256K words × 16 bit) Static RAM with Error-Correcting Code (ECC)
Document Number: 001-91368
Rev.
ECN No.
Orig. of
Change
Submission
Date
*F
4867081
NILE
07/31/2015
Changed status from Preliminary to Final.
*G
4876251
NILE
08/07/2015
Updated Ordering Information:
Updated part numbers.
*H
4968879
NILE
10/16/2015
Fixed typo in bookmarks.
*I
5019226
VINI
11/18/2015
Updated Ordering Information:
Updated part numbers.
Description of Change
*J
5122043
NILE
02/02/2016
Updated Truth Table.
*K
5223335
NILE
08/30/2016
Updated DC Electrical Characteristics:
Removed values of VOH parameter corresponding to “2.7 V to 3.6 V” range.
Added values of VOH parameter corresponding to “2.7 V to 3.0 V” and “3.0 V
to 3.6 V” ranges.
Updated Note 9 (Replaced “2 ns” with “20 ns”).
Updated Ordering Information:
Updated part numbers.
Updated to new template.
*L
5655218
NILE
03/09/2017
Updated Logic Block Diagram – CY7C1041G (Updated diagram to change the
devices from Dual Chip enabled to Single Chip enabled).
Updated Logic Block Diagram – CY7C1041GE (Updated diagram to change
the devices from Dual Chip enabled to Single Chip enabled).
Updated to new template.
*M
5731242
GNKK
05/09/2017
Updated the Cypress logo.
Document Number: 001-91368 Rev. *M
Page 20 of 21
CY7C1041G
CY7C1041GE
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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cypress.com/iot
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Cypress Developer Community
Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components
Technical Support
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Wireless Connectivity
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cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2014-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-91368 Rev. *M
Revised May 9, 2017
Page 21 of 21
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